A

REPORT
ON
PRACTICAL TRAINING
TAKEN AT
LINUX SOFT TECHNOLOGIES
PVT. LTD., JAIPUR
Submitted in the Partial Fulfillment of the
Requirements for the
Award of the Degree of
BACHELOR OF TECHNOLOGY
in
ELECTRONICS & COMMUNICATION ENGG.

SESSION 2009-10

Submitted by:-
Ankur Bhat
(B.Tech. VII Sem)
Roll No.-060207

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
Government Engineering College Ajmer
(An Autonomous Institution of Govt. of Rajasthan)
Badaliya Circle, Ajmer-305001
 ACKNOWLEDGEMENT
I am greatly privileged to express my sincere thanks to Mr. Rohit
Gupta, Director, Linux Soft Technologies Pvt. Ltd., Jaipur for the
opportunity he has provided me, and making the requisite facilities readily
available for experimental work.

I feel immensely proud in extending my heartiest thanks to Mr.

Himanshu Bhojwani, Director, Contrivance IT Solutions Pvt. Ltd, for
his inspiring guidance, encouragement, unconditional cooperation and
support, which has greatly contributed towards the successful completion of
this work. He has been a source of inspiration for all of us and his experience
and knowledge has helped us in learning and giving this project the shape it
has assumed.

I offer my heartfelt thanks to Mr. M.C. Govil, Principal,

Government Engineering College, Ajmer and Mr. Dhirendra Mathur,
Training & Placement Officer, Government Engineering College,
Ajmer for providing me an opportunity to undergo this training. I am also
grateful to Mrs. Rekha Mehra, Head of Department, Electronics &
Communication, Government Engineering College, Ajmer for his
proper guidance, encouragement and support. The help by other faculty
members is also greatly acknowledged.

I also wish to thank my family and friends for motivating, encouraging

and giving moral support to accomplish this project successfully.

ANKUR BHAT
 COMPANY PROFILE
Linux Soft Technologies Pvt. Ltd., Jaipur is the Redhat
Authorized training partner, exam centre & Registered with Govt. of
India.They are the leading Training–Solution-Development organization
of Redhat Linux, Oracle, Cisco, Microsoft, Sun Microsystems, VHDL /
VLSI & ROBOMAKING-EMBEDDED SYSTEMS. They have been providing
services in imparting training and solution in Networking domain &
Programming covering LAN, MAN, WAN with the complete offerings in
Internet Security.

Based on their extensive support experience with a variety of

customers, Linux Soft Technologies Pvt. Ltd. has developed a unique
approach for technical support. They offer consulting and planning,
integration and maintenance services for many open source projects,
allowing you to deploy them across your network with complete peace of
mind. With growing popularity and acceptance of Linux, RoboMaking, VLSI,
Oracle, and Routers in the govt. sector we started a company, The Linux
Soft Technologies Pvt. Ltd. to provide all Computer based solutions under
one roof.

Linux Soft Technologies Pvt. Ltd. is

1) An Authorized Redhat Training partner & Exam Centre from
USA, Microsoft Certified Solution Provider (MCSP) & Cisco
Solution Provider.
2) Training, Solution & Development Company Registered by
Govt. of INDIA.

Linux Soft Technologies Pvt. Ltd. is providing Training program on following

Technologies –

 Red Hat Linux – RHCT, RHCE

 Cisco System – CCNA, CCNP, CSPFA

  Microsoft – MCP, MCSA, MCSE 2003, VB.Net, ASP.Net, C#.Net

 CompTia – A+, Network+

 Sun Microsystems – Java, J2EE

 Oracle – Oracle DBA/Developer

 VHDL/VLSI, Robomaking / Embedded Systems

 Security – CEH, CCSA

Linux Soft Technologies Pvt. Ltd. Is providing Solution on following

Technologies –

 Redhat Linux

 Cisco Router – Switch Implementation

 Windows Server Installation & Configuration

 Cisco Pix Firewall Implementation

 Web Hosting, Domain Registration

 Web Site Development, Web Solution

 Software Development

 Electronic Projects

 Database Solution
 PREFACE
This report describes an practical training based on VLSI/VHDL which
was done under the supervision of Mr. Himanshu Bhojwani by a group of
eight Engineering students. The objective of this practical training was to
develop an approach to make VHDL based real time applications working on
digital logics. The hardware and software tools used are those manufactured
and developed by Altera and the VLSI circuit has been designed on a CPLD
kit. A basic understanding of electronic devices, digital electronics and VLSI
software and hardware tools is a pre-requisite.
 CONTENTS
1 INTRODUCTION TO VLSI
1.1 HISTORICAL PERSPECTIVE
1.2 COMPANIES INVOLVED
1.3 ABOUT ALTERA
1.4 METHODS OF DESIGN
1.5 APPLICATION SPECIFIC INTEGRATED CIRCUIT
1.6 PROGRAMMABLE LOGIC DEVICES
2 INTRODUCTION TO VHDL
2.1 NEED OF VHDL
2.2 ADVANTAGES OF VHDL
2.3 DIFFERENCES BETWEEN VHDL AND OTHER PROCEDURAL
LANGUAGES
2.4 CAPABILITIES OF VHDL
2.5 VHDL TERMS
2.6 STYLES OF MODELING
2.7 VHDL DESIGN FLOW
2.8 VHDL BASIC FILE STRUCTURE
2.9 VHDL EXPRESSIONS AND OPERATORS
3 PROGRAMMING IN VHDL
3.1 HALF ADDER
3.2 FULL ADDER
3.3 4-BIT ADDER CUM SUBTRACTOR
3.4 2TO4 DECODER
3.5 4TO1 MULTIPLEXER
3.6 3TO8 DECODER USING 2TO4 DECODER
3.7 D FLIP FLOP
4 COMPONENTS USED IN THE DESIGN
 4.1 RESISTORS
4.2 VARIABLE RESISTORS
4.3 CAPACITORS
4.4 DIODES
4.5 SWITCHES
4.6 TRANSISTORS
4.7 RELAY
4.8 POWER SUPPLY
4.9 PRINTED CIRCUIT BOARD
4.10 ELT II KIT
4.11 SOFTWARE TOOL- QUARTUS II
5 EXPERIENCE DURING TRAINING
6 SUGGESTION FOR IMPROVEMENT & IMPLEMENTATION FOR
STUDENTS
7 BIBLIOGRAPHY

1. INTRODUCTION TO VLSI
In an era of newly emerging technologies demanding fastest possible
operations with minimum possible equipment size, integrated circuit chips
have become a popular choice for developers. Very Large Scale Integration
(VLSI) based on logic density upto about 1,00,000 logic devices per cubic
millimeter, is emerging as the latest trend in IC fabrication.

1.1 Historical Perspective

The electronics industry has achieved a phenomenal growth over the

last few decades, mainly due to the rapid advances in integration
technologies and large-scale systems design. The use of integrated circuits
in high performance computing, telecommunications, and consumer
electronics has been growing at a very fast pace.
Typically, the required computational and information processing power of
these applications is the driving force for the fast development of this field.
The current leading-edge technologies (such as low bit-rate video and
cellular communications) already provide the end-users a certain amount of
processing power and portability. This trend is expected to continue, with
very important implications for VLSI and systems design. One of the most
important characteristics of information services is their increasing need for
very high processing power and bandwidth. The other important
characteristic is that the information services tend to become more
personalized, which means that the information devices must be more
intelligent and also be portable to allow more mobility. This trend towards
portable, distributed system architectures is one of the main driving forces
for system integration, even though it does not preclude a concurrent and
equally important trend towards centralized, highly powerful information
systems such as those required for network computing and video services.

Figure1: Prominent “driving” trends in information service technologies.

As more and more complex functions are required in various data

processing and telecommunications devices, the need to integrate these
functions in a small package is also increasing. The level of integration as
measured by the number of logic gates in a monolithic chip has been
steadily rising for almost three decades, mainly due to the rapid progress in
processing technology and interconnect technology. Table1 shows the
evolution of logic complexity in integrated circuits over the last three
decades, and marks the milestones of each era. Here, a logic block may
contain anywhere from 10 to 100 transistors, depending on the function.

Era Date Complexity

(# of logic blocks per
chip)
Single Transistor 1958 <1
Unit logic (one gate) 1960 1
Multi-function 1962 2-4
Complex function 1964 5-20
Medium Scale Integration (MSI) 1967 20-200
Large Scale Integration (LSI) 1972 200-2000
Very large Scale Integration (VLSI) 1978 2000-20,000
Ultra Large Scale Integration (ULSI) 1989 >20,000
Table 1: Evolution of logic complexity in integrated circuits
 Note that the term VLSI has been used continuously even for chips in
the ULSI (Ultra Large Scale Integration) category, not necessarily abiding by
the distinction in Table 1.

The monolithic integration of a large number of functions on a single

chip usually
provides:
 Less area/volume and therefore, compactness

 Less power consumption

 Less testing requirements at system level

 Higher reliability, mainly due to improved on-chip interconnects

 Higher speed, due to significantly reduced interconnection length

 Significant cost savings

Therefore, the current trend of integration will continue in the

foreseeable future.
Advances in device manufacturing technology allow the steady reduction of
minimum feature size. Nowadays, programmable VLSI devices are also being
manufactured by companies like Xilinx and Altera.

1.2 Companies Involved

Presently, the programmable VLSI are mainly being manufactured by
1. Xilinx
2. Altera

1.3 About Altera

Altera is one of the leading companies involved in the manufacturing of
programmable VLSI devices such as CPLD (Complex Programmable Logic
Devices) and FPGA (Field Programmable Gate Array). They also design
development boards or kits for learners and experimentation purposes.
Other areas of expertise include IP cores (processor/ ASIC core) and add-on
boards for interfacing (USB devices, analog- to-digital converter etc.). The
points of comparison of CPLD and FPGA are tabulated in Table2

.
S.No. CPLD FPGA
1 Complex Programmable Logic Device Field Programmable Gate Array
2 Field Programmable Gate Array Gate density-over 1 lakh devices
3 Non-volatile Volatile
4 Low cost Expensive
5 Slow Fast
6 Not ideal for ASIC design Ideal for ASIC design
7 Ideal for custom solutions Not ideal for custom solutions

Table 2: Comparison of CPLD and FPGA kits

1.4 Methods Of Design

The circuit design on a VLSI kit may be accomplished by any one of the
following
methods:-
(1) Schematic/Block editor
(2) VHDL coding
(3) Verilog coding

Schematic/Block editor

Some softwares like Quartus II provide the facility of schematic

designing of circuit. In this, first the circuit is drawn with the help of various
tools on the design window. Then this design is compiled and pin
assignments are done with reference from manual. A JECDC file is generated
which is programmed into the VLSI chip. This method is a purely hardware
form of circuit design although a software is used as tool because in the final
chip connections are made through hardware implementation.

VHDL Coding

VHDL refers to Very large scale integration Hardware Description

Language. It provides a facility for designing electronic and digital circuits on
chips using software design techniques. VHDL has been explained in detail in
a later section.

Verilog Coding
 It is another programming language for designing hardware using
software design techniques. Despite of having similar applications, VHDL is
more popular at trainee level circuit design.

Kits Used

Altera manufactures the following kits as per their applications :-

1) ELT II (CPLD)
2) ESDK (FPGA)
3) DE I (Codec Development Kit)
In this project ELT II kit has been used.

1.5 Application Specific Integrated Circuit

As the name suggests, ASICs are integrated circuits designed
specifically to perform tasks related to a single application. For example, a
chip designed for use in cellphone is an ASIC. These kind of chips can be
designed by an engineer with no particular knowledge of semiconductor
physics.

● ASIC at its beginning

Initially, the ASIC technology was known as gate array
technology. Ferranti produced the first gate array- ULA (Universal Logic
Array). The later versions were generalized with different base dies
customized by both metal and polysilicon layer. The designer would choose a
manufacturer and implement the design with the tools available with the
designer

● Types of ASIC
1) Full custom ASIC
2) Standard cell based ASIC
3) Gate array based ASIC
4) Programmable ASIC
Standard Cells ASIC
These are designed using cells of transistors already connected and
compactly routed to form higher level functions as flip flops, adders,
counters etc. The designer connects these logic functions and the software
tries to place them on a die and connect them in the most efficient way.
Each cell consists of all the material layers needed to produce the transistors
and connect them. A typical standard cell is shown in the figure. A major
disadvantage of a standard cell ASIC is that the number of gates cannot be
optimized.
 Figure 2: Standard Cell Based ASIC

Masked Gate Array ASIC

It consists of rows and columns of regular transistor structures. The
basic cells or
gates are nothing but the same number of unconnected transistors. Design
is implemented byconnecting these gates according to the circuit
requirements. Lower level logic isimplemented first. In the manufacturing of
gate array, the unrouted die is processed exceptthe last metal layer which
would be done after the design. Although this method providesflexibilty in
connections so that design can be optimized, the process is quite tedious.

Figure 3: Gate Array

● Disadvantages of ASIC

1. Manufacturing process is lengthy and time consuming.

2. Long design time.
3. Design verification is done during final implementation which results in
more bugs.
4. As they are produced in bulk, they are not ideal for custom solutions.
 These disadvantages led to the development of newer and more
evolved
alternatives such as the programmable logic devices.

1.6 Programmable Logic Devices

PLDs are standard ICs available from a standard catalogue and sold in
a very high volume to a variety of customers. As they can be configured as
per specific application demands, so they also belong to the family of ASICs.

Features :-
 No customized mask layers.
 Quick design turnaround.
 Single block of interconnects which are programmable.
 A matrix of logic macro cells.

Hierarchy of Programmable Devices

Where:
PLD=Programmable Logic Device
SPLD= Simple Programmable Logic Device
CPLD= Complex Programmable Logic Device
PROM= Programmable Read Only Memory
PLA= Programmable Logic Array
PAL= Programmable Array Logic

● PROM
 Programmable Read Only Memories are simply memories that
can be inexpensively programmed by the user to contain a specific pattern.
The pattern can be used to represent a microprocessor program, a simple
algorithm or a state machine. PROM could be either OTP (One Time
Programmable) or multiple time programmable (such as EPROM or EEPROM).
Earlier PROMs were meant to be only memory devices. But with their
introduction in market, they were also started being used as programmable
logic devices. A major advantage of PROM is that any process can be stored
whether logical or not, which is not the case with other PLDs.

Demerits of PROM :-
1. Memory locations are wasted.
2. More time consuming process.

● PLA

The Programmable Logic Arrays provide a solution to the speed

and input limitation of PROMs. Inputs are given to AND plane and then
results are derived from OR plane which is explained diagrammatically in
figure 4. Typically, inverters are provided at the inputs and outputs to
provide logical NOT. PLA can implement a large number of functions i.e., all
those which can be resolved in Sum Of Products (SOP) form. The
interconnects between planes and through input and output are defined
using programming. PLAs have more inputs and are faster as compared to
PROM.

Figure 4: PLA Architecture

 ● PAL

Programmable Array Logic comprises of a wide programmable

AND plane with fixed OR plane. Basic logic devices such as multiplexers,
exclusive ORs and latches have to be added separately to inputs and outputs
whereas clocked elements such as flip flops are included. Therefore PAL can
implement a large number of logical functions including clocked sequential
logic needed for state machines. Since it has a fixed OR plane, the
processing is extremely fast. The architecture of Programmable Array Logic
is shown in figure 5.

Figure 5: PAL Architecture

● CPLD

The blind race for bigger (in terms of functions), smaller (in terms
of physical size), faster, more powerful and cheaper devices lead to more
sophisticated PLDs. In 1984, Altera (newly formed) introduced a CPLD based
on a combination of CMOS and EPROM technologies. This new innovation
was found to have tremendous functional density and complexity while
consuming relatively less power. Basing the programmability on EPROM cells
made them ideal for development and prototyping solutions.
 Figure 6: A generic CPLD structure

Figure 7: CPLD Architecture

● FPGA
Field Programmable Gate Array, rather than being structured by
PAL or other programmable devices, is structured very much like a Gate
Array ASIC. Hence it is more suitable for prototyping ASICs. Each FPGA
vendor has its own architecture which is nothing but a variation of the
architecture shown in figure 9. FPGA has configurable logic blocks,
configurable I/O blocks and programmable interconnect. Clock circuitry is
provided within the chip. Two basic programmable elements used in FPGA
are SRAM (for interconnects) and antifuse (for configuration).

Figure 8: A generic FPGA structure

 Figure 9: The key elements forming a simple programmable logic block

2. INTRODUCTION TO VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware
Description Language. In the mid-1980's the U.S. Department of Defense
and the IEEE
sponsored the development of this hardware description language with the
goal to develop very high-speed integrated circuit. It has become now one of
industry's standard languages to describe digital systems. The other widely
used hardware description language is Verilog. Both are powerful languages
that allow us to describe and simulate complex digital systems. A third HDL
is ABEL (Advanced Boolean Equation Language) which was specifically
designed for Programmable Logic Devices (PLD). ABEL is less powerful than
the other two languages and is less popular in industry. This section deals
with VHDL, as described by the IEEE standard 1076-1993.

VHDL is designed to fill a number of needs in the design process. It is

being used
for documentation, verification, and synthesis of large digital designs. Firstly,
it allows
description of the structure of a design i.e. how it is decomposed into sub-
designs, and how those sub-designs are interconnected. Secondly, it allows
the specification of the function of designs using familiar programming
language forms. Thirdly, as a result, it allows a design to be simulated before
being manufactured so that designers can quickly compare alternatives and
test for correctness without the delay and expense of hardware prototyping.
2.1 Need of VHDL

Initially, in the late 1970's the circuit designers worked on Printed

Circuit Boards,
when there was no Hardware Description Language present in the market.
Following were the limitations of PCB's :-
1. For the designing of large circuits we need a large PCB. Suppose if at
that time theyhad to design a microprocessor then they needed a PCB size
equal to the size of atypical college campus, which was not a feasible
approach.
2. The testing of large circuits was not possible because the large
circuits contain lots of gates and the response of each and every gate could
not be checked. So, it was also not a feasible approach.

With the evolution of the HDL the designers have to just write the code
for a particular logic, whether this code is for the simple AND gate or for the
complex microprocessor. The HDL will automatically produce the virtual
hardware description for that particular logic. With the advent of the
synthesis and the simulation tools now it is possible to generate the other
technical details of the circuit also such as timing reports, placing & routing
reports, delay reports etc. It is also possible now to virtually implement and
check the circuit inside that computer. So the HDL has been revolutionary in
the era of electronics technology.

The usage of VHDL is about 60% in the market as compared to verilog

which is
used in 40% applications only. Reason is the user-friendly nature of VHDL.

2.2 Advantages of VHDL

VHDL offers the following advantages:-

Standard: VHDL is an IEEE standard. This reduces confusion and makes
interfaces between tools, companies and products easier. Any development
to the standard would have better chances of lasting longer and have less
chance of becoming obsolete due to incompatibility with others.

Government Support: VHDL is a result of the VHSIC program; hence it is

clear that the US government supports the VHDL standard for electronic
procurement. The department of defense requires contractors to supply
VHDL for all Application Specific Integrated Circuit (ASIC) designs.
Industry Support: With the advent of more powerful and efficient VHDL
tools has come the growing support of the electronics industry. Companies
use VHDL not only with regard to defense contracts, but also for their
commercial designs.

Portability: The same VHDL code can be simulated and used in many
design tools and at different stages of the design process. This reduces
dependency on a set of design tools whose limited capability may not be
competitive in later markets. The VHDL standard also transforms design data
much easier than a design database of a proprietary design tool.
Modeling Capability: VHDL was developed to model all levels of designs,
from electronic boxes to transistors. VHDL can accommodate behavioral
constructs and mathematical routines that describe complex models, such as
queuing networks and analog circuits. It allows use of multiple architectures
and associates with the same design during various stages of the design
process. VHDL can describe low-level transisitors up to very large systems.

Reusability: Certain common designs can be described, verified and

modified slightly in VHDL for future use. This eliminates reading and marking
changes to schematic pages, which is time-consuming and subject to error.

Technology and Foundry Independence: The functionality and behavior

of the design can be described with VHDL and verified, making it foundry and
technology independent. This frees the designer to proceed without having
to wait for the foundry and technology to be selected.

2.3 Differences between VHDL and other

Procedural Languages

 VHDL is a parallel language while C/C++ are sequential languages.

Each statement occuring in VHDL is executed concurrently i.e. all
statements run simultaneously. In C/C++ each statement is executed
in sequential order and its own turn. In VHDL, explicit constructs exist
for explicit sequential steps.

 VHDL is a strongly typed language. It doesn't allow any mismatching of

types, though type conversion is permitted.

 VHDL allows use of explicit time delay, which is not applicable in

procedural language. In procedural languages, the right hand side
value is assigned to the left hand side as soon as the statement is
executed. In VHDL, we have an advantage that we can assign the
computed value to a signal after time delay.
  VHDL model cannot be implemented in real time application directly
like other procedural languages. It is simulated and synthesized using
in-built system clock.

2.4 Capabilities of VHDL

 ● Implementation of any circuit idea like complete robot design.

 ● Microprocessor of your own configuration.
 ● Direct hardware interaction.

2.5 VHDL Terms

Library: Library is a collection of pre-defined keywords and components

defined in it. Library contains all characteristics of all components.

Entity: A hardware abstraction of digital systems is called entity. All designs

are expressed in entities.

Architecture: All entities that can be simulated have architecture

description. The architecture describes the behavior of entity.

Package: A package is a collection of commonly used data types and

subprograms used in a design. Package is just like a tool box that contains
tools used to build designs.

Configuration: A configuration is used to bind a component instance to an

entity architecture pair. A configuration is like parts list for a design.

Bus: The term bus is used to bind a group of signals at one position.

Generic: A generic is a VHDL term for a parameter that passes information

to an entity.

Process: A process is a basic unit of execution in VHDL source code. All

operations that are performed in a simulation of a VHDL description are
broken into single or multiple processes.
2.6 Styles of Modeling
1. Dataflow modeling
2. Behavioral modeling
3. Structural modeling

Dataflow Modeling: In the dataflow style of modeling, we have to know

just about the boolean expressions and how data flows inside the program.

Behavioral Modeling: For programming in the behavioral style of modeling

we have to know about the truth table and behavior of entities in the
program.

Structural Modeling: The structural style of modeling comes into picture

when we have to deal with the bigger projects. The big project is divided into
small modules and we have to design each module separately. At the end of
the project each module is added s the component in the main program, or
in other words, all modules are interfaced with each other in the main
program.

2.7 VHDL DESIGN FLOW

 Initial Design Entry

 Logic Optimization

 Technology Mapping

 Placement

 Routing

 Programming Unit

 Configured FPGA

2.8 Basic Structure of a VHDL file

 A digital system in VHDL consists of a design entity that can contain other
entities that are then considered components of the top-level entity. Each entity is
modeled by an entity declaration and an architecture body. One can consider the
entity declaration as the interface to the outside world that defines the input and
output signals, while the architecture body contains the description of the entity
and is composed of interconnected entities body contains the description of the
entity and is composed of interconnected entities, processes and components, all
operating concurrently, as schematically shown in Figure 2.1 below. In a typical
design there will be many such entities connected together to perform the desired
function.

VHDL uses reserved Key works that cannot be used as signal names or
identifiers. Keywords and user-defined identifiers are case insensitive. Lines with
comments start with two adjacent hyphens (--) and will be ignored by the compiler.
VHDL also ignores line breaks and extra spaces. VHDL is a strongly typed
language which implies that one has always to declare the type of every object that
can have a value, such as signals, constants and variables.

2.9 Expressions and Operators

Expressions in VHDL are much like expressions in other programming

languages. An expression is a formula combining primaries with operators.
Primaries include names of objects, literals function calls and parenthesized
expressions.

The logical operators and, or nand, nor, xor and not operate on values of
type bit or Boolean, and also on one –dimensional arrays of these types. For array
operands, the operation is applied between corresponding elements of each array,
yielding an array of the same length as the result. For bit and

Highest precedence: * * abs not

* / mod rem
+ (sign) -(sign)
+ - &
= /= < < = >>=
Lowest precedence: and or nand nor xor

Boolean operands, and or, nand, and nor are ‘short-circuit’ that is they only
evaluate their right operand if the left operand does not determine the result. So
and and nand only evaluate the right operand if the left operand is false or ‘0’

The relational operators =,/= <,> and > =must have both operands of the
same type, and yield Boolean results. The equality operators (=and /=) can have
operands of any type. For composite types, two values are equal if all of their
corresponding elements are equal. For composite type, two values are equal if all
of their corresponding elements are equal. The remaining operators must have
operands which are scalar types or one-dimensional arrays of discrete types.

The sign operators (+ and -) and the addition (+) and subtraction (-)
operators have their usual meaning on numeric operands. The concatenation
operator (&) operators on one-dimensional arrays to form a new array with the
contents of the right operand following the contents of the left operand. It can also
concatenate a single new element to an array, or two individual elements to form
an array. The concatenation operator is mist commonly used with strings.

The multiplication (*) and division (/) operators work on integer, floating
point and physical types. The modulus (mod) and remainder (rem) operators only
work on integer types. The absolute value (abs) operator only work on any numeric
type. Finally, the exponentiation (**) operator can have an integer or floating point
left operand, but must have an integer right operand. A negative right operand is
only allowed if the left operand is a floating point number.

- - VHDL supports different classes of operators that operate on signals,

variables and constants. The different classes of operators are summarized
below.

The order of precedence is the highest for the operators of class 7, followed
by class 6 the lowest precedence for class 1. Unless parentheses are used, the
operators with the highest precedence are applied first. Operators of the same class
have the same precedence are applied form left to right in an expression. As an
example, consider the following std_ulogic_vectors, X (=’010’), and Z (‘101110’).
The expression
Not X & Y xor Z rol 1

Is equivalent to ((notX) & Y) xor (Z rol 1) = ((101) & 10) xor (0101100) xor
(01011) =11101. The xor is executed on a bit-per-bit basis.

Logical Operators

The logic operators (and, or nand, nor, xor and xnr) are defined for the “bit”
“Boolean” “std_logic” types and their vectors. They are used to define Boolean
logic expression or to perform bit-per-bit operations on arrays of bits. Operations
on arrays of bits. They give a result of the same type as the operand (Bit or
Boolean). These operators can applied to signals, variables and constants.

Notice that the nand and nor operators are not associative. One should use
parentheses in a sequence of nand or nor operators to prevent a syntax error:

X nand Y nand Z will give a syntax error and should be written as (X nand Y)
nand Z.

Relational operators

The relational operators test the relative values of two scalar types and give
and give as result a Boolean output of “TRUE” or FALSE”.

Notice that symbol of the operator “<=” (smaller or equal to ) the same one the
assignment operator used to assign a value to a signal or variable. In the following
examples the first “<=” symbol is the assignment operator. Some examples of
relational operations are:

variable STS :Boolean;

constant A : integer: 24;
constant B_COUNT :integer:=32;
constant C : integer:= 14;

STS <= (A >B_COUNT); - - will assign the value “TRUE” to STS

STS <= ((A > =B_COUNT) or (A > C)); - - will result in “TRUE”
STD <=(std_logic (‘1’, ‘0’, ‘1’) < std_logic (‘0’, ‘1’, ‘1’ ));- - makes STS
“FALSE”

type new_std_logic is (‘0’, ‘1’ ‘Z’, ‘-‘);

variable A1: new_std_logic := ‘1’;
variable A2: new_std_logic:=’Z’;

STD <= (A1 <A2); will result in “TRUE” since ‘1’ occurs to the left of ‘Z’

For discrete array types, the comparison is done on an element –per-element basis,
starting form the left towards the right, as illustrated by the last two examples.

Shift operators

These operators perform a bit-wise shift or rotate operation on a one-

dimensional array of elements of the type bit (or std_logic) or Boolean.

The operand is on the left of the operator and the number (integer) of shifts is on
the right side of the operator. As an example,

Variable NUM1 :bit_vector:= “10010110”;

NUM1 srl 2;

Will result in the number “00100101”.

When a negative integer is given, the opposite action occurs, i.e. a shift to the left
will be a shift to the right. As an example

NUM 1 srl-2 would be equivalent to NUM 1 sll 2 and give the result “01011000”.
Other examples of shift operations are for the bit_vector A = “1010001”

Addition operators

The addition operators are used to perform arithmetic operation (addition

and subtraction) on operands of any numeric type. The concatenation (&) operator
is used to concatenate two vectors together to make a longer one. In order to use
these operators one has to specify the ieee.std_logic_unsigned.all or std_logic_arith
package in addition to the ieee.std_logic_1164 package.

An example of concatenation is the grouping of signals into a single bus [4].

Signal MYBUS :std_logic_vector (15downto 0);
Signal STATUS : std_logic_vector (2downto 0);
Signal RW, CSI, CS2 : std_logic;
Signal MDATA : std_logic_vector (0 to 9);
MYBUS <= STATUS &RW&CS1&SC2&MDATA;
MYARRAY (15 downto 0) <=”1111_1111” & MDATA (2 to 9);
NEWWORD <=’ VHDL” & “93”;
The first example results in filling up the first 8 leftmost bits of MYARRAY with
1’s and the rest with the 8 rightmost bits of MDATA. The last example results in
an array of characters “VHDL93”

Unary operators

The unary operators “+” and “-“are used to specify the sign of a numeric
type. Multiplying operators are used to perform mathematical functions on numeric
types (integer).

The multiplication operator is also defined when one of the operands is a physical
type and the other an integer or real type.

The remainder (rem) and modulus (mod) are defined as follows:

A rem B – (A/B)*B (in which A/B in an integer)

A mod B =A-B*N (in which N is an integer)

The result of the rem operator has the sign of its first operand while the of the mod
operators has sign of the second operand.

Some examples of these operators are given below.

11 rem 4 results in 3
(-11) rem 4 results in-3
9 mod 4 results in 1
7 mod (-4) results in -1 (7-4*2=-1).

Miscellaneous operators

These are the absolute value and exponentiation operators that can be
applied to numeric types. The logical negation (not) results in the inverse polarity
but the same type.

Delays or timing information

Packages (list standard, 1164 packages).

3. PROGRAMMING IN VHDL
3.1 HALF ADDER

--Structural model for Half Adder

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity HA is
port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC);
end HA;
architecture struct of HA is
component myXOR
port(in1,in2:in STD_LOGIC; out1:out STD_LOGIC);
end component;
begin
X1: myXOR port map(A,B,Sum);
Carry<=A and B;
end struct;

3.2 FULL ADDER

--Structural model for Full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FA is
port(x,y,cin:in std_logic; s, cout:out std_logic);
end FA;
architecture struct of FA is
signal s1,c1,c2 :std_logic;
component HA
port(A,B:in STD_LOGIC; sum, Carry:out STD_LOGIC);
end component;
begin
HA1: HA port map(x,y, s1,c1);
HA2: HA port map(s1,cin, s,c2);
cout<=c1 or c2;
end struct;

--VHDL code for DATA FLOW model of Full Adder:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_DF is
port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT);
end FA_DF;
architecture FA_dataflow of FA_DF is
begin
Fs <= Fx XOR Fy XOR Fcin;
Fcout <= (Fx AND Fy) OR (Fx AND Fcin) OR (Fy AND Fcin);
end FA_dataflow;

--VHDL code for BEHAVIORAL model of Full Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA_Bhr is
port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT);
end FA_Bhr;
architecture FA_struct of FA_Bhr is
component HA
port (hx, hy :in BIT; hs, hcout: out BIT);
end component;
signal s1, c1, c2 : BIT;
begin
HA1: HA port map (Fx, Fy, s1, c1);
HA2: HA port map (s1, Fcin, Fs, c2);
Fcout <= c1 OR c2;
end FA_struct;

3.3 4-BIT ADDER CUM SUBTRACTOR

VHDL CODE (Structural):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;//standard library packages
ENTITY addersub4s IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
SEL:IN BIT;
COUT:OUT BIT;
X:OUT BIT_VECTOR(3 DOWNTO 0));//inputs and outputs declaration
END addersub4s;
ARCHITECTURE struc OF addersub4s IS
COMPONENT fa1d
PORT(X,Y,CIN:IN BIT;
S,COUT:OUT BIT);
END COMPONENT;
COMPONENT xor2 //basic components used for realization…
PORT(A,B:IN BIT;C:OUT BIT);
END COMPONENT;
COMPONENT and2bit
PORT(A,B:IN BIT;C:OUT BIT);
END COMPONENT;
COMPONENT invert
PORT(A:IN BIT;B:OUT BIT);
END COMPONENT;
SIGNAL E:BIT_VECTOR(3 DOWNTO 0);
SIGNAL C:BIT_VECTOR(3 DOWNTO 1);
SIGNAL carry,non_sel:BIT;
BEGIN//mapping with basic gates
X0:xor2 PORT MAP(B(0),SEL,E(0));
FA0:fa1d PORT MAP(A(0),E(0),SEL,X(0),C(1));
X1:xor2 PORT MAP(B(1),SEL,E(1));
FA1:fa1d PORT MAP(A(1),E(1),C(1),X(1),C(2));
X2:xor2 PORT MAP(B(2),SEL,E(2));
FA2:fa1d PORT MAP(A(2),E(2),C(2),X(2),C(3));
X3:xor2 PORT MAP(B(3),SEL,E(3));
FA3:fa1d PORT MAP(A(3),E(3),C(3),X(3),carry);
I0:invert PORT MAP(SEL,non_sel);
A0:and2bit PORT MAP(non_sel,carry,COUT);
END struc;

VHDL Code(Dataflow):
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY addersub4d IS
PORT(A,B:IN BIT_VECTOR(3 DOWNTO 0);
SEL:IN BIT;
COUT:OUT BIT;
X:OUT BIT_VECTOR(3 DOWNTO 0));
END addersub4d;
ARCHITECTURE dataflow OF addersub4d IS
BEGIN
PROCESS(A,B,SEL)
VARIABLE S:BIT_VECTOR(3 DOWNTO 0);
VARIABLE C:BIT_VECTOR(4 DOWNTO 0);
BEGIN
C(0):=SEL;
FOR i IN 0 TO 3 LOOP
S(i):=A(i) XOR B(i) XOR C(i) XOR SEL;
C(i+1):=(B(i) XOR SEL) AND A(i);
END LOOP;
COUT<=C(4);
X<=S;
END PROCESS;
END dataflow;

3.4 2 TO 4 DECODER
VHDL code

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY dec24d IS
PORT(A,B,EN_L:IN BIT;
Q0,Q1,Q2,Q3:OUT BIT);
END ENTITY;
ARCHITECTURE dataflow OF dec24d IS
BEGIN
Q0<=(NOT A)AND (NOT B) AND (NOT EN_L);
Q1<=( A)AND (NOT B) AND (NOT EN_L);
Q2<=(NOT A)AND (B) AND (NOT EN_L);
Q3<=(A)AND (B) AND (NOT EN_L);
END dataflow;

3.5 4 TO 1 MULTIPLEXER
VHDL CODE: (behavioral code)
LIBRARY IEEE;//standard library.
USE IEEE.STD_LOGIC_1164.ALL;//importing standard library.
USE IEEE.STD_LOGIC_ARITH.ALL;
//entity declaration
ENTITY 4mux1 IS
PORT(A,B,C,D:IN STD_LOGIC;
S0,S1: IN STD_LOGIC;
Q:OUT STD_LOGIC);
END 4mux1;
//end of entity declaration
ARCHITECTURE behave OF 4mux1 IS
BEGIN
PROCESS(A,B,C,D,S0,S1)//sensitivity list.
BEGIN
IF S0='0' AND S1='0' THEN Q<='A';
ELSIF SO='1' AND S1='0' THEN Q<='B';
ELSIF SO='0' AND S1='1' THEN Q<='C';
ELSE Q<='D';
END IF;
END PROCESS;
END behave;//end of architecture.
3.6 3TO8 DECODER USING 2TO4 DECODER

VHDL CODE:
LIBRARY IEEE;//standard library
USE IEEE.STD_LOGIC_1164.ALL;//importing the libraray
//entity declaration...
ENTITY decoder38 IS
PORT(A,B,C:IN BIT;
Q0,Q1,Q2,Q3,Q4,Q5,Q6,Q7:OUT BIT);
END ENTITY;
//end of entity declaration.
ARCHITECTURE struc OF decoder38 IS
//component declaration..
COMPONENT decoder24 IS
PORT(S0,S1,EN_L:IN BIT;Q0,Q1,Q2,Q3:OUT BIT);
END COMPONENT;
COMPONENT INVERT
PORT(A:IN BIT;B:OUT BIT);
END COMPONENT;
//signal declaration..
SIGNAL CINV:BIT;
BEGIN
I0:INVERT PORT MAP(C,CINV);
D0:decoder24 PORT MAP(A,B,C,Q0,Q1,Q2,Q3);
D1:decoder24 PORT MAP(A,B,CINV,Q4,Q5,Q6,Q7);
END struc;//

3.7 D FLIP FLOP

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ffD IS
PORT(D,CLK,RESET:IN BIT;
Q,QINV:OUT BIT);
END ffD;
ARCHITECTURE behav OF ffD IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL CLK='1' AND CLK 'EVENT;
IF(RESET='1') THEN Q<='0';QINV<='1';
ELSIF D='1' THEN Q<='1';QINV<='0';
ELSE Q<='0';QINV<='1';
END IF;
END PROCESS;
END behav;

4. COMPONENTS USED IN THE DESIGN

4.1 Resistors

Resistors are components that have a predetermined resistance.

Resistance determines how much current will flow through a component.
Resistors are used to control voltages and currents. A very high resistance
allows very little current to flow. Air has very high resistance. Current almost
never flows through air. (Sparks and lightning are brief displays of current
flow through air. The light is created as the current burns parts of the air.) A
low resistance allows a large amount of current to flow. Metals have very low
resistance. That is why wires are made of metal. They allow current to flow
from one point to another point without any resistance. Wires are usually
covered with rubber or plastic. This keeps the wires from coming in contact
with other wires and creating short circuits. High voltage power lines are
covered with thick layers of plastic to make them safe, but they become very
dangerous when the line breaks and the wire is exposed and is no longer
separated from other things by insulation.

Resistance is given in units of ohms. (Ohms are named after Mho

Ohms who played with electricity as a young boy in Germany.) Common
resistor values are from 100 ohms to 100,000 ohms. Each resistor is marked
with colored stripes to indicate its resistance.

4.2 Variable Resistors

Variable resistors are also common components. They have a dial or a

knob that allows you to change the resistance. This is very useful for many
situations. Volume controls are variable resistors. When you change the
volume you are changing the resistance which changes the current. Making
the resistance higher will let less current flow so the volume goes down.
Making the resistance lower will let more current flow so the volume goes up.
The value of a variable resistor is given as its highest resistance value. For
example, a 500 ohm variable resistor can have a resistance of anywhere
between 0 ohms and 500 ohms. A variable resistor may also be called a
potentiometer (pot for short).

4.3 Capacitors

Capacitors are like electron storage banks. If your circuit is running

low, it will deliver electrons to your circuit. Some capacitors are polarized,
meaning current can only flow one direction through them. If a capacitor has
a lead that is longer than the other, assume the longer lead must always
connect to positive.

4.4 Diodes

Diodes are components that allow current to flow in only one direction.
They have a positive side (leg) and a negative side. When the voltage on the
positive leg is higher than on the negative leg then current flows through the
diode (the resistance is very low). When the voltage is lower on the positive
leg than on the negative leg then the current does not flow (the resistance is
very high). The negative leg of a diode is the one with the line closest to it. It
is called the cathode. The positive end is called the anode. Usually when
current is flowing through a diode, the voltage on the positive leg is 0.65
volts higher than on the negative leg

4.5 Switches

Switches are devices that create a short circuit or an open circuit

depending on the position of the switch. For a light switch, ON means short
circuit (current flows through the switch, and lights light up.) When the
switch is OFF, that means there is an open circuit (no current flows, lights go
out. When the switch is ON it looks and acts like a wire. When the switch is
OFF there is no connection.

4.6 Transistor

Transistors are basic components in all of today's electronics. The

transistor has three legs, the Collector (C), Base (B), and Emitter (E).
Sometimes they are labeled on the flat side of the transistor. Transistors
always have one round side and one flat side. If the round side is facing you,
the Collector leg is on the left, the Base leg is in the middle, and the Emitter
leg is on the right.

4.7 Relays

A relay is usually an electromechanical device that is actuated by an

electrical current. The current flowing in one circuit causes the opening or
closing of another circuit Relays are like remote control switches and are
used in many applications because of their relative simplicity, long life, and
proven high reliability. They are used in a wide variety of applications
throughout industry, such as in telephone exchanges, digital computers and
automation systems.

4.8 Power Supply

Power supply can be defined as electronic equipment, which is a stable

source of D.C. power for electronic circuits.

Power supply can be classified into two major categories: -

1 Unregulated power supply
2 Regulated power supply

UNREGULATED POWER SUPPLY:-

These power supplies, supply power to the load but do not take into
variation of power supply output voltage or current with respect to the
change in A.C. mains voltage, load current or temperature variations. In
other words, we can say that the output voltage or current of an
unregulated power supply changes with the change in A.C.mains voltage,
load current and temperature.

REGULATED POWER SUPPLY:-

These power supplies are regulated over the change in source voltage
or load current i.e. its output remain stable.

Regulated power supplies are of two types: -

1 Current regulated power supplies
These are constant current supplies in spite of change in load or
input voltage.
2 Voltage regulated power supplies
 These supplies supply constant output voltage with respect to the
variation in
load or source input voltage.

CIRCUIT OF REGULATED POWER SUPPLY WITH HALF WAVE RECTIFIER

AND IC-7809 AS A REGULATOR:-

Here diode D1, D2, D3 and D4 forms half wave rectifier. Capacitor C1 is
filtering capacitor.IC-7809 is used for voltage regulation. Capacitor C2 is used
for bypassing, if any ripples are present then it eliminates those ripples.
As IC-7809 is used so it gives 9V DC regulated voltage ideally. If we
take 16 volts transformer then we will get 8.97V at output. Thus voltage is
regulated.

4.9 Printed Circuit Boards

The use of miniaturization and sub miniaturization in electronic

equipment design
has been responsible for the introduction of a new technique in inter
component wiring and assembly that is popularly known as printed circuit.
The printed circuit boards (PCBs) consist of an insulating substrate
material with metallic circuitry photo chemically formed upon that substrate.
Thus PCB provides sufficient mechanical support and necessary electrical
connections for an electronic circuit.
Advantages of printed circuit boards: -
1) Circuit characteristics can be maintained without introducing
variations inter
. circuit capacitance .
2) Wave soldering or vapour phase reflow soldering can mechanize
component
wiring and assembly.
3) Mass production can be achieved at lower cost.
4)The size of component assembly can be reduced with corresponding
decrease
in weight.
5) Inspection time is reduced as probability of error is eliminated.

Types of PCB’s: -

There are four major types of PCB’s: -

 Single sided PCB: - In this, copper tracks are on one side of the board,
and are the simplest form of PCB. These are simplest to
manufacture thus have low production cost.
 Double sided PCB:- In this, copper tracks are provided on both sides of
the substrate. To achieve the connections between the boards, hole
plating is done, which increase the manufacturing complexity.
 Multilayered PCB: - In this, two or more pieces of dielectric substrate
material with circuitry formed upon them are stacked up and bonded
together. Electrically connections are established from one side to the
other and to the layer circuitry by drilled holes, which are subsequently
plated through copper.
 Flexible PCB: - Flexible circuit is basically a highly flexible variant of the
conventional rigid printed circuit board theme.

PCB Manufacturing Process: -

There are a number of different processes, which are used to
manufacture a PCB, which is ready for component assembly, from a copper
clad base material. These processes are as follows
 Preprocessing: - This consists of initial preparation of a copper clad
laminate ready for subsequent processing. Next is to drill tooling
holes. Passing a board through rollers performs cleaning operation.
 Photolithography: - This process for PCBs involves the exposure of a
photo resist material to light through a mask. This is used for defining
copper track and land patterns.
  Etching: - The etching process is performed by exposing the surface of
the board to an etchant solution which dissolves away the exposed
copper areas .The different solutions used are: FeCl3, CuCl3, etc.
 Drilling: - Drilling is used to create the component lead holes and
through holes in a PCB .The drilling can be done before or after the
track areas have been defined.
 Solder Masking: - It is the process of applying organic coatings
selectively to those areas where no solder wettings is needed .The
solder mask is applied by screenprinting.
 Metal Plating: - The plating is done to ensure protection of the copper
tracks and establish connection between different layers of multilayer
boards. PCBs are stacked before being taken for final assembly of
components .The PCB should retain its solder ability.
 Bare-Board Testing: - Each board needs to ensure that the required
connections exist, that there are no short circuits and holes are
properly placed .The testing usually consists of visual inspection and
continuity testing.

4.10 Entry Level Tool II Kit

The Entry Level Tool - II is a MAX II CPLD (EPM240/570) based board

which serves as the basic tool for understanding and experimenting with
Programmable Logic Devices, namely the MAX II Family, and hence the name
Entry Level Tool - II or ELT-II for short. The ELT-II Board helps in
understanding the basic Programmable Logic Design flow in the simplest
manner. This board contains a number of user IOs for easy access and
experimentation.

FEATURES:-
 • Based on MAX II CPLD EPM240T100Cx.
 • 41 General Purpose IOs (+5V tolerant) available on the standard
Santa Cruz short expansion footprint.
 • 10 CPLD clock selection option available through jumper selection
along with the dual crystal support on the board, making the clock
selection choices 10x2 = 20 (2 Hz upto 230.4 Khz).
 • 4-Digit scanning 7-Segment LED Display Interface.
 • 8x2 On-Off Push Button switches shared with IO headers, giving
flexibility of additional 16 general purpose IOs (+5V tolerant).
 • 4x4 Momentary Push Button Switch Matrix and 8 LEDs shared and
configured through 4 Jumper selection options to use them in any of
the possible available combinations.
BLOCK DIAGRAM:-

ELT II BOARD- TOP VIEW

BOARD COMPONENTS
4.11 Software Tool: Quartus II

The software tool used for hardware design of the project was Quartus
II. It is a tool provided by Altera to design and simulate VLSI circuits through
simple schematic design or by using hardware description languages such as
VHDL and Verilog. In this project we have used schematic design technique
for circuit design. After design and simulation on Quartus, the circuit can be
downloaded as a '.bdf' file on the ELT II board.

5. EXPERIENCE DURING TRAINING

Practical training provides a great learning experience with regard to
implementation of theoretical knowledge in real-world applications.
Furthermore, a course in VLSI/VHDL based systems gave us additional
knowledge on how these techniques are implemented since our University
curriculum imbibes only basics of CMOS IC fabrication and not its
implementation in VLSI circuit design.

During training, we underwent a basic course on VLSI technology as it is

prevalent in the world market. We also learnt basic VHDL programming and
attended lectures on basic electronics and digital electronics, which are
indispensable for Electronics Engineering students.

We were a team of six students, having a hands-on experience on

technology, we also learnt working in a team and creating a congenial
environment for higher efficiency as a human resource.

6. SUGGESTIONS FOR IMPROVEMENT

&
IMPLEMENTATION FOR STUDENTS

This training programme provided the best it could , taking into account the
time and resource limitations. However, the quality could be improved by
increasing the time duration of such summer training programmes. Also, the
companies should be transparent in their strategies so that the students can
choose the programme best suited to their requirements.

The students can implement such training for getting hands-on experience
over the theoretical knowledge acquired by them throughout their degree
and inculcating values like team spirit and professionalism.
7. BIBLIOGRAPHY
1. Principles of CMOS VLSI Design by Neil H. Weste and Kamran Eshraghian.
2. VHDL Programming by Example by Douglas L. Perry.
3. Entry Level Tool II – Reference Manual provided by System Level Solutions,
Inc.
(USA).