CD54HC273, CD74HC273,

CD54HCT273, CD74HCT273
Data sheet acquired from Harris Semiconductor
SCHS174B
High-Speed CMOS Logic
February 1998 - Revised May 2003 Octal D-Type Flip-Flop with Reset

Features Description
• Common Clock and Asynchronous Master Reset The ’HC273 and ’HCT273 high speed octal D-Type flip-flops
with a direct clear input are manufactured with silicon-gate
[ /Title • Positive Edge Triggering
CMOS technology. They possess the low power consumption
(CD74 • Buffered Inputs of standard CMOS integrated circuits.
HC273 • Fanout (Over Temperature Range) Information at the D inputis transferred to the Q outputs on
, - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads the positive-going edge of the clock pulse. All eight flip-flops
CD74 - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
HCT27 • Wide Operating Temperature Range . . . -55oC to 125oC independent of the clock. All eight Q outputs are reset to a
3) • Balanced Propagation Delay and Transition Times logic 0.
/Sub- Ordering Information
• Significant Power Reduction Compared to LSTTL
ject Logic ICs
(High PART NUMBER TEMP. RANGE (oC) PACKAGE
• HC Types
Speed - 2V to 6V Operation CD54HC273F3A -55 to 125 20 Ld CERDIP
CMOS - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC273E -55 to 125 20 Ld PDIP
Logic at VCC = 5V
CD74HC273M -55 to 125 20 Ld SOIC
Octal • HCT Types
CD74HC273M96 -55 to 125 20 Ld SOIC
D- - 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, CD54HCT273F3A -55 to 125 20 Ld CERDIP
Type VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT273E -55 to 125 20 Ld PDIP
Flip- - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HCT273M -55 to 125 20 Ld SOIC

CD74HCT273M96 -55 to 125 20 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.

Pinout
CD54HC273, CD54HCT273
(CERDIP)
CD74HC273, CD74HCT273
(PDIP, SOIC)
TOP VIEW
MR 1 20 VCC
Q0 2 19 Q7
D0 3 18 D7
D1 4 17 D6
Q1 5 16 Q6
Q2 6 15 Q5
D2 7 14 D5
D3 8 13 D4
Q3 9 12 Q4
GND 10 11 CP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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 CD54/74HC273, CD54/74HCT273

Functional Diagram
CLOCK
CP

D0 Q0

D1 Q1

D2 Q2

D3 Q3
DATA DATA
INPUTS OUTPUTS
D4 Q4

D5 Q5

D6 Q6

D7 Q7

RESET MR

TRUTH TABLE

INPUTS OUTPUT

RESET (MR) CLOCK CP DATA Dn Q

L X X L

H ↑ H H

H ↑ L L

H L X Q0

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to
High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established.

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 CD54/74HC273, CD54/74HCT273

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJC (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage VIL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
-5.2 6 5.48 - - 5.34 - 5.2 - V
TTL Loads
Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage VIL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
5.2 6 - - 0.26 - 0.33 - 0.4 V
TTL Loads
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND

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DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage VIL
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage VIL
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 2) -2.1 5.5
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

MR 1.5

Data 0.4

CP 1.5
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Maximum Clock Frequency fMAX - 2 6 - - 5 - 4 - MHz
(Figure 1)
4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz
MR Pulse Width tW - 2 60 - - 75 - 90 - ns
(Figure 1)
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns

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 CD54/74HC273, CD54/74HCT273

Prerequisite For Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Clock Pulse Width (Figure 1) tW - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
Set-up Time Data to Clock tSU - 2 60 - - 75 - 70 - ns
(Figure 5)
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
Hold Time, Data to Clock tH - 2 3 - - 3 - 3 - ns
(Figure 5)
4.5 3 - - 3 - 3 - ns
6 3 - - 3 - 3 - ns
Removal Time, MR to Clock tREM - 2 50 - - 65 - 75 - ns
4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
HCT TYPES
Maximum Clock Frequency fMAX - 4.5 25 - - 20 - 16 - MHz
(Figure 2)
MR Pulse Width tw - 4.5 12 - - 15 - 18 - ns
(Figure 2)
Clock Pulse Width (Figure 2) tw - 4.5 20 - - 25 - 30 - ns
Set-up Time Data to Clock tSU - 4.5 12 - - 15 - 18 - ns
(Figure 6)
Hold Time, Data to Clock tH - 4.5 3 - - 3 - 3 - ns
(Figure 6)
Removal Time, MR to Clock tREM - 4.5 10 - - 13 - 15 - ns

Switching Specifications Input tr, tf = 6ns

-55oC TO
25oC -40oC TO 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS

HC TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 2 - 150 190 225 ns
Clock to Output
(Figure 3) 4.5 - 30 38 45 ns

6 - 26 30 38 ns

CL = 15pF 5 12 - - - ns

Propagation Delay, tPHL CL = 50pF 2 - 150 190 225 ns

MR to Output
(Figure 3) 4.5 - 30 38 45 ns

6 - 26 30 38 ns

Output Transition Time tTLH, tTHL CL = 50pF 2 - 75 95 110 ns

(Figure 3)
4.5 - 15 19 22 ns

6 - 13 16 19 ns

Input Capacitance CI - - - 10 10 10 pF

Maximum Clock Frequency fMAX CL = 15pF 5 60 - - - MHz

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 CD54/74HC273, CD54/74HCT273

Switching Specifications Input tr, tf = 6ns (Continued)

-55oC TO
25oC -40oC TO 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS

Power Dissipation CPD - 5 25 - - - pF

Capacitance
(Notes 3, 4)

HCT TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 4.5 - 30 38 45 ns
Clock to Output (Figure 4)
CL = 15pF 5 12 - - - ns

Propagation Delay, tPHL CL = 50pF 4.5 - 32 40 48 ns

MR to Output (Figure 4)

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - 15 19 22 ns

Input Capacitance CIN - - - 10 10 10 pF

Maximum Clock Frequency fMAX CL = 15pF 5 50 - - - MHz

Power Dissipation CPD - 5 25 - - - pF

Capacitance
(Notes 3, 4)

NOTES:
3. CPD is used to determine the dynamic power consumption, per flip-flop.
4. PD = CPD VCC2 fi + ∑ (CL VCC2 + fO) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply
Voltage.

Test Circuits and Waveforms

I
I tWL + tWH =
tWL + tWH = trCL = 6ns fCL
trCL tfCL fCL tfCL = 6ns

VCC 3V
90% 2.7V
CLOCK 50% CLOCK 1.3V
50% 50% 1.3V 1.3V
10% 10% GND 0.3V 0.3V GND

tWL tWH tWL tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%. accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH PULSE WIDTH

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

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Test Circuits and Waveforms (Continued)

trCL tfCL trCL tfCL

VCC 3V
90% CLOCK 2.7V
CLOCK 50% 1.3V
INPUT 10% INPUT 0.3V
GND GND

tH(H) tH(L) tH(H) tH(L)

VCC 3V
DATA
DATA 50% 1.3V 1.3V 1.3V
INPUT INPUT
GND GND
tSU(H) tSU(L) tSU(H) tSU(L)

tTLH tTHL tTLH tTHL

90% 90%
90% 90%
50% 1.3V
OUTPUT OUTPUT 1.3V
10% 10%
tPLH tPHL tPLH tPHL

tREM tREM
VCC 3V
SET, RESET 50% SET, RESET 1.3V
OR PRESET OR PRESET
GND GND

IC IC
CL CL
50pF 50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS