CD54HC153, CD74HC153,

CD54HCT153, CD74HCT153
Data sheet acquired from Harris Semiconductor
SCHS151C
High-Speed CMOS Logic
September 1997 - Revised October 2003 Dual 4- to 1-Line Selector/Multiplexer

Features Description
• Common Select Inputs The ’HC153 and ’HCT153 are dual 4- to 1-line
selector/multiplexers that select one of four sources for each
[ /Title • Separate Enable Inputs
section by the common select inputs, S0 and S1. When the
(CD74H • Buffered inputs and Outputs enable inputs (1E, 2E) are HIGH, the outputs are in the LOW
C153, state.
• Fanout (Over Temperature Range)
CD74H - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Ordering Information
CT153) - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
/Subject • Wide Operating Temperature Range . . . -55oC to 125oC
TEMP. RANGE
PART NUMBER (oC) PACKAGE
(High
• Balanced Propagation Delay and Transition Times
Speed CD54HC153F3A -55 to 125 16 Ld CERDIP
CMOS • Significant Power Reduction Compared to LSTTL
CD54HCT153F3A -55 to 125 16 Ld CERDIP
Logic ICs
Logic
• HC Types CD74HC153E -55 to 125 16 Ld PDIP
Dual 4-
Input - 2V to 6V Operation CD74HC153M -55 to 125 16 Ld SOIC
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
CD74HC153MT -55 to 125 16 Ld SOIC
VCC = 5V
• HCT Types CD74HC153M96 -55 to 125 16 Ld SOIC

- 4.5V to 5.5V Operation CD74HCT153E -55 to 125 16 Ld PDIP

- Direct LSTTL Input Logic Compatibility,
CD74HCT153M -55 to 125 16 Ld SOIC
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH CD74HCT153MT -55 to 125 16 Ld SOIC

CD74HCT153M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.

Pinout
CD54HC153, CD54HCT153
(CERDIP)
CD74HC153, CD74HCT153
(PDIP, SOIC)
TOP VIEW

1E 1 16 VCC

S1 2 15 2E

1I3 3 14 S0

1I2 4 13 2I3

1I1 5 12 2I2
1I0 6 11 2I1

1Y 7 10 2I0

GND 8 9 2Y

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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 CD54HC153, CD74HC153, CD54HCT153, CD74HCT153

Functional Diagram
1
1E
6
1I0
5
1I1 7
4 SEL/MUX 1Y
1I2
3
1I3
14
S0
2
S1
10
2I0
11
2I1 9
12 SEL/MUX 2Y
2I2
13
2I3
15 GND = 8
2E VCC = 16

TRUTH TABLE

SELECT INPUTS DATA INPUTS ENABLE OUTPUT

S1 S0 I0 I1 I2 I3 E Y

X X X X X X H L

L L L X X X L L

L L H X X X L H

L H X L X X L L

L H X H X X L H

H L X X L X L L

H L X X H X L H

H H X X X L L L

H H X X X H L H

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

NOTE: Select inputs S1 and S0 are common to both sections.

2
 CD54HC153, CD74HC153, CD54HCT153, CD74HCT153

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DC Output Diode Current, IOK Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only)
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND

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 CD54HC153, CD74HC153, CD54HCT153, CD74HCT153

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 2) -2.1 5.5
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

Data 0.45

Enable 0.6

Select 1.35

NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g.

360µA max at 25oC.

Switching Specifications Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay (Figure 1) tPLH, CL = 50pF 2 - - 160 - 200 - 240 ns
tPHL
S to Y 4.5 - - 32 - 40 - 48 ns
CL =15pF 5 - 13 - - - - - ns
CL = 50pF 6 - - 27 - 34 - 41 ns

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 CD54HC153, CD74HC153, CD54HCT153, CD74HCT153

Switching Specifications Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
I to Y tPLH, CL = 50pF 2 - - 145 - 180 - 220 ns
tPHL
4.5 - - 29 - 36 - 44 ns
CL =15pF 5 - 12 - - - - - ns
CL = 50pF 6 - - 25 - 31 - 38 ns
E to Y tPLH, CL = 50pF 2 - 120 - 150 - 180 ns
tPHL
4.5 - 24 - 30 - 36 ns
CL =15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 20 - 26 - 31 ns
Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 - 110 ns
(Figure 1)
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CIN - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - 5 - 45 - - - - - pF
(Notes 3, 4)
HCT TYPES
Propagation Delay (Figure 2) tPLH,
S to Y tPHL CL = 50pF 4.5 - - 34 - 43 - 51 ns
CL =15pF 5 - 14 - - - - ns
I to Y tPLH, CL = 50pF 4.5 - - 24 - 30 - 36 ns
tPHL
CL =15pF 5 - 9 - - - - - ns
I to Y tPLH, CL = 50pF 4.5 - 34 - 43 - 51 ns
tPHL
CL =15pF 5 - 14 - - - - - ns
E to Y tPLH, CL = 50pF 4.5 - - 27 - 34 - 41 ns
tPHL
CL =15pF 5 - 11 - - - - ns
Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CIN - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance CPD - 5 - 45 - - - - - pF
(Notes 3, 4)
NOTES:
3. CPD is used to determine the dynamic power consumption, per multiplexer.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuit and Waveform

tr = 6ns tf = 6ns

E
90%
VS
I OR S 10%

VS
OUTPUT Y
tPLH tPHL

FIGURE 1. PROPAGATION DELAY TIMES

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 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9050501MEA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9050501ME Samples
& Green A
CD54HCT153F3A
CD54HC153F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8409301EA Samples
& Green CD54HC153F3A
CD54HCT153F3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9050501ME Samples
& Green A
CD54HCT153F3A
CD74HC153E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC153E Samples

CD74HC153EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC153E Samples

CD74HC153M OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HC153M

CD74HC153M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC153M Samples

CD74HCT153E ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT153E Samples

CD74HCT153EE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT153E Samples

CD74HCT153M OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HCT153M

CD74HCT153M96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HCT153M Samples

CD74HCT153MT OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 HCT153M

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC153, CD54HCT153, CD74HC153, CD74HCT153 :

• Catalog : CD74HC153, CD74HCT153

• Military : CD54HC153, CD54HCT153

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC153M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT153M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC153M96 SOIC D 16 2500 353.0 353.0 32.0
CD74HCT153M96 SOIC D 16 2500 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC153E N PDIP 16 25 506 13.97 11230 4.32
CD74HC153E N PDIP 16 25 506 13.97 11230 4.32
CD74HC153EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HC153EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HCT153E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT153E N PDIP 16 25 506 13.97 11230 4.32
CD74HCT153EE4 N PDIP 16 25 506 13.97 11230 4.32
CD74HCT153EE4 N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
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