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    Negative Setup and Hold Times

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    Aman Arora
    Negative hold time means an input can change before the clock edge and the old level will still be recognized, due to internal data delay. Negative setup time means an input can change after the clock edge and the new level will be recognized, due to internal clock delay. Both are illustrated by a D flip-flop example where the input level 1 ns before or after the clock edge, respectively, determines the output if the input is stable at that time.

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    Negative Setup and Hold Times

    Uploaded by

    Aman Arora
    3K views2 pages
    Negative hold time means an input can change before the clock edge and the old level will still be recognized, due to internal data delay. Negative setup time means an input can change after the clock edge and the new level will be recognized, due to internal clock delay. Both are illustrated by a D flip-flop example where the input level 1 ns before or after the clock edge, respectively, determines the output if the input is stable at that time.

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    Negative hold time means an input can change before the clock edge and the old level will still be recognized, due to internal data delay. Negative setup time means an input can change after the clock edge and the new level will be recognized, due to internal clock delay. Both are illustrated by a D flip-flop example where the input level 1 ns before or after the clock edge, respectively, determines the output if the input is stable at that time.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    3K views2 pages

    Negative Setup and Hold Times

    Uploaded by

    Aman Arora
    Negative hold time means an input can change before the clock edge and the old level will still be recognized, due to internal data delay. Negative setup time means an input can change after the clock edge and the new level will be recognized, due to internal clock delay. Both are illustrated by a D flip-flop example where the input level 1 ns before or after the clock edge, respectively, determines the output if the input is stable at that time.

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    NegativeSetupandHoldTimes

    Inadigitalcircuit,theholdtimeistheminimumtimethataninputsignalmustremain stableaftertheactiveedgeoftheclockinordertoassurethatthatinputiscorrectly recognized. Ifacircuithasanegativeholdtime,thismeansthattheinputcanchangebeforetheclock edgeandneverthelesstheoldlevelwillbecorrectlyrecognized.Thiscanbeproducedby internaldelayofthedatainput.Forexample,ifaDflipflophasaholdtimeof1ns,the levelpresentattheDinputupto1nsbeforetheclockedgeisthelevelcaptured, provideditwasstableuptothatmoment. Thisconditionisillustratedinthefigurebelow.Thefirsttwowaveformsaretheclock anddatarespectivelyatthechiptoporatthepreviousflop.Thethirdandfourth waveformsshowtheclockanddataattheflopwithnegativeholdtime.Thelast waveformshowstheoutputoftheflopunderconsideration.

    Setuptimeistheminimumtimethataninputmuststabilizetoitslogicallevelbeforethe activeedgeoftheclockinordertoassurethatthatinputiscorrectlyrecognized. Ifacircuithasanegativesetuptime,thismeansthattheinputcanchangeaftertheclock edgeandneverthelessthenewlevelwillbecorrectlyrecognized.Thiscanbeproduced byinternaldelayoftheclocksignal.Forexample,ifaDflipflophasasetuptimeof1 ns,thelevelpresentattheDinputfrom1nsaftertheclockedgeisthelevelcaptured, provideditremainsstablefromthatmoment. Thisconditionisillustratedinthefigurebelow.Thefirsttwowaveformsaretheclock anddatarespectivelyatthechiptoporatthepreviousflop.Thethirdandfourth waveformsshowtheclockanddataattheflopwithnegativesetuptime.Thelast waveformshowstheoutputoftheflopunderconsideration.

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