What are the different types of delays in ASIC or VLSI design?

1. Different Types of Delays in ASIC or VLSI design

2. Source Delay/Latency
3. Network Delay/Latency
4. Insertion Delay
5. Transition Delay/Slew: Rise time, fall time
6. Path Delay
7. Net delay, wire delay, interconnect delay
8. Propagation Delay
9. Phase Delay
10. Cell Delay
11. Intrinsic Delay
12. Extrinsic Delay
13. Input Delay
14. Output Delay
15. Exit Delay
16. Latency (Pre/post CTS)
17. Uncertainty (Pre/Post CTS)
18. Unateness: Positive unateness, negative unateness
19. Jitter: PLL jitter, clock jitter

Gate delay

 Transistors within a gate take a finite time to switch. This means that a change on the
input of a gate takes a finite time to cause a change on the output.[Magma]
 Gate delay =function of(i/p transition time, Cnet+Cpin).
 Cell delay is also same as Gate delay.

Clock latency
 Latency is the delay of the clock source and clock network delay.
 Clock source delay is the time taken to propagate from ideal waveform origin point to
clock definition point. Clock network latency is the delay from clock definition point to
register clock pin.
 Pre CTS Latency and Post CTS Latency
 Latency is the summation of the Source latency and the Network latency. Pre CTS
estimated latency will be considered during the synthesis and after CTS propagated
latency is considered

Source Delay (or Source Latency)

 It is known as source latency also. It is defined as "the delay from the clock origin point
to the clock definition point in the design".
 Delay from clock source to beginning of clock tree (i.e. clock definition point).
  The time a clock signal takes to propagate from its ideal waveform origin point to the
clock definition point in the design.

Network Delay(latency)

 It is also known as Insertion delay or Network latency. It is defined as "the delay from the
clock definition point to the clock pin of the register".

The time clock signal (rise or fall) takes to propagate from the clock definition point to a
register clock pin

 register clock pin.

Figure below shows example of latency for a design without PLL

The latency definitions for designs with PLL are slightly different.

Figure below shows latency specifications of such kind of designs.

Latency from the PLL output to the clock input of generated clock circuitry becomes source
latency. From this point onwards till generated clock divides to flops is now known as network
latency. Here we can observe that part of the network latency is clock to q delay of the flip flop
(of divide by 2 circuit in the given example) is known value.
 latency for a design with PLL

Insertion delay

 The delay from the clock definition point to the clock pin of the register.

Transition delay

1. It is also known as "Slew". It is defined as the time taken to change the state of the
signal. Time taken for the transition from logic 0 to logic 1 and vice versa . or Time
taken by the input signal to rise from 10%(20%) to the 90%(80%) and vice versa.
2. Transition is the time it takes for the pin to change state.

Slew

1. Rate of change of logic.See Transition delay.

2. Slew rate is the speed of transition measured in volt / ns.

1.
Rise Time

2. Rise time is the difference between the time when the signal crosses a low threshold to
the time when the signal crosses the high threshold. It can be absolute or percent.
3. Low and high thresholds are fixed voltage levels around the mid voltage level or it can be
either 10% and 90% respectively or 20% and 80% respectively. The percent levels are
converted to absolute voltage levels at the time of measurement by calculating
 percentages from the difference between the starting voltage level and the final settled
voltage level.

Fall Time

1. Fall time is the difference between the time when the signal crosses a high threshold
to the time when the signal crosses the low threshold.
2. The low and high thresholds are fixed voltage levels around the mid voltage level or
it can be either 10% and 90% respectively or 20% and 80% respectively. The percent
levels are converted to absolute voltage levels at the time of measurement by
calculating percentages from the difference between the starting voltage level and the
final settled voltage level.
3. For an ideal square wave with 50% duty cycle, the rise time will be 0.For a symmetric
triangular wave, this is reduced to just 50%.

 The rise/fall definition is set on the meter to 10% and 90% based on the linear power in
Watts. These points translate into the -10 dB and -0.5 dB points in log mode (10 log 0.1)
and (10 log 0.9). The rise/fall time values of 10% and 90% are calculated based on an
algorithm, which looks at the mean power above and below the 50% points of the rise/fall
times. Click here to see more.

Path delay

 Path delay is also known as pin to pin delay. It is the delay from the input pin of the cell
to the output pin of the cell.
 Net Delay (or wire delay):The difference between the time a signal is first applied to the
net and the time it reaches other devices connected to that net.

1. It is due to the finite resistance and capacitance of the net.It is also known as wire delay.
2. Wire delay =fn(Rnet , Cnet+Cpin)

1. Propagation delay
2. For any gate it is measured between 50% of input transition to the corresponding 50% of
output transition.
3. This is the time required for a signal to propagate through a gate or net. For gates it is the
time it takes for a event at the gate input to affect the gate output.
4. For net it is the delay between the time a signal is first applied to the net and the time it
reaches other devices connected to that net.It is taken as the average of rise time and fall
time i.e. Tpd= (Tphl+Tplh)/2.

Phase delay

 Same as insertion delay

Cell delay

 For any gate it is measured between 50% of input transition to the corresponding 50% of
output transition.

Intrinsic delay

1. Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of
the cell.
2. It is defined as the delay between an input and output pair of a cell, when a near zero
slew is applied to the input pin and the output does not see any load condition.It is
predominantly caused by the internal capacitance associated with its transistor.
3. This delay is largely independent of the size of the transistors forming the gate
because increasing size of transistors increase internal capacitors.

Extrinsic delay

1. Same as wire delay, net delay, interconnect delay, flight time.

2. Extrinsic delay is the delay effect that associated to with interconnect. output pin of
the cell to the input pin of the next cell.

Input delay

1. Input delay is the time at which the data arrives at the input pin of the block from external
circuit with respect to reference clock.

Output delay

 Output delay is time required by the external circuit before which the data has to arrive at
the output pin of the block with respect to reference clock.

Exit delay

 It is defined as the delay in the longest path (critical path) between clock pad input and an
output. It determines the maximum operating frequency of the design.

Unateness

1. A function is said to be unate if the rise transition on the positive unate input variable
causes the ouput to rise or no change and vice versa.
2. Negative unateness means cell output logic is inverted version of input logic. eg. In
inverter having input A and output Y, Y is -ve unate w.r.to A. Positive unate means cell
output logic is same as that of input.
3. These +ve ad -ve unateness are constraints defined in library file and are defined for
output pin w.r.to some input pin.
 4. A clock signal is positive unate if a rising edge at the clock source can only cause a rising
edge at the register clock pin, and a falling edge at the clock source can only cause a
falling edge at the register clock pin.
5. A clock signal is negative unate if a rising edge at the clock source can only cause a
falling edge at the register clock pin, and a falling edge at the clock source can only cause
a rising edge at the register clock pin. In other words, the clock signal is inverted.

A clock signal is not unate if the clock sense is ambiguous as a result of non-unate timing arcs in
the clock path. For example, a clock that passes through an XOR gate is not unate because there
are nonunate arcs in the gate. The clock sense could be either positive or negative, depending on
the state of the other input to the XOR gate.

Jitter
1. The short-term variations of a signal with respect to its ideal position in time.
2. Jitter is the variation of the clock period from edge to edge. It can varry +/- jitter
value.From cycle to cycle the period and duty cycle can change slightly due to the
clock generation circuitry. This can be modeled by adding uncertainty regions around
the rising and falling edges of the clock waveform.

Jitter in technical terms is the deviation in or displacement of some aspect of the pulses in a
high-frequency digital signal. As the name suggests, jitter can be thought of as shaky pulses. The
deviation can be in terms of amplitude, phase timing, or the width of the signal pulse. Another
definition is that it is "the period frequency displacement of the signal from its ideal
location."[citation needed] Among the causes of jitter are electromagnetic interference (EMI) and
crosstalk with other signals. Jitter can cause a display monitor to flicker; affect the ability of the
processor in a personal computer to perform as intended; introduce clicks or other undesired
effects in audio signals, and loss of transmitted data between network devices. The amount of
allowable jitter depends greatly on the application.

Jitter is the time variation of a periodic signal in electronics and telecommunications, often in
relation to a reference clock source. Jitter may be observed in characteristics such as the
frequency of successive pulses, the signal amplitude, or phase of periodic signals. Jitter is a
significant, and usually undesired, factor in the design of almost all communications links (e.g.,
USB, PCI-e, SATA, OC-48). In clock recovery applications it is called timing jitter.[1]

Jitter can be quantified in the same terms as all time-varying signals, e.g., RMS, or peak-to-peak
displacement. Also like other time-varying signals, jitter can be expressed in terms of spectral
density (frequency content).

Jitter period is the interval between two times of maximum effect (or minimum effect) of a
signal characteristic that varies regularly with time. Jitter frequency, the more commonly quoted
figure, is its inverse. Generally, very low jitter frequency is not of interest in designing systems,
and the low-frequency cutoff for jitter is typically specified at 1 Hz.[citation needed]
Jitter on PLL Clocks
Home > Support > Devices > Jitter Information

What is jitter? Jitter is, as shown in Figure 1, is “the short-term variations of a signal with respect
to its ideal position in time.”

Figure 1. Jitter in Clock Signals

This deviation in a clock’s output transition from its ideal position can negatively impact data
transmission quality. In many cases, other signal deviations, like signal skew and coupled noise
are combined and labeled as jitter.Deviation (expressed in ±ps) can occur on either the leading
edge or the trailing edge of a signal. Jitter may be induced and coupled onto a clock signal from
several different sources and is not uniform over all frequencies.Excessive jitter can increase the
bit error rate (BER) of a communications signal by incorrectly transmitting a data bit stream. In
digital systems, jitter can lead to a violation of timing margins, causing circuits to behave
improperly. Accurate measurement of jitter is necessary for ensuring the reliability of a system.

Sources of Jitter

1. Common sources of jitter include:

2. Internal circuitry of the phase-locked loop (PLL)
3. Random thermal noise from a crystal
4. Other resonating devices
5. Random mechanical noise from crystal vibration
6. Signal transmitters
7. Traces and cables
8. Connectors
9. Receivers

Beyond these sources, termination dependency, cross talk, reflection, proximity effects, VCC
sag, ground bounce, and electromagnetic interference (EMI) from nearby devices and equipment
can also increase the amount of jitter in a device.
Reflection and cross-talk frequency-dependent effects may be amplified if an adjacent signal is
synchronous and in phase. Aside from noise caused by power supplies and ground, changes in
circuit impedance are responsible for most of the jitter in data transmission circuits.

Jitter Components

The two major components of jitter are random jitter, and deterministic jitter.

Random Jitter:The random component in jitter is due to the noise inherent in electrical circuits
and typically exhibits a Gaussian distribution. Random jitter (RJ) is due to stochastic sources,
such as substrate and power supply. Electrical noise interacts with the slew rate of signals to
produce timing errors at the switching points.

RJ is additive as the sum of squares, and follows a bell curve. Since random jitter is not bounded,
it is characterized by its standard deviation (rms) value.

Deterministic Jitter:Deterministic jitter (DJ) is data pattern dependant jitter, attributed to a

unique source. Sources are generally related to imperfections in the behavior of a device or
transmission media but may also be due to power supply noise, cross-talk, or signal
modulation.

DJ is linearly additive and always has a specific source. This jitter component has a non-
Gaussian probability density function and is always bounded in amplitude. DJ is characterized by
its bounded, peak-to-peak, value.

Types of Jitter

There are many different types of jitter. Period jitter, cycle-to-cycle jitter and half-period jitter
are described below.

Period Jitter

Period jitter is the change in a clock’s output transition (typically the rising edge) from its ideal
position over consecutive clock edges. Period jitter is measured and expressed in time or
frequency. Period jitter measurements are used to calculate timing margins in systems, such as
tSU and tCO.

Cycle-to-Cycle Jitter

Cycle-to-cycle jitter is the difference in a clock’s period from one cycle to the next. Cycle-to-
cycle jitter is the most difficult to measure usually requiring a timing interval analyzer.

As shown in Figure 2, J1 and J2 are the measured jitter values. The maximum value measured
over multiple cycles is the maximum cycle-to-cycle jitter.
Figure 2. Cycle-to-Cycle Jitter

Half-Period Jitter

Half-period jitter is the measure of maximum change in a clock’s output transition from its ideal
position during one-half period. Figure 3 illustrates half-period jitter.

Half-period jitter impacts DDR transfer applications by reducing capture margins.

Figure 3. Half-Period Jitter

Jitter Specifications

The performance of the PLL is measured using several parameters. Three of the common
specifications used to characterize the PLL are jitter generation, tolerance, and transfer.

Jitter Generation

Jitter generation is the measure of the intrinsic jitter produced by the PLL and is measured at its
output. Jitter generation is measured by applying a reference signal with no jitter to the input of
the PLL, and measuring its output jitter. Jitter generation is usually specified as a peak-to-peak
period jitter value.
Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock in the
presence of jitter of various magnitudes at different frequencies) when jitter is applied to its
reference. Jitter tolerance is usually specified using an input jitter mask.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a
given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and
frequencies, and output jitter is measured with various bandwidth settings. Since intrinsic jitter is
always present, jitter attenuation will appear to be lower for low frequency input jitter signals
than for high frequency ones. Jitter transfer is typically specified using a bandwidth plot.

Clock Definitions :

Types of clocks:

Multiple Clocks

If more than one clock is used in a design, then they can be defined to have different waveforms
and frequencies. These clocks are known as multiple clocks. The logics triggered by each
individual clock are then known as “clock domain”. If clocks have different frequencies there
must be a base period over which all waveforms repeat.Base period is the least common multiple
(LCM) of all clock periods

Asynchronous Clocks:In multiple clock domains, if these clocks do not have a common base
period then they are called as asynchronous clocks. Clocks generated from two different crystals,
PLLs are asynchronous clocks. Different clocks having different frequencies generated from
single crystal or PLL are not asynchronous clocks but they are synchronous clocks.

Gated clocks:Clock signals that are passed through some gate other than buffer and inverters are
called gated clocks. These clock signals will be under the control of gated logic. Clock gating is
used to turn off clock to some sections of design to save power. Click here to read more about
clock gating.

Generated clocksGenerated clocks are the clocks that are generated from other clocks by a
circuit within the design such as divider/multiplier circuit.

Static timing analysis tools such as PrimeTime will automatically calculate the latency (delay)
from the source clock to the generated clock if the source clock is propagated and you have not
set source latency on the generated clock.
 generated clock

‘Clock’ is the master clock and new clock is generated from F1/Q output. Master clock is
defined with the constraint ‘create_clok’. Unless and until new generated clock is defined as
‘generated clock’ timing analysis tools won’t consider it as generated clock. Hence to
accomplish this requirement use “create_generated_clock” command. ‘CLK’ pin of F1 is now
treated as clock definition point for the new generated clock. Hence clock path delay till F1/CLK
contributes source latency whereas delay from F1/CLK contributes network latency.

Virtual Clocks:Virtual clock is the clock which is logically not connected to any port of the
design and physically doesn’t exist. A virtual clock is used when a block does not contain a port
for the clock that an I/O signal is coming from or going to. Virtual clocks are used during
optimization; they do not really exist in the circuit.Virtual clocks are clocks that exist in memory
but are not part of a design. Virtual clocks are used as a reference for specifying input and output
delays relative to a clock. This means there is no actual clock source in the design. Assume the
block to be synthesized is “Block_A”. The clock signal, “VCLK”, would be a virtual clock. The
input delay and output delay would be specified relative to the virtual clock.

Rising and falling edge of the clock

For a +ve edge triggered design +ve (or rising) edge is called ‘leading edge’ whereas –ve (or
falling) edge is called ‘trailing edge’.

For a -ve edge triggered design –ve (or falling) edge is called ‘leading edge’ whereas +ve (or
rising) edge is called ‘trailing edge’.

basic clock
Minimum pulse width of the clock can be checked in PrimeTime by using commands given
below:

set_min_pulse_width -high 2.5 [all_clocks]

set_min_pulse_width -low 2.0 [all_clocks]

These checks are generally carried out for post layout timing analysis. Once these commands are
set, PrimeTime checks for high and low pulse widths and reports any violations.

Capture Clock Edge:The edge of the clock for which data is detected is known as capture edge.

Launch Clock Edge:This is the edge of the clock wherein data is launched in previous flip flop
and will be captured at this flip flop.

launch clock and capture clock

Skew :Skew is the difference in arrival of clock at two consecutive pins of a sequential element
is called skew. Clock skew is the variation at arrival time of clock at destination points in the
clock network. The difference in the arrival of clock signal at the clock pin of different flops.

Two types of skews are defined: Local skew and Global skew.

Local skew Local skew is the difference in the arrival of clock signal at the clock pin of related
flops.

Global skew Global skew is the difference in the arrival of clock signal at the clock pin of non
related flops. This also defined as the difference between shortest clock path delay and longest
clock path delay reaching two sequential elements.

Skew can be positive or negative. When data and clock are routed in same direction then it is
Positive skew. When data and clock are routed in opposite direction then it is negative skew.
 local and global skew

Positive Skew:If capture clock comes late than launch clock then it is called +ve skew.

Clock and data both travel in same direction.

When data and clock are routed in same direction then it is Positive skew.

+ve skew can lead to hold violation.

+ve skew improves setup time.

 positive skew negative skew

Negative Skew:If capture clock comes early than launch clock it is called –ve skew. Clock and
data travel in opposite direction. When data and clock are routed in opposite then it is negative
skew. -ve skew can lead to setup violation. -ve skew improves hold time. (Effects of skew on
setup and hold will be discussed in detail in forthcoming articles)

Uncertainty (pre/post cts)

 Uncertainty is the amount of skew and the variation in the arrival clock edge. Pre CTS
uncertainty is clock skew and clock Jitter. After CTS we can have some margin of skew
+ Jitter.
 Clock uncertainty is the time difference between the arrivals of clock signals at registers
in one clock domain or between domains.
 Pre-layout and Post-layout Uncertainty
 Pre CTS uncertainty is clock skew, clock Jitter and margin. After CTS skew is calculated
from the actual propagated value of the clock. We can have some margin of skew + Jitter.

timing diagram depicting skew, latency, jitter

Clock Gating :Clock tree consume more than 50 % of dynamic power. The components of this
power are:

1) Power consumed by combinatorial logic whose values are changing on each clock edge
2) Power consumed by flip-flops and
3) The power consumed by the clock buffer tree in the design. It is good design idea to turn off
the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They
identify the circuits where clock gating can be inserted.

RTL clock gating works by identifying groups of flip-flops which share a common enable
control signal. Traditional methodologies use this enable term to control the select on a
multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-
flop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock
gating circuit which is connected to the clock ports of all of the flip-flops with the common
enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL
clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable
signal is false.

There are two types of clock gating styles available. They are:

1) Latch-based clock gating

2) Latch-free clock gating.

Latch free clock gating

The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on
which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or
if it multiple times then gated clock output either can terminate prematurely or generate multiple
clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-
clock flip-flop based design.
 Latch free clock gating

Latch based clock gating

The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable
signal from the active edge of the clock until the inactive edge of the clock. Since the latch
captures the state of the enable signal and holds it until the complete clock pulse has been
generated, the enable signal need only be stable around the rising edge of the clock, just as in the
traditional ungated design style.

Latch based clock gating

Specific clock gating cells are required in library to be utilized by the synthesis tools.
Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler
method of low power technique. Advantage of this method is that clock gating does not require
modifications to RTL description.

Delays in ASIC Design :We encounter several types of delays in ASIC design. They are as
follows:
  Gate delay or Intrinsic delay
 Net delay or Interconnect delay or Wire delay or Extrinsic delay or Flight time
 Transition or Slew
 Propagation delay
 Contamination delay

Wire delays or extrinsic delays are calculated using output drive strength, input capacitance and
wire load models. Other delays are intrinsic properties of each and every gate.

Delays are interdependent on different electrical properties. [Nekoogar]:

 Input capacitance of the logic gate is a function of output state, output loads and input
slew rate.

1. Internal timing arcs and output slew rate is a function of switching input(s).
2. Capacitance of the wire is dependent on frequency.
a. Internal timing arcs are a function of input slew rates.
3. Output slew rate is a function of input slew rate on each input.
4. Wires exhibit RLC characteristics instead of lumped RC.

Gate DelayTransistors within a gate take a finite time to switch. This means that a change on
the input of a gate takes a finite time to cause a change on the output. [Magma]

Gate delay =function of (input transition (slew) time, Cnet+Cpin).

or

Gate delay =function of (input transition (slew) time, Cload).

where Cload=Cnet+Cpin

Cnet-->Net capacitance

Cpin-->pin capacitance of the driven cell

Cell delay is also same as Gate delay.

How gate delay is calculated?Cell or gate delay is calculated using Non-Linear Delay
Models (NLDM). NLDM is highly accurate as it is derived from SPICE characterizations. The
delay is a function of the input transition time (i.e. slew) of the cell, the wire capacitance
and the pin capacitance of the driven cells. A slow input transition time will slow the rate at
which the cell’s transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), as well as a
large output load Cload (Cnet + Cpin), thereby increasing the delay of the logic gate.There is
another NLDM table in the library to calculate output transition. Output transition of a cell
becomes the input transition of the next cell down the chain.

Table models are usually two-dimensional to allow lookups based on the input slew and the
output load (Cload). A sample table is given below.

timing() {

related_pin : "CKN";

timing_type : falling_edge;

timing_sense : non_unate;

cell_rise(delay_template_7x7) {

index_1 ("0.012, 0.032, 0.074, 0.154, 0.318, 0.644, 1.3");

index_2 ("0.001278, 0.0046008, 0.0112464, 0.0245376, 0.05112, 0.10454, 0.212148");

values ( \

"0.225894, 0.249015, 0.285537, 0.352680, 0.484244, 0.748180, 1.279570", \

"0.231295, 0.254415, 0.290938, 0.358081, 0.489646, 0.753585, 1.284980", \

"0.243754, 0.266878, 0.303398, 0.370542, 0.502105, 0.766044, 1.297440", \

"0.267240, 0.290389, 0.326908, 0.394052, 0.525615, 0.789561, 1.320950", \

"0.307080, 0.330200, 0.366721, 0.433861, 0.565425, 0.829373, 1.360760", \

"0.380552, 0.403875, 0.440426, 0.507569, 0.639136, 0.903084, 1.434500", \

"0.497588, 0.521769, 0.558548, 0.625744, 0.757301, 1.021260, 1.552680");

rise_transition(delay_template_7x7) {

index_1 ("0.012, 0.032, 0.074, 0.154, 0.318, 0.644, 1.3");

index_2 ("0.001278, 0.0046008, 0.0112464, 0.0245376, 0.05112, 0.10454, 0.212148");

values ( \

"0.040574, 0.068619, 0.125391, 0.246672, 0.497688, 1.005982, 2.030120", \

"0.040570, 0.068618, 0.125390, 0.246672, 0.497688, 1.005940, 2.030240", \

"0.040565, 0.068616, 0.125389, 0.246650, 0.497770, 1.006180, 2.030120", \

"0.040532, 0.068612, 0.125387, 0.246670, 0.497710, 1.006164, 2.030100", \

"0.040578, 0.068621, 0.125392, 0.246636, 0.497688, 1.006182, 2.030040", \

"0.041763, 0.069211, 0.125662, 0.246758, 0.497726, 1.005930, 2.030000", \

"0.045813, 0.071321, 0.126671, 0.247154, 0.497846, 1.005962, 2.030180");

index_1 --> input transition values

index_2--> output load capacitance values

values--> delay values

Situation 1: Input transition and output load values match with table index values
:If both input transition and output load values match with table index values then corresponding
delay value is directly picked up from the delay “values” table as highlighted by yellow shaded
data.

Situation 2: Output load values doesn't match with table index values :When the actual
load capacitance values does not fall directly on or at one of the load-axis index points, the delay
is determined by interpolation from the closest points. Note that to carry out interpolation input
transition point should match with the any one of the table index values.
  Determine the equation for the line segment connecting the two nearest points in the
table.
 To do this first we need to find the slope value.

Slope m = (y2-y1)/(x2-x1) where (y2-y1) is delay segment (generally in ns) on y axis and (x2-
x1) is load segment (generally in pf) on x-axis.

 Solve for the delay at the load point of interest.

The linear equation is:

y = mx+c

where y-->delay (ns),m-->slope,x-->load capacitance (pf)

i.e. delay=slope*load point of interest (constant value is zero)

Load point of interest means load capacitance value for which delay has to be calculated.

Situation 3:
Both input transition and output load values doesn't match with table index values

If both input transition and load capacitance values do not match exactly with the look up table
index values then bilinear interpolation is used.Multiple linear interpolations (~3) are performed
on multiple closest table data points (~4) as shown in highlighted violet color in the look up
table.

Situation 4: Output load values doesn't match with table index values and is outside
the table boundary:When the load point is outside of the boundary of the index, the delay is
extrapolated to the closest known points.Lookup value too far out of range of the given table
value could lead to inaccuracy. [Cadence]

Intrinsic delayIntrinsic delay is the delay internal to the gate. This is from input pin of the
cell to output pin of the cell.

1. It is defined as the delay between an input and output pair of a cell, when a near zero
slew is applied to the input pin and the output does not see any load condition. It is
caused by the internal capacitance associated with its transistor.
2. This delay is largely dependent on the size of the transistors forming the gate because
increasing size of transistors increase internal capacitors.

Net Delay or Interconnect Delay or Wire Delay or Extrinsic Delay or Flight Time
Net delay is the difference between the time a signal is first applied to the net and the time it
reaches other devices connected to that net. It is due to the finite resistance and capacitance of
the net. It is also known as wire delay.

Wire load models for synthesis

Wire load modeling allows us to estimate the effect of wire length and fanout on the resistance,
capacitance, and area of nets. Synthesizer uses these physical values to calculate wire delays and
circuit speeds. Semiconductor vendors develop wire load models, based on statistical
information specific to the vendors’ process. The models include coefficients for area,
capacitance, and resistance per unit length, and a fanout-to-length table for estimating net lengths
(the number of fanouts determines a nominal length).

1. Selection of wire load models in the initial stage (before physical design) depends on the
fallowing factors:
1. User specification
2. Automatic selection based on design area
3. Default specification in the technology library

Once the final routing step is over in the physical design stage, wire load models are generated
based on the actual routing in the design and synthesis is redone using those wire load models.

In hierarchical designs, we have to determine which wire load model to use for nets that cross
hierarchical boundaries. There are three modes for determining which wire load model to use for
nets that cross hierarchical boundaries:

Top:

Applying same wire load models to all nets as if the design has no hierarchy and uses the wire
load model specified for the top level of the design hierarchy for all nets in a design and its sub
designs.

The wire load model of the smallest design that fully encloses the net is applied. If the design
enclosing the net has no wire load model, then traverses the design hierarchy upward until we
finds a wire load model. Enclosed mode is more accurate than top mode when cells in the same
design are placed in a contiguous region during layout.

Use enclosed mode if the design has similar logical and physical hierarchies.

Segmented:

Wire load model for each segment of a net is determined by the design encompassing the
segment. Nets crossing hierarchical boundaries are divided into segments. For each net segment,
the wire load model of the design containing the segment is used. If the design contains a
segment that has no wire load model, then traverse the design hierarchy upward until it finds a
wire load model.
Interconnect Delay vs. Deep Sub Micron Issues
Performances of deep sub micron ICs are limited by increasing interconnect loading affect. Long
global clock networks account for the larger part of the power consumption in chips. Traditional
CAD design methodologies are largely affected by the interconnect scaling. Capacitance and
resistance of interconnects have increased due to the smaller wire cross sections, smaller wire
pitch and longer length. This has resulted in increased RC delay. As technology is advancing
scaling of interconnect is also increasing. In such scenario increased RC delay is becoming major
bottleneck in improving performance of advanced ICs.

Here the gate delay and the interconnect delay are shown as functions of various technology
nodes ranging from 180nm to 60nm. The interconnect delays shown assumes a line where
repeaters are connected optimally and includes the delay due to the repeaters. From the graph it
can be observed that with the shrinking of technology gate delay reduces but interconnect delay
increases.

Transition Delay and Propagation Delay

Transition Delay
Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90
%( 80%) of its maximum value. This is known as “rise time”.

Similarly “fall time” can be defined as the time taken by a signal to fall from 90 %( 80%) to the
10 %( 20%) of its maximum value.
Transition is the time it takes for the pin to change state.

Propagation DelayPropagation delay is the time required for a signal to propagate through a
gate or net. Hence if it is cell, you can call it as “Gate or Cell Delay” or if it is net you can call it
as “Net Delay”

Propagation delay of a gate or cell is the time it takes for a signal at the input pin to affect the
output signal at output pin.

For any gate, propagation delay is measured between 50% of input transition to the
corresponding 50% of output transition.

There are 4 possibilities:

1. Propagation delay between 50 % of Input rising to 50 % of output rising.

2. Propagation delay between 50 % of Input rising to 50 % of output falling.
3. Propagation delay between 50 % of Input falling to 50 % of output rising.
4. Propagation delay between 50 % of Input falling to 50 % of output falling.

Each of these delays has different values. Maximum and minimum values of these set are very
important. Maximum and minimum propagation delay values are considered for timing analysis.

For net, propagation delay is the delay between the time a signal is first applied to the net and the
time it reaches other devices connected to that net.

Propagation delay is taken as the average of rise time and fall time i.e. Tpd= (Tphl+Tplh)/2.

Propagation delay depends on the input transition time (slew rate) and the output load. Hence
two dimensional look up tables are used to calculate these delays. How to calculate propagation
delay of net and gate? Please refer below articles to find

Recovery Time

1. Recovery specifies the minimum time that an asynchronous control input pin must be
held stable after being de-asserted and before the next clock (active-edge) transition.
2. Recovery time specifies the time the inactive edge of the asynchronous signal has to
arrive before the closing edge of the clock.
3. Recovery time is the minimum length of time an asynchronous control signal (eg.preset)
must be stable before the next active clock edge. The recovery slack time calculation is
similar to the clock setup slack time calculation, but it applies asynchronous control
signals.

Equation 1:
 1. Recovery Slack Time = Data Required Time – Data Arrival Time
2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +
Tclkq+ Register to Register Delay
3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register
=Tsetup

If the asynchronous control is not registered, equations shown in Equation 2 is used to calculate
the recovery slack time.

Equation 2:

1. Recovery Slack Time = Data Required Time – Data Arrival Time
2. Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay
3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register
Delay+Tsetup

 If the asynchronous reset signal is from a port (device I/O), you must make an Input
Maximum Delay assignment to the asynchronous reset pin to perform recovery analysis
on that path.

What is Static Timing Analysis (STA)?In Static Timing Analysis (STA)

static delays such as gate delay and net delays are considered in each path and these
delays are compared against their required maximum and minimum values. Circuit to be
analyzed is broken into different timing paths constituting of gates, flip flops and their
interconnections. Each timing path has to process the data within a clock period which
is determined by the maximum frequency of operation. Cell delays are available in the
corresponding technology libraries. Cell delay values are tabulated based on input
transition and fanout load which are characterized by SPICE simulation. Net delays are
calculated based on the Wire Load Models(WLM) or extracted resistance R and
capacitance C. Wire Load Models(WLM) are available in the Technology File. These
values are Table Look Up(TLU) values calculated based on the net fanout length.

The static timing analyzer will report the following delays (or it can do following
analysis):

1. Register to Register delays

2. Setup times of all external synchronous inputs
3. Clock to Output delays
4. Pin to Pin combinational delays
5. Different Analysis Modes-Best, Worst, Typical, On Chip Variation (OCV)
6. Data to Data Checks
7. Case Analysis
8. Multiple Clocks per Register
9. Minimum Pulse Width Checks
10. Derived Clocks
 11. Clock Gating Checks
12. Netlist Editing
13. Report_clock_timing
14. Clock Reconvergence Pessimism

Worst-Arrival Slew Propagation

Path-Based Analysis

Debugging Delay Calculation

The wide spread use of STA can be attributed to several factors [David]:

The basic STA algorithm is linear in runtime with circuit size, allowing analysis of
designs in excess of 10 million instances.

 The basic STA analysis is conservative in the sense that it will over-estimate the
delay of long paths in the circuit and under-estimate the delay of short paths in
the circuit. This makes the analysis ”safe”, guaranteeing that the design will
function at least as fast as predicted and will not suffer from hold-time violations.

 The STA algorithms have become fairly mature, addressing critical timing issues
such as interconnect analysis, accurate delay modeling, false or multi-cycle
paths, etc.

 Delay characterization for cell libraries is clearly defined, forms an effective

interface between the foundry and the design team, and is readily available. In
addition to this, the Static Timing Analysis (STA) does not require input vectors
and has a runtime that is linear with the size of the circuit [Agarwal].

Advantages of STA:All timing paths are considered for the timing analysis. This
is not the case in simulation.

 Analysis times are relatively short when compared with event and circuit
simulation.

 Timing can be analyzed for worst case, best case simultaneously. This type of
analysis is not possible in dynamic timing analysis.

 Static Timing Analysis (STA) works with timing models. STA has more
pessimism and thus gives maximum delay of the design. DTA performs full
timing simulation. The problem associated with DTA is the computational
complexity involved in finding the input patterns (vectors) that produce maximum
delay at the output and hence it is slow.
Disadvantages of STA:
 All paths in the design may not run always in worst case delay. Hence the analysis is
pessimistic.

 Clock related all information has to be fed to the design in the form of constraints.

 Inconsistency or incorrectness or under constraining of these constraints may lead to

disastrous timing analysis.

 STA does not check for logical correctness of the design.

 STA is not suitable for asynchronous circuits.

A comprehensive static timing analysis includes analysis of register-to-register, I/O, and

asynchronous reset paths. The TimeQuest timing analyzer uses data required times, data arrival
times, and clock arrival times to verify circuit performance and to detect possible timing
violations. The TimeQuest analyzer determines the timing relationships that must be met for the
design to correctly function, and checks arrival times against required times to verify timing.

 Clock Setup Check

 Clock Hold Check
 Recovery and Removal
 Multicycle Paths

Clock Setup Check

To perform a clock setup check, the TimeQuest analyzer determines a setup relationship by
analyzing each launch and latch edge for each register-to-register path. For each latch edge at the
destination register, the TimeQuest analyzer uses the closest previous clock edge at the source
register as the launch edge.

In Figure 1, two setup relationships are defined and labeled Setup A and Setup B. For the latch
edge at 10 ns, the closest clock that acts as a launch edge is at 3 ns and is labeled Setup A. For
the latch edge at 20 ns, the closest clock that acts as a launch edge is at 19 ns and is labeled Setup
B.

Figure 1. Setup Check

The TimeQuest analyzer reports the result of clock setup checks as slack values. Slack is the
margin by which a timing requirement is met or not met. Positive slack indicates the margin by
which a requirement is met, and negative slack indicates the margin by which a requirement is
not met. The TimeQuest analyzer determines clock setup slack as shown in Equation 1 for
internal register-to-register paths.

Equation 1

1. Clock Setup Slack = Data Required Time – Data Arrival Time

2. Data Required = Clock Arrival Time – μtSU – Setup Uncertainty

3. Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register

4. Data Arrival Time = Launch Edge + Clock Network Delay Source Register + μtCO +
Register-to-Register Delay

If the data path is from an input port to a internal register, the TimeQuest analyzer uses the
equations shown in Equation 2 to calculate the setup slack time.

Equation 2

1. Clock Setup Slack Time = Data Required Time – Data Arrival Time

2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Input
Maximum Delay of Pin + Pin to Register Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register – μtSU

4. If the data path is an internal register to an output port, the TimeQuest analyzer uses the
equations shown in Equation 3 to calculate the setup slack time.

Equation 3

1. Clock Setup Slack Time = Data Required Time – Data Arrival Time
 2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCO +
Register to Pin Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register –
Output Maximum Delay of Pin

Clock Hold Check

To perform a clock hold check, the TimeQuest analyzer determines a hold relationship for each
possible setup relationship that exists for all source and destination register pairs. The TimeQuest
analyzer checks all adjacent clock edges from all setup relationships to determine the hold
relationships. The TimeQuest analyzer performs two hold checks for each setup relationship. The
first hold check determines that the data launched by the current launch edge is not captured by
the previous latch edge. The second hold check determines that the data launched by the next
launch edge is not captured by the current latch edge.

Figure 2 shows two setup relationships labeled Setup A and Setup B. The first hold check is
labeled Hold Check A1 and Hold Check B1 for Setup A and Setup B, respectively. The second
hold check is labeled Hold Check A2 and Hold Check B2 for Setup A and Setup B, respectively.

Figure 2. Hold Check

From the possible hold relationships, the TimeQuest analyzer selects the hold relationship that is
the most restrictive. The hold relationship with the largest difference between the latch and
launch edges (that is, latch– launch and not the absolute value of latch – launch) is selected
because this determines the minimum allowable delay for the register-toregister path. For Figure
2, the hold relationship selected is Hold Check A2. The TimeQuest analyzer determines clock
hold slack as shown in Equation 4.

Equation 4

1. Clock Hold Slack = Data Arrival Time – Data Required Time

2. Data Required Time = Clock Arrival Time +μtH + Hold Uncertainty

 3. Clock Arrival Time = Latch Edge + Clock Network Delay to Destination Register

4. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +μtCO+
Register to Register Delay

If the data path is from an input port to an internal register, the TimeQuest analyzer uses the
equations shown in Equation 5 to calculate the hold slack time.

Equation 5

1. Clock Setup Slack Time = Data Arrival Time – Data Required Time

2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Input
Minimum Delay of Pin + Pin to Register Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register + μtH

If the data path is an internal register to an output port, the TimeQuest analyzer uses the
equations shown in Equation 6 to calculate the hold slack time.

Equation 6

1. Clock Setup Slack Time = Data Arrival Time – Data Required Time

2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCO +
Register to Pin Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register –
Output Minimum Delay of Pin

Recovery and Removal

Recovery time is the minimum length of time an asynchronous control signal, for example, and
preset, must be stable before the next active clock edge. The recovery slack time calculation is
similar to the clock setup slack time calculation, but it applies asynchronous control signals. If
the asynchronous control is registered, the TimeQuest analyzer uses Equation 7 to calculate the
recovery slack time.

Removal Time

 Removal specifies the minimum time that an asynchronous control input pin must be held
stable before being de-asserted and after the previous clock (active-edge) transition.

 Removal time specifies the length of time the active phase of the asynchronous signal has
to be held after the closing edge of clock.
  Removal time is the minimum length of time an asynchronous control signal must be
stable after the active clock edge. Calculation is similar to the clock hold slack
calculation, but it applies asynchronous control signals. If the asynchronous control is
registered, equations shown in Equation 3 is used to calculate the removal slack time.

If the recovery or removal minimum time requirement is violated, the output of the sequential
cell becomes uncertain. The uncertainty can be caused by the value set by the resetbar signal or
the value clocked into the sequential cell from the data input.

Equation 3

1. Removal Slack Time = Data Arrival Time – Data Required Time
2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register +
Tclkq of Source Register + Register to Register Delay
3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register +
Thold
4. If the asynchronous control is not registered, equations shown in Equation 4 is used to
calculate the removal slack time.

Equation 4

1. Removal Slack Time = Data Arrival Time – Data Required Time
2. Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to
Register Delay
3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register
+Thold

 If the asynchronous reset signal is from a device pin, you must specify the Input
Minimum Delay constraint to the asynchronous reset pin to perform a removal analysis
on this path.

Equation 7

1. Recovery Slack Time = Data Required Time – Data Arrival Time

2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCO+
Register to Register Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register – μtSU

If the asynchronous control is not registered, the TimeQuest analyzer uses the equations shown
in Equation 8 to calculate the recovery slack time.

Equation 8
 1. Recovery Slack Time = Data Required Time – Data Arrival Time

2. Data Arrival Time = Launch Edge + Maximum Input Delay + Port to Register Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register Delay
– μtSU

Note: If the asynchronous reset signal is from a port (device I/O), you must make an Input
Maximum Delay assignment to the asynchronous reset pin for the TimeQuest Timing Analyzer
to perform recovery analysis on that path.

Removal time is the minimum length of time an asynchronous control signal must be stable after
the active clock edge. The TimeQuest analyzer removal time slack calculation is similar to the
clock hold slack calculation, but it applies asynchronous control signals. If the asynchronous
control is registered, the TimeQuest analyzer uses the equations shown in Equation 9 to calculate
the removal slack time.

Equation 9

1. Removal Slack Time = Data Arrival Time – Data Required Time

2. Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + μtCOof
Source Register + Register to Register Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register + μtH

If the asynchronous control is not registered, the TimeQuest analyzer uses the equations shown
in Equation 10 to calculate the removal slack time.

Equation 10

1. Removal Slack Time = Data Arrival Time – Data Required Time

2. Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to
Register Delay

3. Data Required Time = Latch Edge + Clock Network Delay to Destination Register +μtH

Note: If the asynchronous reset signal is from a device pin, you must specify the Input Minimum
Delay constraint to the asynchronous reset pin for the TimeQuest analyzer to perform a removal
analysis on this path.

Multicycle Paths
Multicycle paths are data paths that require more than one clock cycle to latch data at the
destination register. For example, a register may be required to capture data on every second or
third rising clock edge.

Figure 3 shows an example of a multicycle path between a multiplier’s input registers and output
register where the destination latches data on every other clock edge. Refer to TimeQuest
set_multicycle_path Command for information about the set_multicycle_path command.

Figure 3. Multicycle Path

Many clocks can exist in a design; however, not all clocks interact with one another, and certain
clock interactions are not possible. Asynchronous clocks are unrelated clocks (asynchronous
clocks have different ideal clock sources). Exclusive clocks are not active at the same time (e.g,
multiplexed clocks). The mutual exclusivity must be declared to the TimeQuest analyzer to
prevent it from analyzing these clock interactions.

You can use the set_clock_groups command to specify clocks that are exclusive or
asynchronous.

There are two forms of clock latency: source and network. Source latency is the propagation
delay from the origin of the clock to the clock definition point (for example, a clock port), and
network latency is the propagation delay from a clock definition point to a register’s clock pin.
The total latency (or clock propagation delay) at a register’s clock pin is the sum of the source
and network latencies in the clock path.

You can use the set_clock_latency command to specify input delay constraints to ports in the
design.

The set_clock_uncertainty command specifies clock uncertainty or skew for clocks or clock-to-
clock transfers. You can specify the uncertainty separately for setup and hold, and you can
specify separate rising and falling clock transitions. The TimeQuest analyzer subtracts the setup
uncertainty from the data required time for each applicable path, and adds the hold uncertainty to
the data required time for each applicable path.

You can use the set_clock_uncertainty command to specify any clock uncertainty to the clock
port.

The TimeQuest analyzer considers clock dividers, ripple clocks, or circuits that modify or change the
characteristics of the incoming or master clock as generated clocks. You should define the output of
these circuits as generated clocks. This definition allows the TimeQuest analyzer to analyze these clocks
and account for any network latency associated with them.

Note:

1. The TimeQuest analyzer supports a maximum of three edges in the edge list.

Source latencies are based on clock network delays from the master clock (not necessarily the
master pin). You can use the set_clock_latency -source command to override the source
latency.

Figure 1 shows waveforms for the following SDC commands that create an inverted generated
clock based on a 10 ns clock.

create_clock -period 10 [get_ports clk]

create_generated_clock -divide_by 1 -invert -source [get_registers clk] \
[get_registers gen|clkreg]

Figure 1. Generating an Inverted Clock


 Dynamic vs Static Timing Analysis
 Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be
compromised but not timing! Timing analysis can be static or dynamic. Dynamic timing
analysis verifies functionality of the design by applying input vectors and checking for
correct output vectors whereas Static Timing Analysis checks static delay requirements
of the circuit without any input or output vectors.
 Dynamic timing analysis has to be accomplished and functionality of the design
must be cleared before the design is subjected to Static Timing Analysis (STA).
Dynamic Timing Analysis (DTA) and Static Timing Analysis (STA) are not
alternatives to each other. Quality of the Dynamic Timing Analysis (DTA)
increases with the increase of input test vectors. Increased test vectors increase
 simulation time. Dynamic timing analysis can be used for synchronous as well as
asynchronous designs. Static Timing Analysis (STA) can’t run on asynchronous
deigns and hence Dynamic Timing Analysis (DTA) is the best way to analyze
asynchronous designs. Dynamic Timing Analysis (DTA) is also best suitable for
designs having clocks crossing multiple domains.

 Example of Dynamic Timing Analysis(DTA) tool is Modelsim (from mentor
Graphics), VCS (from Synopsys). DTA is also carried out on post layout netlist to
verify that functionality of the design has not changed. Test vectors remain same
for both.
 Static vs. Dynamic Timing Analysis
Timing analysis can be static or dynamic.

Static Timing Analysis (STA) works with timing models where as the Dynamic Timing
Analysis (DTA) works with spice models. STA has more pessimism and thus gives
maximum delay of the design. DTA overcomes this difficulty because it performs full
timing simulation. The problem associated with DTA is the computational complexity
involved in finding the input pattern(s) that produces maximum delay at the output and
hence it is slow. The static timing analyzer will report the following delays: Register to
Register delays, Setup times of all external synchronous inputs, Clock to Output delays,
Pin to Pin combinational delays. The clock to output delay is usually just reported as
simply another pin-to-pin combinational delay. Timing analysis reports are often
pessimistic since they use worst case conditions.

The wide spread use of STA can be attributed to several factors [2]:

The basic STA algorithm is linear in runtime with circuit size, allowing analysis of
designs in excess of 10 million instances.

The basic STA analysis is conservative in the sense that it will over-estimate the delay of
long paths in the circuit and under-estimate the delay of short paths in the circuit. This
makes the analysis ”safe”, guaranteeing that the design will function at least as fast as
predicted and will not suffer from hold-time violations.

The STA algorithms have become fairly mature, addressing critical timing issues such as
interconnect analysis, accurate delay modeling, false or multi-cycle paths, etc.
Delay characterization for cell libraries is clearly defined, forms an effective interface
between the foundry and the design team, and is readily available. In addition to this, the
Static Timing Analysis (STA) does not require input vectors and has a runtime that is
linear with the size of the circuit [9].


 SPICE Simulation

  Device level timing analysis is carried out using SPICE simulation. SPICE
simulation is very essential for full custom designs to verify the electrical
properties of the designs. These are calculated based on the mathematical
equations that represent electrical properties of devices. Material and some of
the electrical properties of the devices, which are represented by either variables
or constants, are stored in model files. Examples are threshold voltage of
MOSFET, electron density etc. SPICE characterized data is tabulated in
technology libraries which becomes basic delay information for the Static Timing
Analysis. For example let us consider a AND gate. Several electrical properties
such as input and output transition, propagation delay, output capacitance etc
are evaluated by this SPICE simulation. SPICE simulated data gives maximum
accuracy compared to any other form of simulation. SPICE code is manually
written and simulated. Hence for a larger design SPICE simulation is
cumbersome job. There are specific tools available for transistor level Static
Timing Analysis (STA), (Eg. Pathmill from Synopsys) SPICE simulation being the
backbone of all these tools.

Removal Time

 Removal specifies the minimum time that an asynchronous control input pin must be held
stable before being de-asserted and after the previous clock (active-edge) transition.

 Removal time specifies the length of time the active phase of the asynchronous signal has
to be held after the closing edge of clock.

 Removal time is the minimum length of time an asynchronous control signal must be
stable after the active clock edge. Calculation is similar to the clock hold slack
calculation, but it applies asynchronous control signals. If the asynchronous control is
registered, equations shown in Equation 3 is used to calculate the removal slack time.

 If the recovery or removal minimum time requirement is violated, the output of the
sequential cell becomes uncertain. The uncertainty can be caused by the value set by the
resetbar signal or the value clocked into the sequential cell from the data input.

Equation 3

 Removal Slack Time = Data Arrival Time – Data Required Time
  Data Arrival Time = Launch Edge + Clock Network Delay to Source Register + Tclkq of
Source Register + Register to Register Delay

 Data Required Time = Latch Edge + Clock Network Delay to Destination Register +
Thold

 If the asynchronous control is not registered, equations shown in Equation 4 is used to

calculate the removal slack time.

Equation 4

 Removal Slack Time = Data Arrival Time – Data Required Time

 Data Arrival Time = Launch Edge + Input Minimum Delay of Pin + Minimum Pin to
Register Delay

 Data Required Time = Latch Edge + Clock Network Delay to Destination Register
+Thold

 If the asynchronous reset signal is from a device pin, you must specify the Input
Minimum Delay constraint to the asynchronous reset pin to perform a removal analysis
on this path.