VLSI Lab Compendium

VLSI Design EEE 434 Lab Compendium
Student Name: ___________________________ Registration No: ___________________________ Semester: ___________________________ Date: ___________________________
_______________________________________________ Date and signature of student:
_______________________________________________ Date and signature of lab instructor:
Shahzad Asif
February, 2009
Department of Electrical Engineering COMSATS Institute of Information Technology
List of Lab Experiments

DESCRIPTION OF LAB Lab 1 Lab 2 Lab 3 Lab 4 Lab 5 Lab 6 Lab 7 Lab 8 Lab 9 Lab 10 Lab 11 Lab 12 Lab 13 Lab 14 MOSFET Characteristics using DSCH Inverter Characteristics using DSCH Basic Gates Implementation in DSCH and Microwind Combinational Logic (Full Adder) Implementation in DSCH and Microwind CMOS Inverter(Layout Design) Implementation in DSCH and Microwind AND Gate (Layout Design) Implementation in DSCH and Microwind Transistor Sizing for Large Capacitive Loads Implementation in DSCH and Microwind Pass Transistor Logic Implementation in DSCH and Microwind Manchester Carry Chain Adder Implementation in DSCH and Microwind Carry Save Multiplier Implementation in DSCH and Microwind Barrel Shifter Implementation in DSCH and Microwind NAND ROM and NOR ROM Implementation in DSCH and Microwind SRAM Implementation in DSCH and Microwind DRAM Implementation in DSCH and Microwind PAGE NO. 2 8 11 14 16 22 30 32 35 37 39 41 43 45
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Lab # 01: MOSFET Characteristics

1. Objective In this lab, you will study the behaviour of NMOS and PMOS the tools which will be used for the labs are DSCH2 and Microwind. 2. Theory 2.1. MOSFET The metal-oxide-semiconductor field effect transistor is very important part of the digital design. It is mostly used as a switch. MOSFET is a four terminal device. The voltage applied to the gate determines the amount of current flows between source and drain ports. The body of the transistor (BULK) represents the fourth terminal. Note: Mostly the fourth terminal (bulk/body) of a MOS is connected to a DC supply that is identical for all devices of the same type (GND for NMOS, VDD for PMOS), so this terminal is not shown on the schematics. 2.2 NMOS The NMOS transistor consists of n+ drain and n+ source regions which are embedded in a p-type substrate. The current is carried by electrons moving through an ntype channel between source and drain. 2.3 PMOS The PMOS transistor consists of p+ drain and p+ source regions which are embedded in an n-type substrate. The current is carried by electrons moving through an ntype channel between source and drain. 2.4 CMOS The CMOS (Complementary MOS) consists of both p-type and n-type MOS. The advantage of CMOS is its low power design. 3. Design For this lab we have selected a simple NMOS based design for experimentation.
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Figure 1. Test Circuit for NMOS 4. Lab Instructions 4.1. Schematic Design (DSCH) 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Open DSCH. Select the CMOS 025 foundry by selecting File Select Foundry Save the design frequently, during the elapse of the lab session. Drag the required components from the symbol library. The symbol library can be opened from View Symbol Library Connect the components as shown in figure 1. Check if there are any floating lines. Simulated Check Floating Lines. Simulate the design. Simulate Simulation. Carefully observe the results and fill table 1 given below. The timing diagram can be viewed by selecting View Timing Diagrams. To create a Verilog file, select File Make Verilog File. A window will appear as shown below, uncheck all the check boxes and click on OK.
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Figure 2 SR# 1 2 3 4 Input at Gate 0 0 1 1 Input at drain 0 1 0 1 Table 1 Output
4.2. Layout Editor (Microwind) To see the layout of this design follow the following steps. 1. 2. 3. 4. Open Microwind. Select the cmos025 foundry by selecting File Select Foundry. Select Compile Compile Verilog File. Select the file generated by DSCH2. A window will be opened as shown below.
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Figure 3. 5. 6. 7. 8. 9. Click on the Compile button. Click on the Back to Editor button, the layout will be generated. Save your design. To check if there are any errors, select Analysis Design Rule Checker To see the simulation results, select Simulate Run Simulation.
The characteristics of PMOS are similar to the NMOS. Design the test circuits for PMOS and Study its behaviour. 5. Simulation Max Time Delay for NMOS: ________________ Max Time Delay for PMOS: ________________ Dimension of the Layout for NMOS (in Lambda): ________________ Dimension of the Layout for PMOS (in Lambda): ________________ 6. Results Explain the functionality of the designed NMOS ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
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Department of Electrical Engineering COMSATS Institute of Information Technology Explain the functionality of the designed PMOS ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ Draw the circuit designed for PMOS
Find out the maximum drain current when Vd is varied through 0 values of Vg given in the table. Note: Use low-leakage NMOS device to fill the table.
2.5V, for the
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Table 2. What is the affect of W/L on IDs? Explain the affect of Vb to the threshold voltage for NMOS devices. Explain the affect of Vb to the threshold voltage for PMOS devices. Explain the affect of Vb to Ids for NMOS devices. Explain the affect of Vb to Ids for NMOS devices. What is the affect of Vg to Cgs (gate to source capacitance). What is the affect of Vg to Cgd (gate to drain capacitance). What is the affect of temperature on the following? 1. 2. 3. Capacitance Threshold Voltage Drain Current (IDs)
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Lab # 02: Inverter Characteristics

1. Objective
In this lab, students will design a CMOS inverter and study its behavior. The observation includes input to output delay, affect of transistor size on delay, gain, etc. Note: Make sure that you are familiar with DSCH2 and Microwind, and you have no problem in using the options of these tools. Study the lab manual before coming to the lab to have a better understanding of the problem.
2. Design
Figure 1. Test Circuit for Inverter.
3. Lab Instructions 3.1. Schematic Design (DSCH2)

1. 2. 3. 4. 5. 6. 7. Open DSCH2. Select the cmos025 foundry by selecting File Select Foundry. Save the design frequently, during the elapse of the lab session. Draw the circuit shown in Figure 1. Check for floating lines, and if needed remove them. Simulate the design and observe the results. Create a Verilog file of the design.
3.2. Layout Editor (Microwind)

To see the layout of this design follow the following steps. 1. Open Microwind. 2. Select the cmos025 foundry by selecting File Select Foundry.
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Department of Electrical Engineering COMSATS Institute of Information Technology 3. Select Compile Compile Verilog File. 4. Select the file that you have generated by DSCH2 and compile it. 5. Save the Layout.
4. Simulation (Microwind) and Results

1. Select Simulate Run Simulation Static Voltage vs. Voltage. The following window will appear.
2. Check the X(50%) checkbox and click on reset button. Note the value of Vc in the table 1. 3. You can change the simulation parameters by selecting simulate Simulation Parameters. Fill the table 1 for different values of Vdd. Repeat the same experiment with different length of NMOS & PMOS, and fill table 2 for the default simulation parameters. Sr. # Vdd Supply (in Volts) Vc at y = Vdd/2 1 2 3 4 5 Table 1.
Sr. #
Width of NMOS
Width of PMOS
Input to Output Delay
Vc at y = Vdd/2
1 2 Table 2. When we use NMOS and PMOS transistors of same size, the time that it takes to change the output from 0 to 1 is more than the time for 1 to 0. The reason for this is that the mobility of electrons is more than the mobility of holes. To solve this problem we use PMOS with larger width than NMOS. Keeping the length of transistors constant fill the table 3 for different values of widths for which the inverter becomes symmetric. Sr. # 1 2 3 Width of NMOS Width of PMOS 0 1 time 1 0 time
Table 3 Explain the affect on Input to Output delay due to different size of transistors. ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ Explain the affect of different size of transistors on the voltage curve of output. ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________ Explain the relationship of Vdd and output curve. ________________________________________________________________________ ________________________________________________________________________ ________________________________________________________________________
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Lab # 03: Basic Gates

1. Objective This lab consists of basic gates design. Students will design AND, XOR & XNOR gates at transistor level and observe their behavior.
Note: Make sure that you are familiar with DSCH2 and Microwind, and you have no problem in using the options of these tools. Study the lab manual before coming to the lab to have a better understanding of the problem.
2. Theory 2.1. Complementary MOS

A static CMOS gate is a combination of two networks, the pull-up network (PUN) and the pull-down network (PDN). The function of the PUN is to provide a connection between the output and Vdd anytime the output of the logic gate is meant to be 1. Similarly, the function of PDN is to connect the output to Vss when the output of the logic gate is meant to be 0. At a particular time, only one of these networks conducts.
2.2. Construction of CMOS

The PDN is constructed using NMOS devices because they produce strong zeros, while the PUN is constructed using PMOS devices due to their capability of producing strong ones. NMOS devices connected in series correspond to an AND function. Similarly, NMOS connected in parallel represent an OR function. In contrast, PMOS transistors connected in series conducts if both inputs are low which represent a NOR function. PMOS connected in parallel implement a NAND function. PUN and PDN of a CMOS structure are dual networks. This means that a parallel connection of transistors in the PUN corresponds to a series connection of transistors in the PDN. To construct a CMOS, only one network is designed and the other network is obtained using the duality principle. The complementary gates such as NOR, NAND, XNOR can be designed in a single stage, while the gates such as AND, OR, XOR require an additional inverter to complete the design. The number of transistors required to implement an N-input logic gate is 2N.
Complementary CMOS is explained in the book (Digital Integrated Circuits by Jan M. Rabaey) on page 236-240.
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3. Design of AND Gate

As it is mentioned that the AND can be obtained by connecting the NMOS devices in series. And by complementing it we get the PMOS devices in parallel. As AND gate is not a complementary gate so we need to place an inverter at second stage to complete the required circuit.
Figure 1. Test Circuit for AND gate
3. Lab Instructions 3.1. Schematic Design (DSCH2)

8. Open DSCH2. 9. Select the cmos025 foundry by selecting File Select Foundry. 10. Save the design frequently, during the elapse of the lab session. 11. Draw the circuit shown in Figure 1. 12. Check for floating lines, and if needed remove them. 13. Simulate the design and observe the results. 14. Create a Verilog file of the design.
3.2. Layout Editor (Microwind)

To see the layout of this design follow the following steps. 6. Open Microwind. 7. Select the cmos025 foundry by selecting File Select Foundry. 8. Select Compile Compile Verilog File. 9. Select the file that you have generated by DSCH2 and compile it. 10. Save the Layout.
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Design the circuits for XOR & XNOR in DSCH2 and fill the tables 1 & 2 respectively.
Sr. # 1 2 3 4
A 0 0 1 1
B 0 1 0 1
Out
Table 1. XOR Gate Results
Sr. # 1 2 3 4
A 0 0 1 1
B 0 1 0 1
Out
Table 2. XNOR Gate Results Draw the circuits designed for XOR & XNOR gates.
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Lab # 04: Combinational Logic (Full Adder)

1. Objective In this lab, students will implement a 1-bit full adder at transistor level. The software used will be DSCH.
Note: Make sure that you are familiar with DSCH2 and Microwind, and you have no problem in using the options of these tools. Study the lab manual before coming to the lab to have a better understanding of the problem.
2. Theory 2.1. Full Adder

A 1-bit full adder has 3 inputs and two outputs. 2 inputs are the numbers which are to be added and one input is the carry in. The outputs are sum and carry out.
A B Cin Figure 1. Block Diagram of Full Adder

Full Adder
Sum Cout
2.2. Truth Table for Full Adder

A 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Cin 0 1 1 0 1 0 0 1 Sum 0 0 0 1 0 1 1 1 Cout
Figure 2. Truth Table for Full Adder
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2.3. Logic Equations for Cout

The equation for Cout obtained from the truth table in figure 2 is Cout = ABC` + A`BC + AB`C + ABC By simplifying this equation, we get Cout = AB + AC + BC . (1) Cout = A (B+C) + BC (2)
3. Lab Instructions Design the circuit for Cout according to equations (1) & (2), and find out the difference in the design and results. Write the equation for sum and complete the full adder circuit. 4. Results and Observations
1) Number of transistors used for Cout using equation (1) _____________________________ 2) Number of transistors used for Cout using equation (2) _____________________________ 3) Input to Output delay for Cout using equation (1) _____________________________ 4) Input to Output delay for Cout using equation (2) _____________________________ 5) Equation for the sum _____________________________ 6) Number of transistors used for Sum _____________________________ 7) Input to Output delay for Sum _____________________________ 8) Attach the circuit diagram for complete circuit (optimized for area and speed).
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Lab # 05: CMOS Inverter(Layout Design)

1. Objective In this lab students will start working with layouts. Students will draw the layout of single NMOS & PMOS transistors, and finally a CMOS inverter will be designed.
Note: Make sure that you are familiar with Microwind. Study the lab manual before coming to the lab to have a better understanding of the problem. You must have a copy of the design rules while working in the lab.
2. Theory 2.1. Lambda-based design rules

In general, design rules and layout methodology based on the concept of provide a process and feature size-independent way of setting out mask dimensions to scale. All paths in all layers will be dimensioned in units and can be assigned any appropriate value which is compatible with the fabrication process. This means that we do not need to remember the design rules for different technologies but a single set of rules is used for all technologies. For example, the minimum width of poly silicon can be 2. We can find out the actual value for different technologies by simply putting the value of For 0.25u technology, 2 = 0.5um For 0.12u technology, 2 = 0.24um Lambda-based design rules are explained in the book (Basic VLSI Design by Douglas A. Pucknell) on page 73.
2.2. Lambda-based and micron-based design rules

For the lambda-based design rules, the rules are formulated in terms of a length unit of which is related to the resolution of the process. Lambda may be viewed as a bound on the width deviation of a feature from its idea size and also as a bound on the maximum misalignment of any one mask. A consequence of using the lambda-based rules is that every dimension must be rounded up to whole values and this leads to layouts which do not fully exploit the capabilities of the process. On the other hand, micron-based rule sets utilize the full advantages of the fabrication line capabilities and tighter layouts result. Suppose for example, that the micron-based rules allow the minimum poly silicon width to be of 0.48um when using 0.25 process. If we derive lambda-based design rules
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Department of Electrical Engineering COMSATS Institute of Information Technology for this then for 0.25 process will be 1.92. As is an integer value so the rounded value for is 2. More information can be found in the book (Basic VLSI Design by Douglas A. Pucknell) on page 79.
2.3. Architectural Issues

In all design processes, a logical and systematic approach is essential. Some guidelines can be set out as follows: 1. 2. 3. 4. 5. 6. 7. Define the requirements (properly and carefully). Partition the overall architecture into appropriate subsystems. Draw a floor plan of how the system is to map onto the silicon. Aim for regular structures so that design is largely a matter of replication. Convert each cell to layout. Carefully and thoroughly carry out a design rule check on each cell. Simulate the performance of each cell/subsystem. The whole design process will be greatly assisted if considerable care is taken with: The partitioning of the system so that there are clean and clear subsystems with a minimum interdependence and complexity of interconnection between them. The design simplification within subsystems so that architectures are adopted which allow the exploitation of a cellular design concept. This allows the system to be composed of relatively few standard cells which are replicated to form highly regular structures. Architectural Issues are explained in the book (Basic VLSI Design by Douglas A. Pucknell) on page 147.
3. Lab Instructions
Use 0.25 design rule file for the CMOS inverter design.
3.1. MOS Generator

For the layout of NMOS and PMOS we will use the MOS Generator tool. It is the first button of the second row in the palette. Clicking on this button will display the window shown in figure 1.
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Figure 1. MOS Generator Tool Select the device type (PMOS or NMOS). Set the number of figures to generate and then click on the Generate Device button. Click on the window and the device will be placed there.
3.2. Creating a CMOS Inverter

To create a CMOS Inverter, follow the following steps. 1. Draw layout for NMOS using the MOS Generator. 2. Draw layout for PMOS using the MOS Generator and place it above NMOS as shown in figure 2.
Figure 2. NMOS and PMOS

3. Connect the gates (poly silicon) and drains (metals) of the two devices as shown in figure 3.
Figure 3. Connecting gates and drains 4. Connect the Vdd supply (first button on third row) to the source of PMOS. 5. Connect the Ground (third button on third row) to the source of NMOS. 6. Click on the Design Rule Checker and correct the errors if any. The layout of CMOS Inverter is completed.
3.3. Adding Input and Output

To simulate the design, you need to add input and output to the device. The steps are given below: 1. Click on Add a Clock (fourth button on third row) and then click on the poly silicon (gate). A window will appear as shown in figure 4.
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Figure 4. Adding a Clock to input 2. Set the properties of clock according to figure 4 and then click on Assign button. 3. Click on the Visible Node (last button on third row) and then click on the drain of MOS. Then click on Assign button in the window displayed. 4. Click on the Add Virtual Capacitance (third button on second row) and then click on the output of the inverter. Set the desired value of capacitance and click on Assign button.
4. Simulation and Results 4.1 Simulating the Design

To simulate the design, click on the Run Simulation button. An error window will be displayed indicating that the N-Well region is floating. The reason of this error is that the N-Well is neither connected to Ground nor with Vdd supply. To remove this error, connect the N-Well with Vdd Supply. Final design of inverter is shown in figure 5. Again run the simulation and there should be no errors. Run the simulation for different values of capacitance and fill the table 1.
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Figure 5. Final design of the inverter
Sr. No 1 2 3 4 5 6 7 8 9 10
Virtual Capacitance Value 0.0001 pf 0.001 pf 0.010 pf 0.050 pf 0.100 pf 0.500 pf 1.000 pf 2.000 pf 5.000 pf 10.00 pf
1 Time
0 Time
Table 1. Effect of Load capacitance on Transition Times
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Lab # 06: AND Gate (Layout Design)

1. Objective In this lab, a CMOS AND gate will be implemented at layout level.
2. Theory 2.1. Schematic Design
Figure 1. Schematic of AND Gate There are 2 NMOS and 2 PMOS in the design excluding inverter. NMOS are in series while PMOS are in parallel. The important thing to note is that NMOS are connected such that the drain of one is connected to the source of other, and there is not any other connection at their joining. But in PMOS both the source and the drains are connected with each other and every terminal of the PMOS transistor is connected to some other wire in the circuit. This thing will result in a complex layout for PMOS as compared to NMOS. We can draw the same circuit as in the figure 2 or in figure 3 for having a different view of the circuit. The implementation of circuit given in figure 3 can be understood more easily so we will consider this circuit for our layout design.
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Figure 2. Schematic of AND Gate
Figure 3. Schematic of AND Gate
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3. Lab Instructions
Use 0.25 design rule file for the CMOS inverter design.
3.2. Creating a CMOS AND Gate

To create a CMOS AND gate, follow the following steps. 7. Draw layout for NMOS using the MOS Generator, this time set the number of figures to 2. 8. Draw layout for PMOS using the MOS Generator and place it above NMOS as shown in figure 4.
Figure 4. NMOS and PMOS
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9. Connect the gates (poly silicon) of PMOS and NMOS. As there is no connection at the junction of two NMOS transistors so we can remove this metal as shown in figure 5.
Figure 5. Connecting Gates and removing extra metal 10. Connect the drains of PMOS with each other and then the drain of NMOS as shown in figure 6.
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Figure 6. Connecting the drains of PMOS and NMOS 11. Place an inverter layout next to this design as shown in figure 7.
Figure 7. Placing an inverter layout

Department of Electrical Engineering COMSATS Institute of Information Technology 12. Connect the drain of first layout to the gate of the inverter as shown in figure 8.
Figure 8. Connecting drain of first layout with the inverter gate 13. Connect the source of NMOS with each other and connect them to Ground. 14. Connect the source of PMOS with each other and connect them to Vdd as shown in figure 9.
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Figure 9. The layout of CMOS AND gate is complete.
3.3. Adding Input and Output

To simulate the design, you need to add input and output to the device. The steps are given below: 5. Connect the inputs (two poly gates) with the metal 2 and then with metal 3 so that they come outside of the layout. Then do same with the output as shown in figure 10. 6. Assign the inputs and outputs as shown in the figure 10.
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Figure 10. Final Design of AND gate
4. Simulation and Results

Run the simulation and answer the following questions.
1) What is maximum output load capacitance that this gate can drive without affecting the transition times? ________________________________________________________ 2) What is the maximum output load capacitance where the transition times have no significant affect? ________________________________________________________ 3) What is the maximum output load capacitance where this gate can still operate correctly? ________________________________________________________ 4) What is the minimum output load capacitance where this gate has no affect on output? ________________________________________________________
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Lab # 07: Transistor Sizing for Large Capacitive Loads

1. Objective In this lab, a chain of inverters will be designed to drive a large output load capacitance (10pF).
2. Theory 2.1. Large Output Capacitance

Most of the time, the output of a transistor is connected to inputs of only a small number of transistors, so we do not need to worry for the load capacitance. But if the output of a transistor is connected to a device having high input capacitance or a large number of devices are attached to the output of the transistor, then the transistor with minimum width is unable to drive these devices. To solve this problem, we need to increase the width of the transistor but this will degrade the Tphl and Tplh. To balance these two problems we need to use the transistor in series where each transistor is bigger than the previous transistor and smaller than the next transistor.
2.2. Sizing Inverters for the specified Load Capacitance

The input capacitance of the inverter is 2.5fF. We are required to drive a load capacitance of 10pF. For this, we will have to decide the number of inverters in the chain and their sizes. We will use 2/1 ratio for the first inverter width and then use the formulae to decide the other inverter sizes. The number of stages can be found by the following formula Nopt = ln(load capacitance/input capacitance) Scaling factor for each inverter can be found by the following formula A = (load capacitance/input capacitance) 1/N
3. Homework
You must complete the following tasks before coming to lab to save the time. 1. Find the optimal number of stages of inverter Nopt. 2. Find the Scaling Factor A for the problem. 3. Find the total delay of the design.
4. Lab Instructions
1. Use 0.25 design rule file for the layout design. 2. Design each inverter separately and test each of them before combining with the other inverters. 3. Combine inverters one by one, and after adding each inverter simulate the design carefully. 4. Add the specified load capacitance, and check the timings of the design.

Input Capacitance: _______________________ Load Capacitance: _______________________ Number of stages Nopt: _______________________ Scaling Factor A: _______________________ Calculated Tphl: ________________________ Observed Tphl: ________________________ Calculated Tplh: ________________________ Observed Tplh: ________________________
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Lab # 08: Pass Transistor Logic

1. Objective In this lab, students will draw layout for the NAND gate with two different methods and compare the two designs.
2. Theory 2.1. Pass Transistor Logic

Pass-Transistor logic is widely used to reduce the number of transistors required to implement logic. In this technique the source-drains terminals of transistors can be drive by the inputs. The design consists of NMOS transistors but for inverter fully CMOS design is used. As NMOS passes a strong 0 and a weak 1, so in case of a 1 the output only charges up to Vdd VTn. Due to this reason, pass-transistor gates cannot be cascaded by connecting the output of a pass gate to the gate input of another passtransistor. Similar to CMOS, the voltage transfer curve (VTC) of pass-transistor logic is data dependent. A pure pass-transistor gate is not regenerative. Slow signal degradation will be observed after passing through a number of subsequent stages. This can be cater by the occasional insertion of a CMOS inverter.
2.2. Schematics of NAND gate
Figure 1. NAND Gate (schematic 1)

Figure 2. NAND Gate (schematic 2)
3. Lab Instructions
5. Use 0.25 design rule file for the layout design. 6. The two designs are quite similar so you will not need to draw each transistor separately. 7. Do not forget to save the design during the work.

Tplh for design 1: _____________________________ Tphl for design 1: _____________________________ Tplh for design 2: _____________________________ Tphl for design 2: _____________________________ Number of Transistors in design 1: ______________ Number of Transistors in design 2: ______________
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Sr. # 1 2 3 4 5 6
Comparison of Design 1 & Design 2 Design 1 Design 2
Briefly Explain which design should be used and Why?
_____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________ _____________________________________________________________
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Lab # 09: Manchester Carry Chain Adder Implementation

1. Objective In this lab, students will implement a 4 bit Manchester Carry Chain
Adder in DSCHV and Microwind. Note: Make sure that you are familiar with Microwind. Study the lab manual before coming to the lab to have a better understanding of the problem. You must have a copy of the design rules while working in the lab.
2. Schematics
VDD P0 P1 P2 P3 C3 Ci,0 G0 G1 G2 G3
C0
C1
C2
C3
Figure 1. Manchester Carry Chain
3. Lab Instructions
8. Use 0.25 design rule file for the layout design. 9. Do not forget to save the design during the work.
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Tplh for design: _____________________________ Tphl for design: _____________________________ Number of Transistors in design: ______________ Total Delay Cout: ______________ Latency: ______________
5. Draw complete 4-bit adder circuits.
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Lab # 10: Carry Save Multiplier Implementation

1. Objective In this lab, students will implement a 4 bit Carry Save Multiplier
Implementation in DSCHV and Microwind. Note: Make sure that you are familiar with Microwind. Study the lab manual before coming to the lab to have a better understanding of the problem. You must have a copy of the design rules while working in the lab.
2. Schematics
HA
HA
HA
HA
HA
FA
FA
FA
HA
FA
FA
FA
HA
FA
FA
HA
Vector Merging Adder
Figure 1. Carry Save Multiplier
3. Lab Instructions
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Tplh for design: _____________________________ Tphl for design: _____________________________ Number of Transistors in design: ______________ Latency: ______________
5. Draw complete 4-bit multiplier circuits.
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Lab # 11: Barrel Shifter Implementation

1. Objective In this lab, students will implement a 4 bit Barrel Shifter Implementation in DSCHV and Microwind.
2. Schematics
A3
B3
Sh1 A2 B2
Sh2 A1 B1 Sh3 A0 B0
: Data Wire : Control Wire
Sh0
Sh1
Sh2
Sh3
Figure 1. Barrel Shifter
3. Lab Instructions

5. Draw complete 4-bit Shifter circuits.
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Lab # 12: Nand ROM and NOR ROM Implementation

1. Objective In this lab, students will implement a 4 bit NAND ROM AND NOR ROM Implementation in DSCHV and Microwind.
2. Schematics
V DD Pull-up devices BL [0] BL [1] BL [2] VD Pull-up devices BL [3]
WL [0]
WL [0] GND WL [1] WL [1] WL [2] WL [2] GND WL [3] WL [3] BL [0] BL [1] BL [2] BL [3]
Figure 1. NOR ROM AND NAND ROM EXAMPLES
3. Lab Instructions
14. Use 0.25 design rule file for the layout design. 15. Do not forget to save the design during the work. 16. You have to store the following datas: 0110,1000,0111,1001.

Tplh for design1: _____________________________ Tphl for design1: _____________________________ Number of Transistors in design1: ______________
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Department of Electrical Engineering COMSATS Institute of Information Technology Latency1: ______________ Tplh for design2: _____________________________ Tphl for design2: _____________________________ Number of Transistors in design2: ______________ Latency2: ______________
5. Draw complete circuit diagrams.
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Lab # 13: SRAM Cell Implementation

1. Objective In this lab, students will implement a SRAM CELL in Microwind.
2. Schematics
W VD M2 M5 Q M1 B M4 Q M6
M3 B
Figure 1. SRAM CELL
3. Lab Instructions
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Lab # 14: DRAM Cell Implementation

1. Objective In this lab, students will implement a DRAM CELL in Microwind.
2. Schematics
B 1 WW RW M3 M1 CS X M2 WWL RWL X BL 1 BL 2 V DD V DD 2 V T DV V DD 2 V T B 2
Figure 1. DRAM CELL
3. Lab Instructions

Tplh for design: _____________________________ Tphl for design: _____________________________ Latency: ______________
VLSI Design EEE 434
Page 45 of 46
MICROWIND & DSCH USER'S MANUAL
11. Design Rules
11 Design Rules
11.1 Select a Design Rule File The software can handle various technologies. The process parameters are stored in files with the appendix '.RUL'. The default technology corresponds to a generic 6-metal 0.25m CMOS process. The default file is CMOS025.RUL. To select a new foundry, click on File -> Select Foundry and choose the appropriate technology in the list. To set a specific foundry as the default foundry, click Files -> Properties , 'Set as Default Technology'. 11.2 Start Microwind with a specific design Rule File To start Microwind with a specific design rule file, click with the right button of the mouse on the Microwind icon, select the "Properties" item, then the target. The default target may be: C:\microwind2\Microwind2.exe The command line may include two more parameters: The First parameter is the default mask file loaded at initialization The Second parameter is the design rule file loaded at initialization
The following command executes MICROWIND2 with a default mask file test.MSK and the rule file cmos018.RUL . C:\microwind2\Microwind2.exe test cmos018.rul
11.3 Nwell Design Rules r101 r102 r110 Minimum well size : 12 Between wells : 12 Minimum surface : 144 2
r101 r102 nwell p substrate nwell
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11. Design Rules
11.4 Diffusion Design Rules r201 Minimum N+ and P+ diffusion width : 4 r202 Between two P+ and N+ diffusions : 4 r203 Extra nwell after P+ diffusion : 6 r204 Between N+ diffusion and nwell : 6 r205 Border of well after N+ polarization 2 r206 Distance between Nwell and P+ polarization 6 r210 Minimum surface : 24 2
Nwell polarization r205
N+
r203
P+ diff r201 r204 N+ diff
r202
P+ diff nwell r206 P+ P+ polarization
11.5 Polysilicon Design Rules r301 r302 r303 r304 r305 r306 r307 r310 Polysilicon width : 2 Polysilicon gate on diffusion: 2 Polysilicon gate on diffusion for high voltage MOS: 4 Between two polysilicon boxes : 3 Polysilicon vs. other diffusion : 2 Diffusion after polysilicon : 4 Extra gate after polysilicium : 3 Minimum surface : 8 2
r305
P+dif r302 r304 r303 N+dif r307 High voltage MOS r306 r306
r301
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11. Design Rules
r305
P+diff r302 r306 nwell
r301
r304
r306 N+diff
r307
11.6 2nd Polysilicon Design Rules r311 r312 Polysilicon2 width : 2 Polysilicon2 gate on diffusion: 2
r311 Poly2
r312
11.7 Option Design Rules rOpt Border of option layer over diff N+ and diff P+
N+dif rOp
11.8 Contact Design Rules r401 r402 r403 r404 r405 r406 Contact width : 2 Between two contacts : 5 Extra diffusion over contact: 2 Extra poly over contact: 2 Extra metal over contact: 2 Distance between contact and poly gate: 3
r403 r406 gate diffusion metal r404 r402
r401 contact
contact
polysilicium r405
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11. Design Rules
11.9 Metal & Via Design Rules r501 r502 r510 Metal width : 4 Between two metals : 4 Minimum surface : 32 2
r501
metal
r502
metal
r601 r602 r603 r604 r605
Via width : 2 Between two Via: 5 Between Via and contact: 0 Extra metal over via: 2 Extra metal2 over via: 2 When r603=0, stacked via over contact is allowed
r604 r602 via r601 r603 contact metal2 Stacked via over contact when r603 is 0
11.10 Metal2 & Via2 Design Rules r701 r702 r710 Metal width: 4 Between two metal2 : 4 Minimum surface : 32 2
r701
metal2
r702
metal2
r801 r802 r804 r805
Via2 width : 2 Between two Via2: 5 Extra metal2 over via2: 2 Extra metal3 over via2: 2
r804 r802 via2 r801 Metal3
11.11 Metal3 & Via3 Design Rules r901 r902 r910 Metal3 width: 4 Between two metal3 : 4 Minimum surface : 32 2
r901 metal3 r902 metal3
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11. Design Rules

ra04 ra02 via3 ra01 Metal3,4
ra01 ra02 ra04 ra05
11.12 Metal4 & Via4 Design Rules rb01 rb02 rb10 Metal4 width: 4 Between two metal4 : 4 Minimum surface : 32 2
rb01 Metal4 rb02 Metal4
rc01 rc02 rc04 rc05
rc04 rc02 Via 4 Metal4,5
rc01
11.13 Metal5 & Via5 Design Rules rd01 rd02 rd10 Metal5 width: 8 Between two metal5 : 8 Minimum surface : 100 2
rd01 Metal5 rd02 Metal5
re01 re02 re04 re05
re01
re04
re02 Metal5,6
Via5
11.14 Metal6 Design Rules rf01 rf02 rf10 Metal6 width: 8 Between two metal6 : 15 Minimum surface : 300 2
rf01 Metal6 rf02 Metal6
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11. Design Rules
11.15 Pad Design Rules rp01 rp02 rp03 rp04 rp05 Pad width: 100 m Between two pads 100 m Opening in passivation v.s via : 5m Opening in passivation v.s metals: 5m Between pad and unrelated active area : 20 m
rp03
PAD rp02
rp01
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VLSI Design EEE 434 Lab Compendium

_______________________________________________ Date and signature of student:

_______________________________________________ Date and signature of lab instructor:

Department of Electrical Engineering COMSATS Institute of Information Technology

Department of Electrical Engineering COMSATS Institute of Information Technology

List of Lab Experiments

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Lab # 01: MOSFET Characteristics

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Figure 2 SR# 1 2 3 4 Input at Gate 0 0 1 1 Input at drain 0 1 0 1 Table 1 Output

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

VLSI Design EEE 434

2.5V, for the

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Lab # 02: Inverter Characteristics

Figure 1. Test Circuit for Inverter.

3. Lab Instructions 3.1. Schematic Design (DSCH2)

3.2. Layout Editor (Microwind)

4. Simulation (Microwind) and Results

Department of Electrical Engineering COMSATS Institute of Information Technology

Input to Output Delay

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Lab # 03: Basic Gates

2. Theory 2.1. Complementary MOS

2.2. Construction of CMOS

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

3. Design of AND Gate

Figure 1. Test Circuit for AND gate

3. Lab Instructions 3.1. Schematic Design (DSCH2)

3.2. Layout Editor (Microwind)

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Table 1. XOR Gate Results

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Lab # 04: Combinational Logic (Full Adder)

2. Theory 2.1. Full Adder

A B Cin Figure 1. Block Diagram of Full Adder

2.2. Truth Table for Full Adder

Figure 2. Truth Table for Full Adder

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

2.3. Logic Equations for Cout

VLSI Design EEE 434

Department of Electrical Engineering COMSATS Institute of Information Technology

Lab # 05: CMOS Inverter(Layout Design)

2. Theory 2.1. Lambda-based design rules

2.2. Lambda-based and micron-based design rules

VLSI Design EEE 434

2.3. Architectural Issues