Transmission Logic Circuits
Transmission Logic Circuits
Transmission Logic Circuits
Basic Operation
A transmission gate, or analog switch, is defined as an electronic element that will
selectively block or pass a signal level from the input to the output. This solid-state
switch is comprised of a pMOS transistor and nMOS transistor. The control gates are
biased in a complementary manner so that both transistors are either on or off.
The schematic diagram (Figure 1) includes the arbitrary labels for IN and OUT, as
the circuit will operate in an identical manner if those labels were reversed. This
design provides true bidirectional connectivity without degradation of the input signal.
The common circuit symbol for a transmission gate depicts the bidirectional nature of
the circuit's operation (Figure 2).
The connection scheme in Figure 3 is designed to isolate the I/O bus between the
microprocessor and the memory component, in case the memory is removed. The
SRAM is physically mounted on a removable memory card; the DS3690
transmission gate is used to isolate the various signals routed through the connector.
The ground connection from the SRAM is fed back through the connector to pull
down the DS3690 Chip Enable (active-low CE) pin. This action enables the
transmission gate when the memory card is installed.
The DS3690, with 26 independent channels, has the highest bus width available on
the market today. Most commercially available transmission gates are configured to
accommodate 2, 4, or 8 discrete signals. Using the Figure 3 example, this SRAM
requires 25 discrete signals to be isolated when the card is removed. Using
conventional 8-bit transmission gates, the designer would have to place four
separate components to isolate this SRAM, significantly increasing the final
component count and dedicated PC-board area.
Small Package Saves Board Space
The DS3690 is packaged in a 5mm x 11mm TQFN, requiring a mere 55mm² of PC-
board area for this entire bus-isolation effort. If the designer had selected 8-bit
transmission gates, the most aggressive packaging available is an SSOP that
occupies 51.5mm² each. Given a minimal allowance for signal routing, the four 8-bit
components would occupy well over 200mm² to accomplish the same function as a
single DS3690.
The additional board area required for multiple 8-bit components also complicates
the PC-board layout effort: dissimilar trace lengths can result in dissimilar signal
skew on critical timing events. Additionally, the four 8-bit components selected may
not have identical propagation delays, further aggravating the operational margin of
the final system. The DS3690's 26 parallel data channels (Figure 4) result in no
more than 1ns of channel-to-channel deskew.
Using the TQFN package, all signals can be conveniently routed in the physical
direction of the bus. Finally, for convenience and application flexibility, the designer
decides the assignment of a signal to one of the DS3690's 26 channels.
Note that I have removed the arrow that usually identifies the source. This is
because the source terminal actually changes according to whether V 1 is higher
than V2 or V2 is higher than V1. Also, the use of V1 and V2 instead of VIN and VOUT is
intended to emphasize that this single NMOS transistor can indeed conduct
current in both directions.
As you probably expected, this circuit is far from a perfect switch. One problem is
the source voltage: The current through the MOSFET is influenced by the source
voltage, and the source voltage depends on whatever signal is passing through
the switch. Indeed, if the gate is controlled by a driver that cannot exceed V DD, the
transistor can pass signals only as high as VDD minus the threshold voltage. This
threshold-voltage limitation is made even worse by the body effect, which comes
into play when the FET’s source and body terminals are not at the same potential.
When you analyze and ponder this switch, you recognize a certain asymmetry. For
example, if we are using this switch for pass-transistor logic, the NMOS can
effectively pass a logic-low signal but not a full logic-high signal. Is it possible to
modify the circuit in a way that will redress this asymmetry? If you are maintaining
a good CMOS mentality, your intuition might tell you that we could achieve better
overall performance by incorporating a PMOS transistor to compensate for the
deficiencies of the NMOS. In this case, your intuition is correct.
Here we have a PMOS in parallel with the NMOS; I used an “invert” circle to
identify the PMOS transistor. Note that the control signal applied to the PMOS is
the complement of the control signal applied to the NMOS; this is reminiscent of
the CMOS inverter, where a logic-high voltage turns on the NMOS and a logic-low
voltage turns on the PMOS.
This CMOS transmission gate is a synergistic system—the NMOS provides good
switch performance under conditions that are favorable for itself but not for the
PMOS, and the PMOS provides good switch performance under conditions that
are favorable for itself but not for the NMOS. The result is a simple yet effective
bidirectional voltage-controlled switch that is suitable for both analog and digital
applications.