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Atmel Avr Atmega48 PWM

The document discusses Atmel AVR PWM and fast PWM mode. It describes how the Timer/Counter0 module allows for accurate timing and wave generation. It explains that fast PWM mode operates with a single slope, counting from bottom to max then restarting at bottom. The output is cleared or set depending on the compare match between the counter and output compare register. This allows for higher operating frequencies well-suited for power regulation and DAC applications. Examples are provided to set fast PWM mode and vary PWM duty cycle to control LED brightness.

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Alfred J. Ngunyi
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398 views

Atmel Avr Atmega48 PWM

The document discusses Atmel AVR PWM and fast PWM mode. It describes how the Timer/Counter0 module allows for accurate timing and wave generation. It explains that fast PWM mode operates with a single slope, counting from bottom to max then restarting at bottom. The output is cleared or set depending on the compare match between the counter and output compare register. This allows for higher operating frequencies well-suited for power regulation and DAC applications. Examples are provided to set fast PWM mode and vary PWM duty cycle to control LED brightness.

Uploaded by

Alfred J. Ngunyi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Atmel AVR PWM

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Timer/Counter0
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units and with PWM support It allows accurate program execution timing and event management and wave generation

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ATMega48 Pinout

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Modes of Operation
Normal Mode Clear Timer on Compare Match (CTC) Mode Fast PWM Mode Phase Correct PWM Mode

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PWM Basic

PWM

PWM

PWM

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Fast PWM Mode


The fast PWM differs from the other PWM option by its single-slope operation The counter counts from BOTTOM to MAX then restarts from BOTTOM In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at BOTTOM In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM
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Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost
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10% PWM
#include <avr\io.h> int main(void) { DDRD = 0xFF; TCCR0A = 0x83; TCCR0B = 0x05; OCR0A = 0x19; while(1){ } return 0; }
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// Enable Fast PWM Mode // Set Prescaler to 1024 // 10% PWM

// AVRC302 LED Brightness Control using PWM #include <avr\io.h> #include <util\delay.h> int main(void) { DDRD = 0xFF; TCCR0A = 0x83; TCCR0B = 0x03; while(1) { OCR0A = 0x00; // 0% PWM _delay_ms(500); OCR0A = 0x40; // 25% PWM _delay_ms(500); OCR0A = 0x80; // 50% PWM _delay_ms(500); OCR0A = 0xC0; // 75% PWM _delay_ms(500); OCR0A = 0xFF; // 100% PWM _delay_ms(500); } return 0; } 11/18

TCCR0A Register

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TCCR0A Register

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TCCR0B Register

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The PWM waveform is generated by setting (or clearing) the OC0x register at the compare match between OCR0x and the TCNT0 The PWM frequency for the output can be calculated by the following equation

The N variable represents the prescale factor (1, 8, 64, 256, or 1024)
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If the OCR0 is set equal too BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle Setting the OCR0 equal to MAX will result in a constantly high or low output A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0 to toggle its logical level on each Compare Match at 0x80
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Lab Session
Thank You For more information please read
Atmel AVR ATmega48 Datasheet

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