7447an PDF
7447an PDF
7447an PDF
Features
s All circuit types feature lamp intensity modulation capability s Open-collector outputs drive indicators directly s Lamp-test provision s Leading/trailing zero suppression
Ordering Code:
Order Number DM7446AN DM7447AN Package Number N16E N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Connection Diagram
DS006518
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DM7446A, DM7447A
Function Table
Decimal or Function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT
H = HIGH level,
Inputs LT H H H H H H H H H H H H H H H H X H L RBI H X X X X X X X X X X X X X X X X L X D L L L L L L L L H H H H H H H H X L X C L L L L H H H H L L L L H H H H X L X B L L H H L L H H L L H H L L H H X L X A L H L H L H L H L H L H L H L H X L X
BI/RBO (Note 1) H H H H H H H H H H H H H H H H L L H a L H L L H L H L L L H H H L H H H H L b L L L L L H H L L L H H L H H H H H L c L L H L L L L L L L H L H H H H H H L
Outputs d L H L L H L L H L H L L H L L H H H L e L H L H H H L H L H L H H H L H H H L f L H H H L L L H L L H H L L L H H H L g H H L L L L L H L L L L L L L H H H L
Note
(Note 2)
L = LOW level,
X = Dont Care
Note 1: BI/RBO is a wire-AND logic serving as blanking input (BI) and/or ripple-blanking output (RBO). Note 2: The blanking input (BI) must be OPEN or held at a HIGH logic level when output functions 0 through 15 are desired. The ripple-blanking input (RBI) must be OPEN or HIGH if blanking of a decimal zero is not desired. Note 3: When a LOW logic level is applied directly to the blanking input (BI), all segment outputs are HIGH regardless of the level of any other input. Note 4: When ripple-blanking input (RBI) and inputs A, B, C, and D are at a LOW level with the lamp test input HIGH, all segment outputs go H and the ripple-blanking output (RBO) goes to a LOW level (response condition). Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held HIGH and a LOW is applied to the lamp-test input, all segment outputs are L.
Logic Diagram
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DM7446A, DM7447A
65C to +150C
0.2
40 8 70
A
mA mA
0.2
40 8 70
A
mA mA
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DM7446A, DM7447A
Min
Typ (Note 7)
Max 1.5
Units V V
2.4
A V mA A mA mA mA
BI/RBO Others
4 1.6 4 60 103
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DM7446A, DM7447A
Conditions VCC = Min, II = 12 mA VCC = Min IOH = Max VCC = Max, VO = 15V VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max, VI = 5.5V
Min
Typ (Note 9)
Max 1.5
Units V V
2.4
A V mA A mA mA mA
BI/RBO Others
4 1.6 4 60 103
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16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com