Common Power Format 1.

1 Tutorial

October 2009

Qi Wang Cadence Design Systems, Inc. LPC Vice Chair, LPC, Si2

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CPF 1.1 is a Si2 Standard released in September 2008. This tutorial is targeted for audience with basic knowledge of Si2 Standard CPF 1.0. For more information on CPF 1.0 and related training materials, please visit the following links:
http://www.si2.org/?page=811 (CPF 1.0 Spec) http://www.si2.org/?page=905 (CPF 1.0 Pocket Guide) http://www.si2.org/?page=907 (CPF 1.0 Tutorials)

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Highlights of New Features

Hierarchical flow for IP reuse Macro modeling Modes and transitions Derived and base power domains Isolation Level shifter State retention Others

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Hierarchical Flow Support

Objectives Enable IP reuse Reuse Design Hierarchy and better organization. Enable Low power Custom IP Integration and verification. Support Bottom-up and Top Down Flow Ensures Consistent Representation Consistent Integration style Consistent Verification Consistent Rules, semantics, precedence policy.

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Soft IP Reuse
IP is defined with multiple power structures and functionalities Can use any command to describe a block level power intent Simulation and static verification can be performed at the block design level before chip level integration and fixes can be made earlier with less schedule impact. Top level and block level power structures are linked together using

power domain mapping

Multiple levels of hierarchy are supported Main Features Merge and reconfigure power domains Reconfigure power rules Resolve precedence Integrate power modes

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Power Domain Mapping

Power domain mapping is the merging of a power domain at an upper

scope with another power domain at a lower scope

Semantics of domain mapping can be well defined Not all domains can be merged together Block level switchable domain can only be mapped into top level switchable domain if the shutoff conditions are the compatible Precedence rules of domain merging Top level domain rules cannot overwrite low level domain rules, etc. Power modes integration Domain states in block level power mode definition must be consistent with the power mode definitions of the mapped domain

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Hierarchical Flow Related Extensions

set_instance [ { instance | -instances_of_all_cell cell } [-port_mapping port_mapping_list] [-domain_mapping domain_mapping_list] [-parameter_mapping parameter_mapping_list] set_design module [-ports port_list] [-honor_boundary_port_domain] [-parameters parameter_value_list] get_parameter parameter_name

include

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Hierarchical CPF Example: Block Level CPF

Block1 I1
Iso Rule unswitched (PDOn)

I2
External Switchable (PDExt)

set_design Block1 ports { IsoExt } create_power_domain name PDOn instances { I1 } -default create_power_domain name PDExt instances { I2 } create_isolation_rule -name Iso1 from PDExt to PDOn\ isolation_condition IsoExt create_nominal_condition name on voltage 1.0 state on create_nominal_condition name off voltage 0 state off create_power_mode name all_on domain_conditions { ON@on Ext@on} create_power_mode name ext_off domain_conditions { ON@on Ext@off} end_design
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Hierarchical CPF Example: Top Level CPF

set design Top

unswitched

Switch Internal Switched

X2

X1 I1 I2

I1

I2

Iso Rule

Iso Rule

unswitched
set design Block1

External Switchable

unswithced
set design Block1

External Switchable

include Block1.cpf set_design Top ports { Iso Pwr } create_power_domain name AON create_power_domain name Int shutoff_condition { !Pwr } set_instance X1 domain_mapping { { PDOn AON } { PDExt AON } } design Block1 set_instance X2 domain_mapping { { PDOn AON } { PDExt Int } } design Block1 \ -port_mapping { {IsoExt Iso} } end_design
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Hierarchical CPF Example: Integrated View

Top

unswitched

Switch Internal Switched

X2

X1 I1 I2

I1

I2

Iso Rule

unswitched
Block1

un-switched

unswitched
Block1

Internal Switched

low level isolation rule is not required due to domain reconfiguration

low level domains are merged to the same domain at top

low level isolation rule is promoted to the top

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Reusable IP Example IP description

myIP
externally Switched State Retention set_design myIP -ports { save restore} \ -parameters { {one_ctrl 0}} create_power_domain name PD default if { [get_parameter one_ctrl] == 0 } { create_state_retention_rule name sr\ instances foo*\ -save_level save restore_level restore } else { create_state_retention_rule name sr \ instances foo* \ -restore_edge restore } end_design

Specify virtual ports: port save and restore do not exist in RTL

Specify parameters: declare parameter one_ctrl with default value 0.

externally switchable domain Use parameters: use the parameter like a string variable

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Reusable IP Example IP Usage

configure the IP to use single control retention (overwrite the
default parameter value)

specify the top level driver for the virtual ports

Instantiate IP CPF model

use the IP in a switchable domain

top

I1 myIP1
internal switchable
(PDRed) pso restore

myIP2

PCM

unswitched
(PDBlue)

include myIP.cpf ;#load in the CPF model for IP set_design top create_power_domain name PDBlue default create_power_domain name PDRed \ shutoff_condition pcm/pso base_domains PDBlue set_instance I1/myIP1 design myIP \ -domain_mapping { {PD PDRed}} \ -port_mapping { {restore pcm/restore}} \ -parameter_mapping { {one_control 1}} set_instance myIP2 design myIP \ domain_mapping { {PD PDBlue}} end_design

use the IP in an always-on domain

Instantiate the same IP CPF model in another instance

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Top Level Integrated View

top

I1 myIP1
internal switchable
(PDRed) pso restore

top

I1 myIP1

myIP2
PCM

PCM

pso restore

myIP2

unswitched
(PDBlue)

unswitched
(PDBlue)

Before Integration

After Integration

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Hard IP Support: Macro Model

Accurate simulation, implementation, and verification of custom

IP blocks or macros, such as embedded RAM, can be accomplished by defining the power features using
set_macro_model <name> power information content end_macro_model This independent definition provides verification and

implementation tools the power information necessary to implement and verify designs using these custom IP blocks.
Another benefit of the macro model definition is that it allows

the original IP block behavioral model to co-exist with the CPF definition to enable power aware verification at the design level.

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Macro Model Definition

Define a custom IP block as a macro model it contains one or

more of the following features:

Complete power domain support internally switchable, externally switchable, un-switched Power mode definition Input and output boundary isolation State retention for switchable domains Feed-through ports Floating ports Macro models must be black boxed for implementation and

Conformal verification, example would be an embedded RAM

Macro models are not black boxed for simulation

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Macro Model Example

VDD
D1 iso1 iso2 ret pwr D2

Multiple power ports (VDD, VPP) Unswitched (AON) Switches Internally Switched (PSO) State Retention Isolation Isolation Isolation Different types of domains Domain with retention
D4

Domain without retention Inputs isolated (D3) Inputs not isolated (D2) Outputs isolated (D4) Outputs not isolated (D5)

D3 NC F1 F2

Externally Switched (EXT) VPP

Internal crossing with isolation

D5

Feed-through (F1, F2) Floating port (NC)

VSS

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Macro Model Related Extensions

set_macro_model macro_cell_name end_macro_model set_wire_feedthrough_ports list_of_ports set_input_voltage_tolerance ports list_of_ports max_bias voltage set_floating_ports list_of_ports set_instance -model <model> .

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Macro Model Basics

Make sure all input and output pins are assigned to the correct

domain
An input pin assigned to a domain means the logic driven by the input pin inside the macro cell takes the power supply from this domain An output pin assigned to a domain means the logic driving the output pin inside the macro cell takes the power supply from this domain If a domain contains registers defined in the behavioral model,

declare the registers in the domain definition using instances option

Do not make an internal switchable domain as the default

domain for the macro model.

Choose an un-switched domain or an external switchable domain as the default domain of the macro model To avoid power shutoff behavior applied to unexpected behavioral code during simulation

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Defining Macro Domains

create_power_domain name PSO -shutoff_condition !pwr \ -base_domains AON -boundary_ports { D2 } -instances mem* notes on domain PSO active low input pwr turns power off port D2 is associated with PSO switch source is AON domain create_power_domain -name AON default \ -boundary_ports { D1 D4 iso* ret pwr} update_power_domain name AON \ primary_power_net VDD \
Isolation D1 iso1 iso2 ret pwr D2 Unswitched (AON) Switches Isolation Internally Switched State Retention Isolation VDD

D4

primary_ground_net VSS

D3 NC

Externally Switched (EXT)

D5

create_power_domain name EXT \ -boundary_ports { D3 D5 } update_power_domain name EXT \ -primary_power_net VPP \ -primary_ground_net VSS

F1 F2 VSS VPP

notes on domain EXT

port D5 is associated with EXT

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Defining Isolation Rules

Inputs are NOT isolated inside the macro model but it requires isolation when the drivers can be switched off in the design context\
Define an isolation rule for the input ports without isolation condition and with isolation_output to define what the valid clamp value should be when the driver is switched off.

Internal domain crossings

Isolation of macro internal domain crossings are expected to be part of the behavioral model. However, the isolation control condition in the isolation rules could be by simulation tool to generate automatic assertions to catch illegal power sequences.

Inputs or outputs isolated inside the macro model

Define isolation rule with -isolation_condition and -isolation_output. Condition must be expressed as a macro input port.

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Defining Isolation
VDD

create_isolation_rule name IsoOut \ -from PSO pins { D4 } \ isolation_condition !pwr \ isolation_output high notes on rule IsoOut port D4 belongs to the default domain AON create_isolation_rule name IsoInReq \

D1 iso1 iso2 ret pwr D2 Unswitched (AON) Switches Isolation Internally Switched State Retention Isolation Isolation

D4

to PSO pins { D2 } \ isolation_output low notes on rule IsoInReq D2 has no internal isolation. The rule specify a constraint: if D2 is driven by a switchable domain (after instantiated at top), it needs to be isolated to low when the domain is off create_isolation_rule name IsoIn \ to EXT pins { D3 } \ isolation_condition iso1 \ isolation_output low notes on rule IsoIn port D3 belongs to the domain EXT Innovation Through Collaboration Low Power Coalition

D3 NC F1 F2 VSS

Externally Switched (EXT)

D5

VPP

create_isolation_rule name IsoInt \ from EXT to PSO \ isolation_condition iso2 \ isolation_output low notes on rule IsoInt This rule covers an internal crossing

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Defining State Retention

VDD

create_state_retention_rule name PSO_RET \ -domain PSO secondary_domain AON \ -save_edge ret

D1 iso1 iso2 ret pwr Unswitched (AON) Switches Isolation Internally Switched State Retention Isolation Isolation

D4

notes on state retention rule Use the register names in instances if you want to apply the rule only to those registers No need to use update_state_retention_rule AON domain is the secondary domain of the retention logic by default

D2

D3 NC F1 F2 VSS

Externally Switched (EXT)

D5

VPP

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Defining Feed-through Ports

notes on defining feed-through ports must not have internal drivers may not be defined in multiple groups, i.e. the same pin can not appear in two feed through commands
VDD D1 iso1 iso2 ret pwr D2 Unswitched (AON) Switches Isolation Internally Switched State Retention Isolation Isolation

D4

D3 NC

Externally Switched (EXT)

D5

set_wire_feedthrough_ports { F1 F2 }

F1 F2 VSS VPP

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Defining Floating Ports

notes on defining floating ports not associated with any domain are ignored during verification
VDD D1 iso1 iso2 ret pwr D2 Unswitched (AON) Switches Isolation Internally Switched State Retention Isolation Isolation

D4

D3

set_floating_ports { NC }

NC F1 F2 VSS

Externally Switched (EXT)

D5

VPP

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Usage of the Macro Model in Design

The macro or hard IP cell is instantiated in RTL or netlist Non floating instance input must connect to nets in the design Power and ground nets may be connected in pre P&R design data, but that is not required and is ignored in analysis Power and ground nets must be connected in post P&R netlists Macro model power domains are integrated with parent block power

domains via -domain_mapping option

Domain mapping specifies which top level domain provides power supply to a block level domain P&R should connect power/ground pins of the macro cell to the parent block power/ground nets based on domain mapping Verification tools should check power/ground nets of the parent block connect to the correct macro instance ports Simulation should exercise the power behavior of the macro model based on the parent block or test bench domains that the macro model power domains are mapped to

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Integrate Macro Model At Top

set_design top create_power_domain name PDBlue default update_power_domain name PDBlue \ -primary_power_net VDD \ -primary_ground_net VSS create_power_domain name PDRed \ shutoff_condition pso \ -default_isolation_condition I1/iso1 \ -base_domains PDBlue -instances update_power_domain name PDRed \ -primary_power_net VDD_SW -primary_ground_net VSS end_design Innovation Through Collaboration Low Power Coalition
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VDD

I1
D1

VDD iso1 iso2 ret pwr D2 Unswitched (AON)

Isolation

Unswitched (PDBlue)

Switches Internally Switched State Retention Isolation Isolation

D4

Switches Internally Internally Switched Switched (PDRed) State Retention

D3 NC F1 F2 VSS

Externally Switched (EXT)

D5

VPP

Power Domain Mapping of Macro Model

VDD
set_design top create_power_domain name PDBlue default update_power_domain name PDBlue \ -primary_power_net VDD \ -primary_ground_net VSS create_power_domain name PDRed \ shutoff_condition pso \ -default_isolation_condition I1/iso1 \ -base_domains PDBlue -instances update_power_domain name PDRed \ -primary_power_net VDD_SW -primary_ground_net VSS set_instance ipInst domain_mapping \ { {AON PDBlue} {EXT PDRed}} include macro.cpf end_design
D1

VDD Unswitched (PDBlue)

iso1 iso2 ret pwr

Switches Internally Switched (PDRed) State Retention

D2

Internally Switched State Retention Isolation

Isolation
27

UnAlways switched On (AON)

Switches
D4

D3 NC F1 F2

Externally Externally Switched Switched (EXT) VPP

D5

VSS

VSS

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Integration of Macro Cell At Top

connect power
VDD

no isolation needed: the driver is already isolated no isolation needed: there is no domain crossing, i.e. both drivers and receivers are in the same domain isolation may be needed: if the driver domain can be off while the receiver is on, need to have an isolation rule at top level for isolation insertion No isolation needed: pin D3 is isolated internally and the crossing is not a domain crossing because domain PDRed merged with domain EXT
VDD D1

ret pwr D2

Isolation

Unswitched (PDBlue)

iso1 iso2 Unswitched (AON)

Switches Internally Switched State Retention Isolation Isolation

D4

Switches Internally Internally Switched Switched (PDRed) State Retention

D3 NC F1 F2 VSS

Externally Switched (EXT)

D5

VPP

No isolation needed: NC is a floating pin No isolation needed: F1 and F2 are internal feed-through. At top, the driver and receiver of the net are in the same domain
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VSS

connect ground

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Level Shifters Within Macro Cell

There is no need to describe level shifters between internal domain

crossing.
To describe level shifters at the boundary ports a macro cell, assign

the port to the proper power domain in the macro model Do not create level shifter rules in a macro model See also the slide Macro Model Basics
VDD_EXT VDD

Declare port I belonging to the power domain corresponding to VDD_EXT

Declare port O belonging to the power domain corresponding to VDD_EXT

I Core O

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level shifters
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Improved Power Mode and Mode Transition Modeling

In addition to on and off state, included new standby state A state where cells can maintain its value but cannot support computation A standby state can be achieved by source biasing or reverse body biasing Be able to define states of a power domain along with the conditions to

enable
Be able to specify mode transition time and domain transition time when a

mode transition happens

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Power Mode/Transition Related Extensions

create_nominal_condition -name string -voltage float [-ground_voltage float] [-state {on | off | standby}] [-pmos_bias_voltage float] [-nmos_bias_voltage float] create_power_domain -name power_domain [-active_state_conditions list_of_domain_active_state_conditions] Example: -active_state_conditions {1.0v@vdd_low_en 1.2v@{!vdd_low_en}} update_power_domain -name domain {| -transition_slope [float:]float | | -transition_latency {from_nom latency_list} | -transition_cycles {from_nom cycle_list clock_pin} }

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Secondary Power Domain

Follow pin connected to switchable power (primary power net)

Always-on(Constant) Power Switched Cells

Physical View

Secondary power pin connected to alwayson power

Always on domain PD1

Logical View
Switchable domain PD2

PD2 is a derived power domain of PD1 PD1 is the secondary domain of PD2
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Always on instance

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Secondary Power Pin

Additional power/ground pin other than the follow pins in standard cell

technology.
Special low power cells: Always on Isolation State retention level shifter power switch cell

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Modeling of Secondary Power Domain

Always-on instance There is no absolutely always on. An always-on instance is on/off in sync with the secondary power domain. If the corresponding secondary power domain is shut off, the always-on instance is off. Retention instance Retention cells state is retentive in sync with its secondary power domain Modes of operation On state Both primary and secondary domain are on Retention state Primary domain is off but secondary domain is on Deep-sleep state Both primary and secondary power domain are off
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Secondary Power Domain

Related Commands

identify_secondary_domain secondary_domain power_domain {instances instance_list | -cells cell_list } \ [ -domain power_domain [-from power_domain | -to power_domain]] create_state_retention_rule name string . [-secondary_domain power_domain] create_power_switch_rule name string [-secondary_domain power_domain]

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Isolation Enhancements
Support IP level isolation constraint Create an isolation rule with neither isolation_condition nor no_condition Support isolation cells without enable control Isolation rule with tristate isolation output Isolation insertion at arbitrary locations in the hierarchy Specified on update_isolation_rule Must be in appropriate power domain

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Isolation Enhancements
Related Commands
define_isolation_cell cells [-no_enable { high | low | hold} ] create_power_domain -name power_domain

[ -default_isolation_condition expression] create_isolation_rule -name string -isolation_condition expression [-isolation_output {high|low|hold|tristate}] [-no_condition] update_isolation _rules -names rule_list -within_hierarchy instance}

..

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Level Shifter Enhancements

Be able to instantiate the isolation logic in any logic hierarchy within a

power domain

update_level_shifter_rules -names rule_list \ { -location { from | to} | -within_hierarchy instance} | \ -cells cell_list | -prefix string }...

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State Retention Enhancements

Latch support Differentate rules for level sensitive save/restore retention from edge-

sensitive ones
Gate level simulation Identifies elements in simulation models that is on when the secondary supply is on and primary supply is off Exclude option Easier granulation to identify registers for SR

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State Retention Enhancements

Related Commands
define_state_retention_cell -cells cell_list -restore_function expression [-restore_check expression] [-save_function expression] [-save_check expression ] [-always_on_components component_list] create_state_retention_rule -name string [-exclude instance_list]

[ { -restore_edge expression | -restore_level expression } [ { -save_edge expression | -save_level expression } ]] [-target_type { flop | latch | both} ]

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Verification Related Exhancements

Be able to specify illegal power modes assert_illegal_domain_configuration . Assertion control Control of existing non-power aware assertions during power events Either by name or by domain Control of impact reset or suspended create_assertion_control -name string { -assertions assertion_list | -domains power_domain_list} [ -shutoff_condition expression ] [-type {reset | suspend} ]

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Other Enhancements
Support physically disjoint power domain Logically one power domain but physically located in different regions Power nets can be share or may not be shared update_power_domain -name domain { -equivalent_power_nets list_of_power_nets | -equivalent_ground_nets list_of_ground_nets } ... Handle equivalent control pins for power control signals Isolation, retention and power switch enables may be broken into multiple signals with non-overlapping sequence to reduce rush current set_equivalent_control_pins master pin pins pin_list { -domain domain | -rules rule_names}

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CPF 1.1 Related Information

CPF 1.1 Document CPF 1.1 Parser Si2 Low Power Coalition (LPC) Power Forward Initiative Practical Guide to Low Power Design

http://www.si2.org/?page=811 http://www.si2.org/?page=811 http://www.si2.org/?page=726 http://www.powerforward.org http://www.powerforward.org/lp_guide/

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