6 and c200 Chipset Specification Update

Intel 6 Series Chipset and Intel C200 Series Chipset
Specification Update
August 2012
Notice: Intel 6 Series Chipset and Intel C200 Series Chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are documented in this specification update.
Document Number: 324646-019
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Contents
Contents
Preface ......................................................................................................................7 Summary Tables of Changes......................................................................................8 Identification Information ....................................................................................... 12 PCH Device and Revision Identification ................................................................... 13 Errata ...................................................................................................................... 16 Specification Changes.............................................................................................. 25 Specification Clarifications ...................................................................................... 27 Documentation Changes .......................................................................................... 43
Revision History
Revision History
Revision 001 002 003 004 005 Initial Release Updated Top Markings PCH Device and Revision Identification Added Erratum 14: SATA Ports 2-5 Issue Updated Top Markings PCH Device and Revision Identification Added Intel Q65 Chipset to Top Markings and PCH Device and Revision Identification Specification Change 1: Intel Q65 SKU Addition Removed Specification Change 1 that went into Datasheet rev 003 Added Intel C200 Series Chipsets to Top Markings, PCH Device and Revision Identification, and Errata Added Intel Z68 Chipset to Top Markings and PCH Device and Revision Identification Updated Erratum 12: High-speed USB 2.0 Transmit Signal Amplitude Added Erratum 15: Intel ME Clock Throttling Failure Causes Hang Updated PCH Device and Revision Identification Erratum 12 and USB terminology changed for consistency on various errata Added Errata 16: USB Full-/low-speed Port Reset or Clear TT Buffer Request and 17: Intel 82579 Gigabit Ethernet Controller Transmission Issue Specification Change 1: LED Locate Intel Rapid Storage Technology Capability Removal Specification Clarifications: 1: Device 31 Function 6 Disable Bit, 2: LAN Disable Reset, 3: SGPIO Signal Usage, 4: RTCRST# and SRTCRST# Clarification, 5: PPM of 25 MHz Option for CLKOUTFLEX2, 6: SATA Alternate ID Enable Definition Update, 7: SATA Hot Plug Operation, 8: GPIO13 Voltage Tolerance, and 9: EHCI Configuration Programming Documentation Changes: 1: Addition of LPC Capability List Pointer Register, 2: Intel Smart Response Technology Functional Description Updates, 3: Addition of Legacy ATA Backwards Compatibility Registers, 4: DMI L1 Exit Latency Documentation Change, 5: Device 30 Function 0 Naming Consistency Change, 6: Gigabit Ethernet Capabilities and Status Registers Additions, 7: Measured ICC Corrections, and 8: Miscellaneous Documentation Corrections Added Specification Change: 2: Removal of S1 Support on Intel C200 Series Chipset Specification Clarifications: 10: PCH Thermal Sensor Temperature Range and 11: Secondary PCI Device Hiding Register Attribute Clarification Documentation Changes: 9: 25 MHz Flex Clock AC Timings, 10: Fan Speed Control Signals Functional Description Introduction, 11: SMBus/SMLink Timing Naming Corrections, 12: PCI Express* Lane Reversal Bit Change, 13: Auxiliary Trip Point Lock Bit Correction, 14: Top Swap Updates, and 15: Miscellaneous Documentation Corrections II Updated PCIe* PCH Device and Revision ID Table Documentation Change: PCI Express* Lane Reversal Bit Change Added Specification Clarifications: 12: GPIO Lock Clarification and 13: GPIO13 Voltage Well Documentation Change: 16: Ballout Documentation Changes Description Date January 2011
February 2011
February 2011
April 2011
April 2011
006
May 2011
007
July 2011
008
August 2011
009
September 2011
010
October 2011
Revision History
Revision 011
Description Added Specification Change: 3: A20GATE and A20M# Functionality Removal Specification Clarifications: 14: SLP_SUS# Clarifications and 15: PME_Turn_Off TLP Documentation Changes: 17: Integrated Digital Display Audio Device and Revision IDs and 18: Miscellaneous Documentation Corrections III Updated Specification Changes: 3: A20GATE and A20M# Functionality Removal Documentation Changes: 8: Miscellaneous Documentation Corrections and 17: Integrated Digital Display Audio Device and Revision IDs Added Erratum: 18: USB RMH Think Time Issue Specification Clarifications: 16: GPIO Clarifications and 17: Power Button Override and Deep S4/S5 Documentation Changes: 19: SPI Documentation Changes, 20: Miscellaneous Documentation Corrections IV, and 21: Mobile SFF PCH Ballout Updated Revision History content and formatting PCH Device and Revision ID Table Specification Clarification: 16: GPIO Clarifications Documentation Changes: 8: Miscellaneous Documentation Corrections, 10: Fan Speed Control Signals Functional Description Introduction, 11: SMBus/SMLink Timing Naming Corrections, and 16: Ballout Documentation Changes Added Specification Clarification: 18: Power Management Clarifications Added Erratum: 19: Intel AMT and Intel Standard Manageability KT/SOL Interrupt Status Cleared Prematurely Documentation Changes: 22: Thermal Sensor Thermometer Read Register Updates, 23: DC Inputs Characteristics Tables Corrections, 24: CPU_PWR_FLR Removal, and 25: Miscellaneous Documentation Corrections V. Added Erratum: 20: Incorrect IRQ(x) Vector Returned for 8259 Interrupts With RAEOI Enabled. Specification Clarification: 19: t203 Deep S3/S4 Exit Clarification. Documentation Changes: 26: PCI Express Initialization Registers Corrections, 27: VccSus3_3 Description, 28: Register Default Value Corrections, and 29: Miscellaneous Documentation Corrections VI. Updated Documentation Change: 29: Miscellaneous Documentation Corrections VI. Added Erratum: 21: USB RMH False Disconnect Issue. Documentation Change: 30: Miscellaneous Documentation Correction VII. Updated Specification Clarification: 18: Power Management Clarifications. Added Erratum: 22: USB RMH Think Time Issue. Documentation Changes: 31: Function Level Reset Pending Status Register Correction and 32: Miscellaneous Documentation Correction VIII. Updated Specification Clarification: 16: GPIO Clarifications. Added Specification Clarifications: 20: RAID 1 Description, 21: V_PROC_IO Definition, 22: Manageability Signals Clarifications, and 23: ACPRESENT Definition. Documentation Change: 33: SPI Required Region Correction. Updated Documentation Changes: 6: Gigabit Ethernet Capabilities and Status Registers Additions, 28: Register Default Value Corrections, 29: Miscellaneous Documentation Corrections VI, and 33: SPI Required Region Correction. Added Erratum: 23: Packet Loss on Intel 82579 Gigabit Ethernet Controller. Specification Clarification: 24: SPI Overview. Documentation Changes: 34: High Precision Event Timers Functional Description and 35: Miscellaneous Documentation Corrections IX.
Date
November 2011
012
December 2011
013 014
January 2012
February 2012
015
April 2012
016
May 2012
017
June 2012
018
July 2012
019
August 2012
Revision History
Preface
Preface
This document is an update to the specifications contained in the Affected Documents/Related Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published.
Affected Documents/Related Documents

Title Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet Document Number 324645-006
Nomenclature
Errata are design defects or errors. Errata may cause the behavior of the PCH to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present in all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specifications impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.
Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the product. Intel may fix some of the errata in a future stepping of the component and account for the other outstanding issues through documentation or specification changes as noted. These tables use the following notations:
Codes Used in Summary Tables

Stepping
X: (No mark) or (Blank box): This erratum is fixed or not applicable in listed stepping or Specification Change does not apply to listed stepping. Erratum exists in the stepping indicated. Specification Change that applies to this stepping.
Status
Doc: Plan Fix: Fixed: No Fix: Document change or update will be implemented. This erratum may be fixed in a future stepping of the product. This erratum has been previously fixed. There are no plans to fix this erratum.
Row
Change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.
Errata
Erratum Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Stepping Status B2 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X B3 X X X X X X X X X X X X X No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix Fixed No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix No Fix USB Isoch In Transfer Error Issue USB Full-/low-speed Device Removal Issue USB Babble Detected with SW Overscheduling USB Full-/low-speed EOP Issue USB PLL Control FSM Not Getting Reset on Global Reset Asynchronous Retries Prioritized Over Periodic Transfers USB FS/LS Incorrect Number of Retries Incorrect Data for FS/LS USB Periodic IN Transaction HDMI* 222 MHz Electrical Compliance Testing Failures SATA Signal Voltage Level Violation SATA Differential Return Loss Violations High-speed USB 2.0 Transmit Signal Amplitude Delayed Periodic Traffic Timeout Issue SATA Ports 2-5 Issue Intel ME Clock Throttling Failure Causes Hang USB Full-/Low-speed Port Reset or Clear TT Buffer Request Intel 82579 Gigabit Ethernet Controller Transmission Issue USB RMH Think Time Issue Intel AMT and Intel Standard Manageability KT/SOL Interrupt Status Cleared Prematurely Incorrect IRQ(x) Vector Returned for 8259 Interrupts With RAEOI Enabled USB RMH False Disconnect Issue USB RMH Think Time Issue Packet Loss on Intel 82579 Gigabit Ethernet Controller ERRATA
Specification Changes
Spec Change Number 1 2 3 Stepping SPECIFICATION CHANGES B2 X X X B3 X X X LED Locate Intel Rapid Storage Technology Capability Removal Removal of S1 Support on Intel C200 Series Chipset A20GATE and A20M# Functionality Removal
Specification Clarifications
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Document Revision 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 SPECIFICATION CLARIFICATIONS Device 31 Function 6 Disable Bit LAN Disable Reset SGPIO Signal Usage RTCRST# and SRTCRST# Clarification PPM of 25 MHz Option for CLKOUTFLEX2 SATA Alternate ID Enable Definition Update SATA Hot Plug Operation GPIO13 Voltage Tolerance EHCI Configuration Programming PCH Thermal Sensor Temperature Range Secondary PCI Device Hiding Register Attribute Clarification GPIO Lock Clarification GPIO13 Voltage Well SLP_SUS# Clarifications PME_Turn_Off TLP GPIO Clarifications Power Button Override and Deep S4/S5 Power Management Clarifications t203 Deep S3/S4 Exit Clarification RAID 1 Description V_PROC_IO Definition Manageability Signals Clarifications ACPRESENT Definition SPI Overview
Documentation Changes (Sheet 1 of 2)

No. 1 2 3 4 5 6 7 8 9 10 11 Document Revision 006 006 006 006 006 006 006 006 006 006 006 DOCUMENTATION CHANGES Addition of LPC Capability List Pointer Register Intel Smart Response Technology Functional Description Updates Addition of Legacy ATA Backwards Compatibility Registers DMI L1 Exit Latency Documentation Change Device 30 Function 0 Naming Consistency Change Gigabit Ethernet Capabilities and Status Registers Additions Measured ICC Corrections Miscellaneous Documentation Corrections 25 MHz Flex Clock AC Timings Fan Speed Control Signals Functional Description Introduction SMBus/SMLink Timing Naming Corrections
10
Documentation Changes (Sheet 2 of 2)

No. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Document Revision 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 006 DOCUMENTATION CHANGES PCI Express* Lane Reversal Bit Change Auxiliary Trip Point Lock Bit Correction Top Swap Updates Miscellaneous Documentation Corrections II Ballout Documentation Changes Integrated Digital Display Audio Device and Revision IDs Miscellaneous Documentation Corrections III SPI Documentation Changes Miscellaneous Documentation Corrections IV Mobile SFF PCH Ballout Thermal Sensor Thermometer Read Register Updates DC Inputs Characteristics Tables Corrections CPU_PWR_FLR Removal Miscellaneous Documentation Corrections V PCI Express* Initialization Registers Corrections VccSus3_3 Description Register Default Value Corrections Miscellaneous Documentation Corrections VI Miscellaneous Documentation Corrections VII Function Level Reset Pending Status Register Correction Miscellaneous Documentation Correction VIII SPI Required Region Correction High Precision Event Timers Functional Description Miscellaneous Documentation Correction IX
11
Identification Information
Identification Information
Markings
PCH Stepping B2 B2 B2 B2 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 S-Spec SLH82 SLH84 SLH9C SLH9D SLJ4D SLJ4E SLJ4A SLJ4F SLJ49 SLJ4C SLJ4B SLJ4J SLJ4H SLJ4G SLJ4M SLJ4L SLJ4N SLJ4P SLJ4K Top Marking BD82H67 BD82P67 BD82HM67 BD82HM65 BD82Q67 BD82Q65 BD82B65 BD82Z68 BD82H67 BD82P67 BD82H61 BD82C202 BD82C204 BD82C206 BD82QM67 BD82UM67 BD82HM67 BD82HM65 BD82QS67 Intel H67 Chipset Intel P67 Chipset Intel HM67 Chipset Intel HM65 Chipset Intel Q67 Chipset Intel Q65 Chipset Intel B65 Chipset Intel Z68 Chipset Intel H67 Chipset Intel P67 Chipset Intel H61 Chipset Intel C202 Chipset Intel C204 Chipset Intel C206 Chipset Intel QM67 Chipset Intel UM67 Chipset Intel HM67 Chipset Intel HM65 Chipset Intel QS67 Chipset Notes
12
PCH Device and Revision Identification

The Revision ID (RID) is an 8-bit register located at offset 08h in the PCI header of every PCI device and function. The assigned value is based on the products stepping. PCH Device and Revision ID Table (Sheet 1 of 3)
Device Function Description Dev ID 1C4Eh 1C4Ch 1C50h 1C4Ah 1C44h 1C46h 1C5Ch D31:F0 LPC 1C52h 1C54h 1C56h 1C4Fh 1C47h 1C4Bh 1C49h 1C4Dh 1C00h 1C02h 2822h2 1C04h2 1C06h2 1C01h 1C03h 282Ah2 1C05h2 04h 04h 04h 04h 04h 04h 04h B2 Rev ID B3 Rev ID 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h 05h Comments Intel Q67 Chipset Intel Q65 Chipset Intel B65 Chipset Intel H67 Chipset Intel Z68 Chipset Intel P67 Chipset Intel H61 Chipset Intel C202 Chipset Intel C204 Chipset Intel C206 Chipset Intel QM67 Chipset Intel UM67 Chipset Intel HM67 Chipset Intel HM65 Chipset Intel QS67 Chipset Desktop: Non-AHCI and Non-RAID Mode (Ports 0-3) Desktop: AHCI (Ports 0-5) Desktop: Intel Rapid Storage Technology RAID with or without Intel Smart Response Technology (Ports 0-5) (AIE bit = 0) Desktop (all RAID-capable SKUs except Intel Z68 Chipset): RAID Capable3 (Ports 0-5) (AIE bit = 1) Desktop (Intel Z68 Chipset only): RAID Capable3 (Ports 0-5) (AIE bit = 1) Mobile: Non-AHCI and Non-RAID Mode (Ports 0-3) Mobile: AHCI (Ports 0-5) Mobile: Intel Rapid Storage Technology RAID (Ports 0-5) (AIE bit = 0) Mobile: RAID Capable3 (Ports 0-5) (AIE bit = 1)
D31:F2
SATA1
04h 04h 04h 04h 04h 04h
05h 05h 05h 05h 05h 05h
13
PCH Device and Revision ID Table (Sheet 2 of 3)

Device Function Description Dev ID 1C08h D31:F5 SATA1,4 1C09h D31:F3 D31:F6 SMBus Thermal 1C22h 1C24h 1C25h D30:F0 PCI to PCI Bridge 244Eh 1C25h 2448h D29:F0 D26:F0 D27:F0 USB EHCI #1 USB EHCI #2 Intel HD Audio PCI Express* Port 1 1C26h 1C2Dh 1C20h 1C10h D28:F0 244Eh 2448h 1C12h D28:F1 PCI Express Port 2 244Eh 2448h 1C14h D28:F2 PCI Express Port 3 244Eh 2448h 1C16h D28:F3 PCI Express Port 4 244Eh 2448h 1C18h D28:F4 PCI Express Port 5 244Eh 2448h 1C1Ah D28:F5 PCI Express Port 6 244Eh 2448h 1C1Ch D28:F6 PCI Express Port 7 244Eh 2448h 1C1Eh D28:F7 PCI Express Port 8 244Eh 2448h 04h 04h 04h 04h A4h 04h A4h 04h 04h 04h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h B4h 05h 05h 05h 05h A5h 05h A5h 05h 05h 05h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h B5h Desktop and Mobile (When D28:F0:ECh:bit 1= 0) Desktop (When D28:F0:ECh:bit 1 = 1) Mobile (When D28:F0:ECh:bit 1 = 1) Desktop and Mobile (When D28:F1:ECh:bit 1 = 0) Desktop (When D28:F1:ECh:bit 1 = 1) Mobile (When D28:F1:ECh:bit 1 = 1) Desktop and Mobile (When D28:F2:ECh:bit 1 = 0) Desktop (When D28:F2:ECh:bit 1 = 1) Mobile (When D28:F2:ECh:bit 1 = 1) Desktop and Mobile (When D28:F3:ECh:bit 1 = 0) Desktop (When D28:F3:ECh:bit 1 = 1) Mobile (When D28:F3:ECh:bit 1 = 1) Desktop and Mobile (When D28:F4:ECh:bit 1 = 0) Desktop (When D28:F4:ECh:bit 1 = 1) Mobile (When D28:F4:ECh:bit 1 = 1) Desktop and Mobile (When D28:F5:ECh:bit 1 = 0) Desktop (When D28:F5:ECh:bit 1 = 1) Mobile (When D28:F5:ECh:bit 1 = 1) Desktop and Mobile (When D28:F6:ECh:bit 1 = 0) Desktop (When D28:F6:ECh:bit 1 = 1) Mobile (When D28:F6:ECh:bit 1 = 1) Desktop and Mobile (When D28:F7:ECh:bit 1 = 0) Desktop (When D28:F7:ECh:bit 1 = 1) Mobile (When D28:F7:ECh:bit 1 = 1) Desktop (When D30:F0:4Ch:bit 29 = 1) Desktop (When D30:F0:4Ch:bit 29 = 0) Mobile (When D30:F0:4Ch:bit 29 = 1) Mobile (When D30:F0:4Ch:bit 29 = 0) B2 Rev ID 04h B3 Rev ID 05h Comments Desktop: Non-AHCI and Non-RAID Mode (Ports 4 and 5) Mobile: Non-AHCI and Non-RAID Mode (Ports 4 and 5)
14
PCH Device and Revision ID Table (Sheet 3 of 3)

Device Function D25:F0 D22:F0 D22:F1 D22:F2 D22:F3 Description LAN Intel ME Interface #1 Intel ME Interface #2 IDE-R KT NOTES:
1. 2. 3. 4. 5. 6. PCH contains two SATA controllers. The SATA Device ID is dependent upon which SATA mode is selected by BIOS and what RAID capabilities exist in the SKU. The SATA RAID Controller Device ID is dependent upon: 1) the AIE bit setting (bit 7 of D31:F2:Offset 9Ch); and 2) (only when the AIE bit is 1) which desktop PCH SKU is in the system. A third party RAID driver is required to utilize the SATA ports of the PCH for RAID functionality. Intel Rapid Storage Technology and Intel Smart Response Technology require that the AIE bit is set to 0. SATA Controller 2 (D31:F5) is only visible when D31:F2 CC.SCC =01h. LAN Device ID is loaded from EEPROM. If EEPROM contains either 0000h or FFFFh in the Device ID location, then 1C33h is used. Refer to the appropriate Intel GbE physical layer Transceiver (PHY) datasheet for LAN Device IDs. This table shows the default PCI Express Function Number-to-Root Port mapping. Function numbers for a given root port are assignable through the Root Port Function Number and Hide for PCI Express Root Ports register (RCBA+0404h).
Dev ID 1C33h5 1C3Ah 1C3Bh 1C3Ch 1C3Dh
B2 Rev ID 04h 04h 04h 04h 04h
B3 Rev ID 05h 05h 05h 05h 05h
Comments
15
Errata
Errata
1.
Problem:
USB Isoch In Transfer Error Issue

If a USB full-speed inbound isochronous transaction with a packet length 190 bytes or greater is started near the end of a microframe the PCH may see more than 189 bytes in the next microframe. If the PCH sees more than 189 bytes for a microframe an error will be sent to software and the isochronous transfer will be lost. If a single data packet is lost no perceptible impact for the end user is expected. Intel has only observed the issue in a synthetic test environment where precise control of packet scheduling is available, and has not observed this failure in its compatibility validation testing. Isochronous traffic is periodic and cannot be retried thus it is considered good practice for software to schedule isochronous transactions to start at the beginning of a microframe. Known software solutions follow this practice. To sensitize the system to the issue additional traffic such as other isochronous transactions or retries of asynchronous transactions would be required to push the inbound isochronous transaction to the end of the microframe.
Implication:
Note:
Workaround: None. Status: No Plan to Fix.
2.
Problem:
USB Full-/low-speed Device Removal Issue

If two or more USB full-/low-speed devices are connected to the same USB controller, the devices are not suspended, and one device is removed, one or more of the devices remaining in the system may be affected by the disconnect. The implication is device dependent. A device may experience a delayed transaction, stall and be recovered via software, or stall and require a reset such as a hot plug to resume normal functionality. No Plan to Fix.
Implication:
Workaround: None. Status:
16
Errata
3.
Problem:
USB Babble Detected with SW Overscheduling

If software violates USB periodic scheduling rules for full-speed isochronous traffic by overscheduling, the RMH may not handle the error condition properly and return a completion split with more data than the length expected. If the RMH returns more data than expected, the endpoint will detect packet babble for that transaction and the packet will be dropped. Since overscheduling occurred to create the error condition, the packet would be dropped regardless of RMH behavior. If a single isochronous data packet is lost, no perceptible impact to the end user is expected. USB software overscheduling occurs when the amount of data scheduled for a microframe exceeds the maximum budget. This is an error condition that violates the USB periodic scheduling rule. This failure has only been recreated synthetically with USB software intentionally overscheduling traffic to hit the error condition. No Plan to Fix.
Implication:
Note:
Note:
4.
Problem:
USB Full-/low-speed EOP Issue

If the EOP of the last packet in a USB Isochronous split transaction (Transaction >189 bytes) is dropped or delayed 3 ms or longer the following may occur: If there are no other pending low-speed or full-speed transactions the RMH will not send SOF, or Keep-Alive. Devices connected to the RMH will interpret this condition as idle and will enter suspend. If there is other pending low-speed or full-speed transactions, the RMH will drop the isochronous transaction and resume normal operation.
Implication: If there are no other transactions pending, the RMH is unaware a device entered suspend and may starting sending a transaction without waking the device. The implication is device dependent, but a device may stall and require a reset to resume functionality. If there are other transactions present, only the initial isochronous transaction may be lost. The loss of a single isochronous transaction may not result in end user perceptible impact. Note: Intel has only observed this failure when using software that does not comply with the USB specification and violates the hardware isochronous scheduling threshold by terminating transactions that are already in progress. No Plan to Fix.
5.
Problem: Implication:
USB PLL Control FSM not Getting Reset on Global Reset

Intel 6 Series Chipset and Intel C200 Series Chipset USB PLL may not lock if a Global Reset occurs early during a cold boot sequence. USB interface would not be functional an additional cold boot would be necessary to recover. No Plan to Fix.
17
Errata
6.
Asynchronous Retries Prioritized Over Periodic Transfers

The integrated USB RMH incorrectly prioritizes full-speed and low-speed asynchronous retries over dispatchable periodic transfers. Periodic transfers may be delayed or aborted. If the asynchronous retry latency causes the periodic transfer to be aborted, the impact varies depending on the nature of periodic transfer: If a periodic interrupt transfer is aborted, the data may be recovered by the next instance of the interrupt or the data could be dropped. If a periodic isochronous transfer is aborted, the data will be dropped. A single dropped periodic transaction should not be noticeable by end user.
Note:
This issue has only been seen in a synthetic environment. The USB spec does not consider the occasional loss of periodic traffic a violation. No Plan to Fix.
7.
Problem:
USB FS/LS Incorrect Number of Retries

A USB low-speed Transaction may be retried more than three times, and a USB full-speed transaction may be retried less than three times if all of the following conditions are met: A USB low-speed transaction with errors, or the first retry of the transaction occurs near the end of a microframe, and there is not enough time to complete another retry of the low-speed transaction in the same microframe. There is pending USB full-speed traffic and there is enough time left in the microframe to complete one or more attempts of the full-speed transaction. Both the low-speed and full-speed transactions must be asynchronous (Bulk/Control) and must have the same direction either in or out.
Note: Implication:
Note: Per the USB EHCI Specification a transaction with errors should be attempted a maximum of 3 times if it continues to fail. For low-speed transactions the extra retry(s) allow a transaction additional chance(s) to recover regardless of if the full-speed transaction has errors or not. If the full-speed transactions also have errors, the PCH may retry the transaction fewer times than required, stalling the device prematurely. Once stalled, the implication is software dependent, but the device may be reset by software.
Workaround: None. Status: No Plan to Fix.
18
Errata
8.
Problem:
Incorrect Data for FS/LS USB Periodic IN Transaction

The Periodic Frame list entry in DRAM for a USB FS or LS Periodic IN transaction may incorrectly get some of its data from a prior Periodic IN transaction which was initiated very late into the preceding microframe. It is considered good practice for software to schedule Periodic Transactions at the start of a microframe. However Periodic transactions may occur late into a microframe due to the following cases outlined below: Asynchronous transaction starting near the end of the proceeding microframe gets Asynchronously retried.
Note:
Transactions getting Asynchronous retried would only occur for ill behaved USB device or USB port with a signal integrity issue Or Two Periodic transactions are scheduled by software to occur in the same microframe and the first needs to push the second Periodic IN transaction to the end of the microframe boundary.
Implication: Note: Status:
The implication will be device, driver or operating system specific. This issue has only been observed in a synthetic test environment. No Plan to Fix.
Workaround: None.
9.
HDMI* 222 MHz Electrical Compliance Testing Failures

HDMI* 222 MHz electrical compliance testing may show eye diagram and jitter test failures on Intel 6 Series Chipset and Intel C200 Series Chipset. No functional or visual failures have been observed by Intel. HDMI electrical compliance failures may be seen at 222 MHz Deep Color Mode. This issue does not prevent HDMI with Deep Color Logo certification as no failures have been seen with 74.25 MHz Deep Color Mode (720P 60 Hz or 1080P 30 Hz) as required HDMI Compliance Test Specification. No Plan to Fix.
10.
Problem:
SATA Signal Voltage Level Violation

SATA transmit buffers have been designed to maximize performance and robustness over a variety of routing scenarios. As a result, the SATA transmit signaling voltage levels may exceed the maximum motherboard TX connector and device RX connector voltage specifications as defined in section 7.2.1 of the Serial ATA specification, rev 3.0. This issue applies to Gen 1 (1.5 Gb/s) and Gen 2 (3.0 Gb/s). None known. No Plan to Fix.
Implication: Status:
Workaround: None.
19
Errata
11.
SATA Differential Return Loss Violations

The Intel 6 Series Chipset and Intel C200 Series Chipset SATA buffer capacitance may be higher than expected. There are no known functional failures. This may cause a violation of the SATA-IO* compliance test for Receiver or Transmitter Differential Return Loss.
Workaround: None. Note: Status: Intel has obtained a waiver for the SATA-IO building block status. No Plan to Fix.
12.
Problem:
High-speed USB 2.0 Transmit Signal Amplitude

Intel 6 Series Chipset and Intel C200 Series Chipset High-speed USB 2.0 transmit signal amplitude may exceed the USB 2.0 specification. USB 2.0 Specification Transmit Eye template maximum boundary is +/- 525 mV following bit transitions and +/- 475 mV for non-transitional bit patterns. USB 2.0 Specification VHSOH maximum is 440 mV.
Implication: Status:
There are no known functional failures. No Plan to Fix.
Workaround: None.
13.
Delayed Periodic Traffic Timeout Issue

If a periodic interrupt transaction is pushed out to the x+4 microframe boundary, the RMH may not wait for the transaction to timeout before starting the next transaction. If the next full-speed or low-speed transaction is intended for the same device targeted by the periodic interrupt, the successful completion of that transaction is device dependent and cannot be guaranteed. The implication may differ depending on the nature of the transaction: If the transaction is asynchronous and the device does not respond, it will eventually be retried with no impact. If the transaction is periodic and the device does not respond, the transfer may be dropped. A single dropped periodic transaction should not be noticeable by end user.
Note: Status:
This issue has only been seen in a synthetic environment. No Plan to Fix.
Workaround: None.
20
Errata
14.
Problem:
SATA Ports 2-5 Issue

Due to a circuit design issue on Intel 6 Series Chipset and Intel C200 Series Chipset, electrical lifetime wear out may affect clock distribution for SATA ports 2-5. This may manifest itself as a functional issue on SATA ports 2-5 over time. The electrical lifetime wear out may result in device oxide degradation which over time can cause drain to gate leakage current. This issue has time, temperature and voltage sensitivities.
Implication:
The increased leakage current may result in an unstable clock and potentially functional issues on SATA ports 2-5 in the form of receive errors, transmit errors, and unrecognized drives. Data saved or stored prior to functional issues on a SATA device will be retrievable if connected to a working SATA port. SATA ports 0-1 are not affected by this design issue as they have separate clock generation circuitry.
Workaround: Intel has worked with board and system manufacturers to identify and implement solutions for affected systems. Use only SATA ports 0-1. Use an add-in PCIe SATA bridge solution. Status: Fixed. For steppings affected, see the Summary Table of Changes. This issue has been resolved with a silicon stepping for all Intel 6 Series Chipset and Intel C200 Series Chipset incorporating a minor metal layer change. The fix does not impact the designed functionality and electrical specifications of the Intel 6 Series Chipset and Intel C200 Series Chipset.
15.
Problem:
Intel ME Clock Throttling Failure Causes Hang

When the Intel Management Engine (Intel ME) firmware sets the internal clock frequency, the Intel ME clock may stop toggling, potentially causing the Intel Management Engine Interface to become unresponsive. Parts that exhibit this issue may hang during POST. No functional failures have been seen due to this issue.
Implication: Note:
Workaround: An Intel ME Firmware code change has been identified and may be implemented as a workaround for this erratum. Status: No Plan to Fix.
21
Errata
16.
Problem:
USB Full-/Low-speed Port Reset or Clear TT Buffer Request

One or more full-/low-speed USB devices on the same RMH controller may be affected if the devices are not suspended and either (a) software issues a Port Reset OR (b) software issues a Clear TT Buffer request to a port executing a split full-/low-speed Asynchronous Out command. The Small window of exposure for full-speed device is around 1.5 microseconds and around 12 microseconds for a low-speed device.
The affected port may stall or receive stale data for a newly arrived split transfer occurring at the time of the Port Reset or Clear TT Buffer request. This issue has only been observed in a synthetic test environment. No Plan to Fix.
Workaround: None.
17.
Problem:
Intel 82579 Gigabit Ethernet Controller Transmission Issue

Intel 82579 Gigabit Ethernet Controller with the Intel 6 Series Chipset and Intel C200 Series Chipset and Intel ME Firmware 7.x 5 MB may stop transmitting during a data transfer. Intel 82579 Gigabit Ethernet Controller may stop transmitting packets, the link LED will blink, and a power cycle may be required to resume transmission activity. This issue has only been observed in a focused test environment where data is constantly transferred over an extended period of time (more than approximately 3 hours).
Implication: Note:
Workaround: A combination of Intel ME Firmware code change and Intel 82579 Gigabit Ethernet Controller LAN Driver update has been identified and may be implemented as a workaround for this erratum. Status: No Plan to Fix.
18.
Problem: Implication: Note: Status:
USB RMH Think Time Issue

The Intel 6 Series Chipset and Intel C200 Series Chipset USB RMH Think Time may exceed its declared value in the RMH hub descriptor register of 8 full-speed bit times. If the OS USB driver fully subscribes a USB microframe, full-/low-speed transactions may exceed the microframe boundary. No functional failures have been observed. No Plan to Fix.
Workaround: None.
22
Errata
19.
Problem:
Intel AMT and Intel Standard Manageability KT/SOL Interrupt Status Cleared Prematurely
A read of the Intel AMT and Intel Standard Manageability enabled SOL KTIIR (KT Interrupt Identification Register) or KTLSR (KT Line Status Register) that occurs simultaneous to the arrival of an SOL Host interrupt event may result in a read of the Interrupt Status (INTSTS) bit 0 returning the status of No Pending interrupt to Host despite KTLSR reporting a serviceable event. Implication of a missed SOL Host interrupt is software implementation dependent. Subsequent interrupts not aligned to a KTIIR or KTLSR read will clear 0 bit 0 (INTSTS) to indicate a pending interrupt to the Host.
Implication:
Workaround: Software should not rely on reading only bit 0 (INTSTS) of the KTIIR register and should also poll the KTLSR to determine if a SOL Host interrupt is pending. Status: No Plan to Fix.
20.
Problem:
Incorrect IRQ(x) Vector Returned for 8259 Interrupts With RAEOI Enabled
If multiple interrupts are active prior to an interrupt acknowledge cycle with Rotating Automatic End of Interrupt (RAEOI) mode of operation enabled for 8259 interrupts (0-7), an incorrect IRQ(x) vector may be returned to the processor. Implications of an incorrect IRQ(x) vector being returned to the CPU are SW implementation dependent. This issue has only been observed in a synthetic test environment. No Plan to Fix.
Workaround: None.
21.
Problem:
USB RMH False Disconnect Issue

The PCH may falsely detect a USB High-Speed (HS) device disconnect if all of the following conditions are met: The HS Device is connected through the Rate Matching Hub (RMH) of the PCHs EHCI controller. The device is resuming from selective suspend or port reset. The resume occurs within a narrow time window during the EOP (End of Packet) portion of the SOF (Start of Frame) Packet on the USB bus.
Implication:
Following the false disconnect, the HS device will be automatically re-enumerated. The system implication will depend on the resume event cause: If the resume event is a port reset, a second port reset will be automatically generated and the device re-enumerated. No end user impact is expected. If the resume event is a hardware or software initiated resume from selective suspend, the implication will be device and software specific, which may result in anomalous system behavior.
Note:
If the HS device is a hub, then all of the devices behind the hub, independent of the device speed, may also be re-enumerated. No Plan to Fix.
23
Errata
22.
Problem: Implication: Note: Status:
USB RMH Think Time Issue

The USB RMH Think Time may exceed its declared value in the RMH hub descriptor register of 8 full-speed bit times. If the USB driver fully subscribes a USB microframe, LS/FS transactions may exceed the microframe boundary. No functional failures have been observed. No Plan to Fix.
Workaround: None.
23.
Problem:
Packet Loss on Intel 82579 Gigabit Ethernet Controller

Systems with Intel 6 Series Chipset and Intel C200 Series Chipset using the Intel 82579 Gigabit Ethernet Controller may experience packet Loss at 100 Mbps and 1 Gbps speeds when the link between the Intel 82579 Gigabit Ethernet Controller and the PCH Integrated LAN Controller is exiting the Low Power Link (K1) State. Implications are application and Internet Protocol dependent.
Implication:
Workaround: A BIOS code change has been identified and may be implemented as a workaround for this erratum. Status: No Plan to Fix.
24
1. LED Locate Intel Rapid Storage Technology (Intel RST) Capability Removal
Bit 7 of 14.4.1.10 RSTFIntel RST Feature Capabilities Register (ABAR + C8hC9h), previously known as the LED Locate (LEDL) bit, is changed to Reserved.
2.
Removal of S1 Support on Intel C200 Series Chipset

The S1 power state is no longer supported for the Intel C200 Series Chipset. The change is made accordingly in the Datasheet.
3.
A20GATE and A20M# Functionality Removal

A20M# functionality is not supported on processors on Intel 6 Series Chipset and Intel C200 Series Chipset-based platforms. a. Table 2-9 is updated as shown:
Name A20GATE Type I Description A20 Gate: Functionality reserved. A20M# functionality is not supported.
b. Table 3-4 is updated as shown:

Signal Name Power Well Driver During Reset Processor Interface A20GATE Core External Micro controller or Pull-up Static Off Off S0/S1 S3 S4/S5
c. Table 3-5 is updated as shown:

Signal Name Power Well Driver During Reset Processor Interface A20GATE Core External Micro controller or Pull-up Static Static Off Off C-x states S0/S1 S3 S4/S5
d. A20M# is removed as a VLW message from section 5.12. e. Section 5.12.1.1 is removed. f. A20GATE/A20M# removed from section 5.12.2.1. g. A20M# removed from section 5.12.3.
25
h. 13.1.27 ULKMC USB Legacy Keyboard / Mouse Control Register bit 5 is modified as shown:
Bit Description A20Gate Pass-Through Enable (A20PASSEN) R/W. 5 0 = Disable. 1 = Enable. Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to port 60h and 64h does not result in the setting of the SMI status bits. NOTE: A20M# functionality is not supported.
i. Section 13.7.3 name changed from PORT92Fast A20 and Init Register to PORT92Init Register and bit 1 is modified as shown:
Bit 1 Description Alternate A20 Gate (ALT_A20_GATE) R/W. Functionality reserved. A20M# functionality is not supported.
26
1. Device 31 Function 6 Disable Bit
Section 10.1.45 FDFunction Disable Register bit 24 is changed as shown:
Bit 24 Description Thermal Sensor Registers Disable (TTD) R/W. Default is 0. 0 = Thermal Sensor Registers (D31:F6) are enabled. 1 = Thermal Sensor Registers (D31:F6) are disabled.
2.
LAN Disable Reset

Section 10.1.44 BUCBacked Up Control Register bit 5 is changed as shown:
Bit LAN Disable R/W. 0 = LAN is Enabled 1 = LAN is Disabled. 5 Changing the internal GbE controller from disabled to enabled requires a system reset (write of 0Eh to CF9h (RST_CNT Register)) immediately after clearing the LAN disable bit. A reset is not required if changing the bit from enabled to disabled. This bit is locked by the Function Disable SUS Well Lockdown register. Once locked, this bit cannot be changed by software. Description
3.
SGPIO Signal Usage

The following note is added at the conclusion of the first paragraph of section 5.16.13: Intel does not validate all possible usage cases of this feature. Customers should validate their specific design implementation on their own platforms.
4.
RTCRST# and SRTCRST# Clarification

The following replaces section 5.13.10.6: RTCRST# is used to reset PCH registers in the RTC Well to their default value. If a jumper is used on this pin, it should only be pulled low when system is in the G3 state and then replaced to the default jumper position. Upon booting, BIOS should recognize that RTCRST# was asserted and clear internal PCH registers accordingly. It is imperative that this signal not be pulled low in the S0 to S5 states. SRTCRST# is used to reset portions of the Intel Management Engine and should not be connected to a jumper or button on the platform. The only time this signal gets asserted (driven low in combination with RTCRST#) should be when the coin cell battery is removed or not installed and the platform is in the G3 state. Pulling this
27
signal low independently (without RTCRST# also being driven low) may cause the platform to enter an indeterminate state. Similar to RTCRST#, it is imperative that SRTCRST# not be pulled low in the S0 to S5 states. See Figure 2-2 which demonstrates the proper circuit connection of these pins.
5.
PPM of 25 MHz Option for CLKOUTFLEX2

The following note is added to table 4-2 and applies to CLKOUFLEX2: The 25 MHz output option for CLKOUTFLEX2 is derived from the 25 MHz crystal input to the PCH. The PPM of the 25 MHz output is equivalent to that of the crystal.
6.
SATA Alternate ID Enable Definition Update

Section 14.1.33 D31:F2:Offset 9Ch is changed as follows: a. Name of register is changed from SCLKGC-SATA Clock General Configuration Register to SGC-SATA General Configuration Register b. Bit 7 is redefined as shown:
Bit 7 (non-RAID Capable SKUs Only) Description
Reserved
7 (RAID Capable SKUs Only)
Alternate ID Enable (AIE) R/WO. 0 = Clearing this bit when in RAID mode, the SATA Controller located at Device 31: Function 2 will report its Device ID as 2822h for all Desktop SKUs of the PCH or 282Ah for all Mobile SKUs of the PCH. Clearing this bit is required for the Intel Rapid Storage Technology driver (including the Microsoft* Windows Vista* OS and later in-box version of the driver) to load on the platform. Intel Smart Response Technology also requires that the bit be cleared in order to be enabled on the platform. 1 = Setting this bit when in RAID mode, the SATA Controller located at Device 31: Function 2 will report its Device ID as called out in the table below for Desktop SKUs or 1C05h for all Mobile SKUs of the chipset. This setting will prevent the Intel Rapid Storage Technology driver (including the Microsoft Windows* OS in-box version of the driver) from loading on the platform. During the Microsoft Windows OS installation, the user will be required to "load' (formerly done by pressing the F6 button on the keyboard) the appropriate RAID storage driver that is enabled by this setting. D31:F2 Configured in RAID Mode with AIE = 1 (Desktop Only) Feature Vector Register 0 (FVEC0) RAID Capability Bit 1 0 0 1 1 RAID Capability Bit 0 0 1 0 1 D31:F2 Dev ID Not applicable Not applicable 1C04h 1C06h
This field is reset by PLTRST#. BIOS is required to reprogram the value of this bit after resuming from S3, S4 and S5.
28
c. the following is added to the list of items describing when Intel Rapid Storage Technology is not available in section 5.16.7: 2. The SATA controller is programmed in RAID mode, but the AIE bit (D31:F2:Offset 9Ch bit 7) is set to 1. d. The SATA D31:F2 Device ID table is updated; see PCH Device and Revision Identification section in this document.
7.
SATA Hot Plug Operation

Section 5.16.5 Hot Plug Operation is modified as shown below. Section 5.16.5.1 is removed. The PCH supports Hot Plug Surprise removal and Insertion Notification. An internal SATA port with a Mechanical Presence Switch can support PARTIAL and SLUMBER with Hot Plug Enabled. Software can take advantage of power savings in the low power states while enabling hot plug operation. Refer to chapter 7 of the AHCI specification for details.
8.
GPIO13 Voltage Tolerance

GPIO13 is powered by VccSusHDA well and therefore, the voltage tolerance value varies according to the voltage connected to VccSusHDA. The following clarifications are made: a. Table 2-24, GPIO13 Tolerance is change from 3.3 V to 3.3 V or 1.5 V and the following note is added to table 2-24: GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. b. The following note is added to GPIO13 in table 3-2 as note 16: GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Pin tolerance is determined by VccSusHDA voltage. c. The following note is added to HDA_DOCK_RST#/GPIO13 in table 3-3 as note 24: HDA_DOCK_RST#/GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Pin tolerance is determined by VccSusHDA voltage.
9.
EHCI Configuration Programming

a. Section 16.1.31 EHCIIR1EHCI Initialization Register 1 bits 18 and 10:9 are changed as shown:
Bit 18 10:9 Description EHCI Initialization Register 1 Field 2 R/W. BIOS may write to this bit field. EHCI Initialization Register 1 Field 1 R/W. BIOS may write to this bit field.
b. Section 16.1.32 EHCIIR2EHCI Initialization Register 2 is modified as shown:

Bit 31:30 29 28:20 19 18:12 Reserved EHCI Initialization Register 2 Field 6 R/W. BIOS may write to this bit field. Reserved EHCI Initialization Register 2 Field 5 R/W. BIOS may write to this bit field. Reserved Description
29
Bit 11 10 9 8 7:6 5 4:0
Description EHCI Initialization Register 2 Field 4 R/W. BIOS may write to this bit field. EHCI Initialization Register 2 Field 3 R/W. BIOS may write to this bit field. Reserved EHCI Initialization Register 2 Field 2 R/W. BIOS may write to this bit field. Reserved EHCI Initialization Register 2 Field 1 R/W. BIOS may write to this bit field. Reserved
c. Section 16.1.38 EHCIIR3EHCI Initialization Register 3 bits 32:22 are changed as shown:
Bit 23:22 Description EHCI Initialization Register 3 Field 1 R/W. BIOS may write to this bit field.
d. Section 16.1.39 EHCIIR4EHCI Initialization Register 4 bits 17 and 15 are changed as shown:
Bit 17 15 Description EHCI Initialization Register 4 Field 2 R/W. BIOS may write to this bit field. EHCI Initialization Register 4 Field 1 R/W. BIOS may write to this bit field.
10.
PCH Thermal Sensor Temperature Range

The following sentence is added at the end of the first paragraph of section 5.21.1: The normal readable temperature range of the PCH thermal sensor is from 53 C to 134 C. Note that some parts can read down to 43 C but this is part to part dependent.
11.
Secondary PCI Device Hiding Register Attribute Clarification

The following is added to the register summary of section 11.1.20 SPDHSecondary PCI Device Hiding Register: Bits 3:0 are Read Only on PCI Interface-disabled SKUs; bits 3:0 are Read/Write for PCI Interface-enabled SKUs (see Section 1.3 for full details on SKU definition).
12.
GPIO Lock Clarification

The following note is added to section 5.15.4 GPIO Registers Lockdown: Note: All other GPIO registers not listed here are not be locked by GLE.
13.
GPIO13 Voltage Well

The power well for GPIO13 in table 2-24 is changed from Suspend to HDA Suspend.
30
14.
SLP_SUS# Clarifications
a. The definition for SLP_SUS# is replaced as follows in table 2-8 Power Management Interface Signals:
Name Type Description Deep S4/S5 Indication: When asserted (low), this signal indicates PCH is in Deep S4/S5 state where internal Sus power is shut off for enhanced power saving. When deasserted (high), this signal indicates exit from Deep S4/S5 state and Sus power can be applied to PCH. If Deep S4/S5 is not supported, then this pin can be left unconnected. This pin is in the DSW power well.
SLP_SUS#
b. SLP_SUS# is added to Table 3-2 Power Plane and States for Output and I/O Signals for Desktop Configurations.
Signal Name Power Plane During Reset Immediately after Reset S0/S1 S3 S4/S5
Power Management SLP_SUS# DSW Low High High High High
c. SLP_SUS# is added to Table 3-3. Power Plane and States for Output and I/O Signals for Mobile Configurations
Signal Name Power Plane During Reset Immediately after Reset C-x states S0/S1 S3 S4/S5
Power Management SLP_SUS# DSW Low High High High High High
31
d. The following section is added after section 5.13.10.6. SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior The following tables summarize SUSPWRDNACK/SUSWARN#/GPIO30 pin behavior. SUSPWRDNACK/SUSWARN#/GPIO30 Steady State Pin Behavior
Deep S4/S5 (Supported /Not-Supp orted) GPIO30 Input/Out put (Determine by GP_IO_SEL bit)
Pin Value in S0
Pin Value in Sx/Moff
Pin Value in Sx/M3
Pin Value in Deep S4/S5
SUSPWRDNACK
Not Supported
Native
Depends on Intel ME power package and power source (Note 1) 1 High-Z Depends on GPIO30 output data value
Depends on Intel ME power package and power source (Note 1) 1 (Note 2) High-Z Depends on GPIO30 output data value
Intel ME drives low
Off
SUSWARN#
Supported Don't Care
Native IN
1 High-Z Depends on GPIO30 output data value
Off Off
GPIO30
Don't Care
OUT
Off
NOTES: 1. Intel ME will drive SPDA pin high if power package 1 or DC. Intel ME will drive SPDA pin low if power package 2. 2. If entering Deep S4/S5, pin will assert and become undriven ("Off") when suspend well drops upon Deep S4/S5 entry.
SUSPWRDNACK during reset

Reset Type Power Cycle Reset Reset Initiated By Host or Intel ME (Power Cycle Reset) Host Global Reset (using CF9GR) Intel ME HW/WDT expiration SPDA Value Intel ME drives low Host drives low (using BIOS flow) Intel ME drives low Steady-state value
e. The following note is added to Figure 8-1 G3 w/RTC Loss to S4/S5 (With Deep S4/S5 Support) Timing Diagram: VccSus rail ramps up later in comparison to VccDSW due to assumption that SLP_SUS# is used to control power to VccSus.
32
15.
PME_Turn_Off TLP
The following note is added to section 5.2.2.1 S3/S4/S5 Support: Note: The PME_Turn_Off TLP messaging flow is also issued during a host reset with and without power cycle. Refer to table 5-38 for a list of host reset sources.
16.
GPIO Clarifications
a. Table 2-24 is replaced as following:
Table 2-24 General Purpose I/O Signals (Sheet 1 of 5)

Tolerance Power Well Blink Capability No No No Glitch Protection during Power-On Sequence No No No GPI Event Support No No No
Name
Type
Default
Description
GPIO75 GPIO74 GPIO73 (Mobile Only)
I/O I/O I/O
3.3 V 3.3 V 3.3 V
Suspend Suspend Suspend
Native Native Native Native (Mobile Only) GPI (Desktop Only) Native
Multiplexed with SML1DATA10 Multiplexed with SML1ALERT#/PCHHOT#10 Multiplexed with PCIECLKRQ0#
GPIO72
I/O
3.3 V
Suspend
No
No
No
Mobile: Multiplexed with BATLOW#. Desktop: Unmultiplexed; requires pull-up resistor4. Desktop: Multiplexed with TACH[7:6] Mobile: Used as GPIO only Desktop: Multiplexed with TACH[5:4] Mobile: Used as GPIO only Multiplexed with CLKOUTFLEX3 Multiplexed with CLKOUTFLEX2 Multiplexed with CLKOUTFLEX1 Multiplexed with CLKOUTFLEX0 Multiplexed with SLP_S5# Multiplexed with SUSCLK Multiplexed with SUS_STAT# Multiplexed with SML0ALERT# Multiplexed with OC0#10 Multiplexed with SML1CLK Unmultiplexed Mobile: Multiplexed with PEG_B_CLKRQ#
GPIO[71: 70] GPIO[69: 68] GPIO67 GPIO66 GPIO65 GPIO64 GPIO63 GPIO62 GPIO61 GPIO60 GPIO59 GPIO58 GPIO57 GPIO56 (Mobile Only)
I/O
3.3 V
Core
No
No
No
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Core Core Core Core Core Suspend Suspend Suspend Suspend Suspend Suspend Suspend Suspend
GPI Native Native Native Native Native Native Native Native Native Native GPI Native
No No No No No No No No No No No No No
No No No No No Yes No Yes No No No Yes No
33

Tolerance Power Well Blink Capability Glitch Protection during Power-On Sequence No GPI Event Support
Name
Type
Default
Description
GPIO558
I/O
3.3 V
Core
Native
No
No
Desktop: Multiplexed with GNT3# Mobile: Used as GPIO only Desktop: Multiplexed with REQ3#10. Mobile: Used as GPIO only Desktop: Multiplexed with GNT2# Mobile: Used as GPIO only Desktop: Multiplexed with REQ2#10. Mobile: Used as GPIO only Desktop: Multiplexed with GNT1# Mobile: Used as GPIO only Desktop: Multiplexed with REQ1#10. Mobile: Used as GPIO only Multiplexed with SATA5GP and TEMP_ALERT# Multiplexed with SDATAOUT1. Multiplexed with PEG_A_CLKRQ# Multiplexed with PCIECLKRQ7# Multiplexed with PCIECLKRQ6# Multiplexed with PCIECLKRQ5# Multiplexed with OC[4:1]#10. Multiplexed with SDATAOUT0. Multiplexed with SLOAD. Multiplexed with SATA3GP. Multiplexed with SATA2GP. Multiplexed with NMI#. Multiplexed with STP_PCI# Mobile: Multiplexed with HDA_DOCK_EN# (Mobile Only)4. Desktop: Used as GPIO only Unmultiplexed (Desktop Only)
GPIO54
I/O
5.0 V
Core
Native
No
No
No
GPIO538
I/O
3.3 V
Core
Native
No
No
No
GPIO52
I/O
5.0 V
Core
Native
No
No
No
GPIO518
I/O
3.3 V
Core
Native
No
No
No
GPIO50
I/O
5.0 V
Core
Native
No
No
No
GPIO49 GPIO48 GPIO47 (Mobile Only) GPIO46 GPIO45 GPIO44 GPIO[43: 40] GPIO39 GPIO38 GPIO378 GPIO368 GPIO35 GPIO34
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Core Core Suspend Suspend Suspend Suspend Suspend Core Core Core Core Core Core
GPI GPI Native Native Native Native Native GPI GPI GPI GPI GPO GPI
GPIO33
I/O
3.3 V
Core
GPO
No
No
No
GPIO32 (not available in Mobile)
I/O
3.3 V
Core
GPO, Native (Mobile only)
No
No
No
Mobile Only: Used as CLKRUN#, unavailable as GPIO4.
34

Tolerance Power Well Blink Capability Glitch Protection during Power-On Sequence GPI Event Support
Name
Type
Default
Description
Multiplexed with ACPRESENT. Mobile: This GPIO pin is permanently appropriated by the Intel ME for ACPRESENT function. Desktop: This pin is only GPIO31. NOTES: 1. Toggling this pin at a frequency higher than 10 Hz is not supported. 2. GPIO_USE_SEL[31] is internally hardwired to a lb, which means GPIO mode is permanently selected and cannot be changed. Multiplexed with SUSPWRDNACK, SUSWARN# Desktop: Can be configured as SUSWARN# or GPIO30 only. Cannot be used as SUSPWRDNACK. Mobile: Used as SUSPWRDNACK, SUSWARN#, or GPIO30 Multiplexed with SLP_LAN# Pin usage as GPIO is determined by SLP_LAN#/GPIO Select Soft-strap9. Soft-strap value is not preserved for this signal in the Sx/Moff state and the pin will return to its native functionality (SLP_LAN#) Unmultiplexed Unmultiplexed. Can be configured as wake input to allow wakes from Deep S4/S5. This GPIO has no GPIO functionality in the Deep S4/S5 states other than wake from Deep S4/S5 if this option has been configured. Mobile: Multiplexed with PCIECLKRQ4#
GPIO31
I/O
3.3 V
DSW12
GPI
Yes
Yes
No
GPIO30
I/O
3.3 V
Suspend
Native
Yes
Yes
No
GPIO29
I/O
3.3 V
Suspend
Native
Yes
Yes
No
GPIO288
I/O
3.3 V
Suspend
GPO
Yes
No
No
GPIO27
I/O
3.3 V
DSW12
GPI
Yes
No
No
GPIO26 (Mobile Only)
I/O
3.3 V
Suspend
Native
Yes
No
No
35

Tolerance Power Well Blink Capability Glitch Protection during Power-On Sequence No GPI Event Support
Name
Type
Default
Description
GPIO25 (Mobile Only)
I/O
3.3 V
Suspend
Native
Yes
No
Mobile: Multiplexed with PCIECLKRQ3# Desktop: Can be used as PROC_MISSING configured using Intel ME firmware.
GPIO24
I/O
3.3 V
Suspend
GPO
Yes
Yes
No
Mobile: Unmultiplexed NOTE: GPIO24 configuration register bits are cleared by RSMRST# and not cleared by CF9h reset event. Multiplexed with LDRQ1#. Multiplexed with SCLOCK Multiplexed with SATA0GP Multiplexed with PCIECLKRQ2#, SMI# Multiplexed with SATA1GP Mobile: Multiplexed with PCIECLKRQ1# Desktop: Multiplexed with TACH0. Mobile: Used as GPIO17 only. Multiplexed with SATA4GP Unmultiplexed Multiplexed with OC7# Multiplexed with HDA_DOCK_RST# (Mobile Only)4. Desktop: Used as GPIO only Multiplexed with LAN_PHY_PWR_CTRL. GPIO / Functionality controlled using soft strap7,13 Multiplexed with SMBALERT#10. Multiplexed with OC6#10. Multiplexed with OC5#10. Unmultiplexed Multiplexed with TACH[3:2]. Mobile: Used as GPIO[7:6] only. Multiplexed PIRQ[H:E]#5.
GPIO23 GPIO22 GPIO21 GPIO20 GPIO198 GPIO18 (Mobile Only) GPIO17 GPIO16 GPIO158 GPIO14
I/O I/O I/O I/O I/O I/O
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Core Core Core Core Core Core
Native GPI GPI Native GPI Native
Yes Yes Yes Yes Yes Yes6
No No No No No No
No No No No No No
I/O I/O I/O I/O
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V or 1.5 V11
Core Core Suspend Suspend HDA Suspend
GPI GPI GPO Native
Yes Yes Yes Yes
No No No No
No No Yes2 Yes
2
GPIO13
I/O
GPI
Yes
No
Yes2
GPIO12
I/O
3.3 V
Suspend
Native
Yes
No
Yes
GPIO11 GPIO10 GPIO9 GPIO8 GPIO[7:6] GPIO[5:2]
I/O I/O I/O I/O I/O I/OD
3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5V
Suspend Suspend Suspend Suspend Core Core
Native Native Native GPO GPI GPI
Yes Yes Yes Yes Yes Yes
No No No No No No
Yes2 Yes2 Yes2 Yes

2
Yes2 Yes2
36

Tolerance Power Well Blink Capability Glitch Protection during Power-On Sequence No No GPI Event Support
Name
Type
Default
Description
GPIO1 GPIO0
I/O I/O
3.3 V 3.3 V
Core Core
GPI GPI
Yes Yes
Yes2 Yes2
Multiplexed with TACH1. Mobile: Used as GPIO1 only. Multiplexed with BMBUSY#
NOTES: 1. All GPIOs can be configured as either input or output. 2. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an SMI# or an SCI, but not both. 3. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals are not driven high into powered-down planes. Also, external devices should not be driving powered down GPIOs high. Some GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override event will result in the PCH driving a pin to a logic 1 to another device that is powered down. 4. The functionality that is multiplexed with the GPIO may not be used in desktop configuration. 5. When this signal is configured as GPO the output stage is an open drain. 6. GPIO18 will toggle at a frequency of approximately 1 Hz when the signal is programmed as a GPIO (when configured as an output) by BIOS. 7. For GPIOs where GPIO vs. Native Mode is configured using SPI Soft Strap, the corresponding GPIO_USE_SEL bits for these GPIOs have no effect. The GPIO_USE_SEL bits for these GPIOs may change to reflect the Soft-Strap configuration even though GPIO Lockdown Enable (GLE) bit is set. 8. These pins are used as Functional straps. See Section 2.27 for more details. 9. Once Soft-strap is set to GPIO mode, this pin will default to GP Input. When Soft-strap is SLP_LAN# usage and if Host BIOS does not configure as GP Output for SLP_LAN# control, SLP_LAN# behavior will be based on the setting of the RTC backed SLP_LAN# Default Bit (D31:F0:A4h:Bit 8). 10. When the multiplexed GPIO is used as GPIO functionality, care should be taken to ensure the signal is stable in its inactive state of the native functionality, immediately after reset until it is initialized to GPIO functionality. 11. GPIO13 is powered by VccSusHDA (either 3.3 V or 1.5 V). Voltage tolerance on the signal is the same as VccSusHDA. 12. GPIO functionality is only available when the Suspend well is powered although pin is in DSW. 13. GPIO will assume its native functionality until the soft strap is loaded after which time the functionality will be determined by the soft strap setting.
b. Section 13.8.3.6 GPE0_ENGeneral Purpose Event 0 Enables Register bit 35 is changed as shown:
Bit GPIO27_EN R/W. 0 = Disable. 1 = Enable the setting of the GPIO27_STS bit to generate a wake event/SCI/SMI#. 35 GPIO27 is a valid host wake event from Deep S4/S5. The wake enable configuration persists after a G3 state. NOTE: In the Deep S4/S5 state, GPIO27 has no GPIO functionality other than wake enable capability, which is enabled when this bit is set. Description
37
17.
Power Button Override and Deep S4/S5

a. The following note is added to the PWRBTN# Description in table 2-8 Power Management Interface Signals: Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5. b. The following is added as note 5 to table 5-23 State Transition Rules for the PCH and applies to all Power Button Override statements in the table: Note: Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5. c. Table 5-32 Transitions Due to Power Button is modified as shown:
Present State Event Transition/Action Unconditional transition to S5 state and if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will then transition to Deep S4/S5. Comment
S0S4
PWRBTN# held low for at least 4 consecutive seconds
No dependence on processor (DMI Messages) or any other subsystem
d. The Power Button Override Function sub-section of section 5.13.8.1 PWRBTN# (Power Button) is replaced with the following: If PWRBTN# is observed active for at least four consecutive seconds, the state machine unconditionally transitions to the G2/S5 state or Deep S4/S5, regardless of present state (S0S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5 state or Deep S4/S5 does not depend on any particular response from the processor (such as, a DMI Messages), nor any similar dependency from any other subsystem. The PWRBTN# status is readable to check if the button is currently being pressed or has been released. The status is taken after the de-bounce, and is readable using the PWRBTN_LVL bit. Note: The 4-second PWRBTN# assertion should only be used if a system lock-up has occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the PWRBTN# signal is asserted and held active when the system is in a suspend state (S1S5), the assertion causes a wake event. Once the system has resumed to the S0 state, the 4-second timer starts. During the time that the SLP_S4# signal is stretched for the minimum assertion width (if enabled by D31:F0:A4h Bit 3), the Power Button is not a wake event. As a result, it is conceivable that the user will press and continue to hold the Power Button waiting for the system to awake. Since a 4-second press of the Power Button is already defined as an Unconditional Power down, the power button timer will be forced to inactive while the power-cycle timer is in progress. Once the power-cycle timer has expired, the Power Button awakes the system. Once the minimum SLP_S4# power cycle expires, the Power Button must be pressed for another 4 to 5 seconds to create the Override condition.
Note:
38
e. Note 6 is added to the Straight to S5 (Host Stays there) column in Table 5-38 Causes of Host and Global Resets: 6. Upon entry to S5, if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5. f. Bits 11 and 8 of section 13.8.3.1 PM1_STSPower Management 1 Status Register are modified as shown.
Bit Description Power Button Override Status (PWRBTNOR_STS) R/WC. 0 = Software clears this bit by writing a 1 to it. 1 = This bit is set any time a Power Button Override occurs (that is, the power button is pressed for at least 4 consecutive seconds), due to the corresponding bit in the SMBus slave message, Intel ME Initiated Power Button Override, Intel ME Initiated Host Reset with Power down or due to an internal thermal sensor catastrophic condition. The power button override causes an unconditional transition to the S5 state. The BIOS or SCI handler clears this bit by writing a 1 to it. This bit is not affected by hard resets using CF9h writes, and is not reset by RSMRST#. Thus, this bit is preserved through power failures. Note that if this bit is still asserted when the global SCI_EN is set then an SCI will be generated. NOTE: Upon entry to S5 due to an event described above, if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5. Power Button Status (PWRBTN__STS) R/WC. This bit is not affected by hard resets caused by a CF9 write but is reset by DPWROK. 0 = If the PWRBTN# signal is held low for more than 4 seconds, the hardware clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, and the system transitions to the S5 state with only PWRBTN# enabled as a wake event. This bit can be cleared by software by writing a one to the bit position. 1 = This bit is set by hardware when the PWRBTN# signal is asserted Low, independent of any other enable bit. In the S0 state, while PWRBTN_EN and PWRBTN_STS are both set, an SCI (or SMI# if SCI_EN is not set) will be generated. In any sleeping state S1S5, while PWRBTN_EN (PMBASE + 02h, bit 8) and PWRBTN_STS are both set, a wake event is generated. NOTES: 1. If the PWRBTN_STS bit is cleared by software while the PWRBTN# signal is sell asserted, this will not cause the PWRBN_STS bit to be set. The PWRBTN# signal must go inactive and active again to set the PWRBTN_STS bit. 2. Upon entry to S5 due to a power button override, if Deep S4/S5 is enabled and conditions are met per section 5.13.7.6, the system will transition to Deep S4/S5.
11
18.
Power Management Clarifications

a. Clarify t200 timing by adding the following note to table 8-37: Note: Measured from VccRTC-10% to RTCRST# reaching 55%*VccRTC. VccRTC is defined as the final settling voltage that the rail ramps. b. Delete t226 (in table 8-37, figure 8-1, and figure 8-2) as it is replaced by t200a. c. t200a min timing is changed from 0 ms to 1 us.
39
d. Table 2-13 is modified as shown:

Name Type Description RTC Reset: When asserted, this signal resets register bits in the RTC well. NOTES: 1. Unless CMOS is being cleared (only to be done in the G3 power state), the RTCRST# input must always be high when all other RTC power planes are on. 2. In the case where the RTC battery is dead or missing on the platform, the RTCRST# pin must rise before the DPWROK pin.
RTCRST#
19.
t203 Deep S3/S4 Exit Clarification

The following note is added to t203 in table 8-37: Timing does not apply after Deep S3/S4 exit when Intel ME has configured SLP_S5# and/or SLP_S4# to rise with SLP_A#.
20.
RAID 1 Description
The second bullet of section 5.16.7 Intel Rapid Storage Technology Configuration is changed to: Data redundancy is offered through RAID Level 1, which performs mirroring.
21.
V_PROC_IO Definition
Table 2-26 Power and Ground Signals is modified as shown:
Name Description Power supply for DMI. For 3rd generation Intel Core processors-based platforms, this supply can be connected to the PCH VccIO. For 2nd generation Intel Core processors-based platforms, this supply must be connected to the same supply as the processor I/O voltage. This supply is used to drive the processor interface signals. For 3rd generation Intel Core processors-based platforms, this supply can be connected to the PCH VccIO. For 2nd generation Intel Core processors-based platforms, this supply must be connected to the same supply as the processor I/O voltage.
VccDMI
V_PROC_IO
22.
Manageability Signals Clarifications

The following replaces section 2.25:
2.25 Manageability Signals

The following signals can be optionally used by Intel Management Engine supported applications and appropriately configured by Intel Management Engine firmware. When configured and used as a manageability function, the associated host GPIO functionality is no longer available. If the manageability function is not used in a platform, the signal can be used as a host General Purpose I/O or a native function.
40
Table 2-25 Desktop/Mobile Manageability Signals

Functionality Name Functionality Description Pin Name(s)1 SUSWARN# /SUSPWRDNACK#/ GPIO30 ACPRESENT / GPIO31
SUSWARN# or Used by Intel ME as either SUSWARN# in Deep S4/S5 SUSPWRDNACK state supported platforms or as SUSPWRDNACK in non (Mobile Only) Deep S4/S5 state supported platforms. AC Present (Mobile Only) Input signal from the Embedded Controller (EC) on Mobile systems to indicate AC power source or the system battery. Active High indicates AC power. Used as an alert (active low) to indicate to the external controller (such as EC or SIO) that temperatures are out of range for the PCH or Graphics/Memory Controller or the processor core. Used to indicate Processor Missing to the Intel Management Engine.
Temperature Alert Processor Missing (Desktop Only)
SATA5GP / GPIO49 / TEMP_ALERT#
GPIO24 / PROC_MISSING
NOTES: 1. Manageability functionality can be assigned to at most one pin and is configured through Intel ME FW. 2. See GPIO table for power well each Pin Name is associated with in Section 2-24.
Table 2-26 Server Manageability Signals

Functionality Name SMBALERT# signal from PSU to PCH Intel ME FW Recovery Mode Strap Functionality Description Indicates the PSU may cause system shutdown due to a momentary loss of AC input voltage or an over temperature condition. MGPIO Name(s)1
MGPIO2 MGPIO0, MGPIO1, MGPIO2, MGPIO3, MGPIO4, MGPIO5, MGPIO6, MGPIO7, or MGPIO8
Input to PCH to force Intel ME to stay in recovery boot loader.
NOTES: 1. Manageability functionality can be assigned to at most one pin and is configured through Intel ME FW. 2. See GPIO table for power well each Pin Name is associated with in Section 2-24.
Table 2-27 Server MGPIO Signal to Pin Name Conversion Table (Sheet 1 of 2)
MGPIO MGPIO0 MGPIO1 MGPIO2 MGPIO3 MGPIO4 MGPIO5 GPIO24/PROC_MISSING SUSWARN#/GPIO30 GPIO31 SLP_LAN#/GPIO29 SML0ALERT#/GPIO60 GPIO57 Ballout Pin Name
41
Table 2-27 Server MGPIO Signal to Pin Name Conversion Table (Sheet 2 of 2)
MGPIO MGPIO6 MGPIO7 MGPIO8 GPIO27 GPIO28 SML1ALERT#/PCHHOT#/GPIO74 Ballout Pin Name
23.
ACPRESENT Definition
Table 2-8 Power Management Interface Signals is modified as shown:
Name Type Description ACPRESENT: This input pin indicates when the platform is plugged into AC power or not. In addition to the previous Intel ME to EC communication, the PCH uses this information to implement the Deep S4/S5 policies. For example, the platform may be configured to enter Deep S4/S5 when in S4 or S5 and only when running on battery. This is powered by Deep S4/S5 Well. Mobile: This GPIO pin is permanently appropriated by the Intel ME for ACPRESENT function. Desktop: This pin is only GPIO31, ACPRESENT is not supported. NOTE: This signal is muxed with GPIO31 but GPIO_USE_SEL[31] is internally hardwired to a 1b, which means GPIO mode is permanently selected and cannot be changed.
ACPRESENT (Mobile Only) / GPIO31
24.
SPI Overview
The Serial Peripheral Interface (SPI) subsection of section 1.2.1 Capability Overview is replaced as follows: The PCH provides an SPI Interface and is required to be used on the platform in order to provide chipset configuration settings and Intel ME firmware. If integrated Gigabit Ethernet MAC/PHY is implemented on the platform, the interface is used for this device configuration settings. The interface may also be used as the interface for the BIOS flash device or alternatively a FWH on LPC may be used. The PCH supports up to two SPI flash devices using two chip select pins with speeds up to 50 MHz.
42
Documentation Changes
1. Addition of LPC Capability List Pointer Register
The following is added immediately after 13.1.11: CAPP Capability List Pointer Register (LPC I/FD31:F0) Offset Address: 34h Attribute: RO Default Value: E0h Size: 8 bits
Bit 7:0 Item. Description Capability Pointer (CP) RO. Indicates the offset of the first Capability
2.
Intel Smart Response Technology Functional Description Updates

The following replaces section 5.16.8: Part of the Intel RST storage class driver feature set, Intel Smart Response Technology implements storage I/O caching to provide users with faster response times for things like system boot and application startup. On a traditional system, performance of these operations is limited by the hard drive, particularly when there may be other I/O intensive background activities running simultaneously, like system updates or virus scans. Intel Smart Response Technology accelerates the system response experience by putting frequently-used blocks of disk data on an SSD, providing dramatically faster access to user data than the hard disk alone can provide. The user sees the full capacity of the hard drive with the traditional single drive letter with overall system responsiveness similar to what an SSD-only system provides. See Section 1.3 for SKUs enabled for Intel Smart Response Technology.
3.
Addition of Legacy ATA Backwards Compatibility Registers

a. Section 14.1.22 IDE_TIM IDE Timing Register is modified as shown:
Bit Description
IDE Decode Enable (IDE) R/W. Individually enable/disable the Primary or Secondary decode. 15 0 = Disable. 1 = Enables the PCH to decode the associated Command Block (1F01F7h for primary, 170177h for secondary, or their native mode BAR equivalents) and Control Block (3F6h for primary, 376h for secondary, or their native mode BAR equivalents). This bit effects the IDE decode ranges for both legacy and native-mode decoding.
43
Bit
Description
14:12 11:10 9:0
IDE_TIM Field 2 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_TIM Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
b. The following paragraph is added to the register summary of section 14.1.22 IDE_TIM IDE Timing Register: Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These bits have no effect on hardware. c. The following registers are added immediately following section 14.1.22: SIDETIMSlave IDE Timing Register (SATAD31:F2) Address Offset: 44h Attribute: Default Value: 00h Size: Note: R/W 8 bits
This register is R/W to maintain software compatibility. These bits have no effect on hardware.
Bit Description
7:0
SIDETIM Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
SDMA_CNTSynchronous DMA Control Register (SATAD31:F2) Address Offset: 48h Attribute: Default Value: 00h Size: Note:
R/W 8 bits
Bit Description
7:4 3:0
Reserved SDMA_CNT Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
SDMA_TIMSynchronous DMA Timing Register (SATAD31:F2) Address Offset: 4Ah4Bh Attribute: Default Value: 0000h Size: Note:
R/W 16 bits
Bit Description
15:14 13:12 11:10
Reserved SDMA_TIM Field 4 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved
44
Bit
Description
9:8 7:6 5:4 3:2 1:0
SDMA_TIM Field 3 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved SDMA_TIM Field 2 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved SDMA_TIM Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
IDE_CONFIGIDE I/O Configuration Register (SATAD31:F2) Address Offset: 54h57h Attribute: Default Value: 00000000h Size: Note:
R/W 32 bits
Bit Description
31:24 23:12 11:8 7:0
Reserved IDE_CONFIG Field 2 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_CONFIG Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
d. Section 15.1.21 IDE_TIM IDE Timing Register is modified as shown:

Bit Description IDE Decode Enable (IDE) R/W. Individually enable/disable the Primary or Secondary decode. 0 = Disable. 1 = Enables the PCH to decode the associated Command Block and Control Block. IDE_TIM Field 2 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_TIM Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
15
14:12 11:10 9:0
e. The following paragraph is added to the register summary of section 15.1.21 IDE_TIM IDE Timing Register: Bits 14:12 and 9:0 of this register are R/W to maintain software compatibility. These bits have no effect on hardware. f. The following registers are added immediately following section 15.1.21:
45
SDMA_CNTSynchronous DMA Control Register (SATAD31:F5) Address Offset: 48h Attribute: Default Value: 00h Size: Note:
R/W 8 bits
Bit Description
7:4 3:0
Reserved SDMA_CNT Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
SDMA_TIMSynchronous DMA Timing Register (SATAD31:F5) Address Offset: 4Ah4Bh Attribute: Default Value: 0000h Size: Note:
R/W 16 bits
Bit Description
15:10 9:8 7:2 1:0
Reserved SDMA_TIM Field 2 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved SDMA_TIM Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
IDE_CONFIGIDE I/O Configuration Register (SATAD31:F5) Address Offset: 54h57h Attribute: Default Value: 00000000h Size: Note:
R/W 32 bits
Bit Description
31:24 23:16 15 14 13 12 11:8 7:4 3
Reserved IDE_CONFIG Field 6 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_CONFIG Field 5 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_CONFIG Field 4 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_CONFIG Field 3 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved
46
Bit
Description
2 1 0
IDE_CONFIG Field 2 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware. Reserved IDE_CONFIG Field 1 R/W. This field is R/W to maintain software compatibility. This field has no effect on hardware.
4.
DMI L1 Exit Latency Documentation Change

Section 10.1.14 LCAPLink Capabilities Register bits 17:15 are changed as shown:
Bit L1 Exit Latency (EL1) R/WO. 000b Less than 1 s 001b 1 s to less than 2 s 010b 2 s to less than 4 s 17:15 011b 4 s to less than 8 s 100b 8 s to less than 16 s 101b 16 s to less than 32 s 110b 32 s to 64 s 111b More than 64 s Description
5.
Device 30 Function 0 Naming Consistency Change

Device 30 Function 0 is named PCI-to-PCI Bridge throughout document for consistency.
6.
Gigabit Ethernet Capabilities and Status Registers Additions

a. The follow is added as section 12.2 12.2 Gigabit LAN Capabilities and Status Registers (CSR) The internal CSR registers and memories are accessed as direct memory mapped offsets from the base address register in Section 12.1.10. Software may only access whole DWord at a time.
Note:
Register address locations that are not shown in Table 12-2 should be treated as Reserved.
Table 12-2. Gigabit LAN Capabilities and Status Registers Address Map (Gigabit LAN MBARA) (Sheet 1 of 2)
MBARA + Offset 00h-03h 18h-1Bh 20h-23h 2Ch-2Fh Mnemonic GBECSR1 GBECSR2 GBECSR3 GBECSR4 Register Name Gigabit Ethernet Capabilities and Status Register 1 Gigabit Ethernet Capabilities and Status Register 2 Gigabit Ethernet Capabilities and Status Register 3 Gigabit Ethernet Capabilities and Status Register 4 Default 00100241h 01501000h 1000XXXXh 00000000h Attribute R/W R/W/SN R/W R/W
47
Table 12-2. Gigabit LAN Capabilities and Status Registers Address Map (Gigabit LAN MBARA) (Sheet 2 of 2)
MBARA + Offset F00h-F03 h F10h-F13 h 5400h-54 03h 5404h-54 07h 5800h-58 03h Mnemonic GBECSR5 GBECSR6 GBECSR7 GBECSR8 GBECSR9 Register Name Gigabit Ethernet Capabilities and Status Register 5 Gigabit Ethernet Capabilities and Status Register 6 Gigabit Ethernet Capabilities and Status Register 7 Gigabit Ethernet Capabilities and Status Register 8 Gigabit Ethernet Capabilities and Status Register 9 Default 00010008h 0004000Ch XXXXXXXXh XXXXXXXXh 00000008h Attribute R/W R/W/SN R/W R/W R/W/SN
12.2.1 GBECSR1Gigabit Ethernet Capabilities and Status Register 1 Address Offset: MBARA + 00h Attribute: R/W Default Value: 00100241h Size: 32 bit
Bit 31:25 24 23:0 Reserved PHY Power Down (PHYPDN) R/W. When cleared (0b), the PHY power down setting is controlled by the internal logic of PCH. Reserved Description
12.2.2 GBECSR2Gigabit Ethernet Capabilities and Status Register 2 Address Offset: MBARA + 18h Attribute: R/W/SN Default Value: 01501000h Size: 32 bit
Bit 31:21 20 19:0 Reserved PHY Power Down Enable (PHYPDEN) R/W/SN. When set, this bit enables the PHY to enter a low-power state when the LAN controller is at the DMoff/D3 or with no WOL. Reserved Description
48
12.2.3 GBECSR3Gigabit Ethernet Capabilities and Status Register 3 Address Offset: MBARA + 20h Attribute: R/W Default Value: 1000XXXXh Size: 32 bit
Bit 31:29 28 Reserved Ready Bit (RB) R/W. Set to 1 by the Gigabit Ethernet Controller at the end of the MDI transaction. This bit should be reset to 0 by software at the same time the command is written. MDI Type R/W. 01 = MDI Write 10 = MDI Read All other values are reserved. LAN Connected Device Address (PHYADD) R/W. LAN Connected Device Register Address (PHYREGADD) R/W. DATA R/W. Description
27:26
25:21 20:16 15:0
12.2.4 GBECSR4Gigabit Ethernet Capabilities and Status Register 4 Address Offset: MBARA + 2Ch Attribute: R/W Default Value: 00000000h Size: 32 bits
Bit 31 Description WOL Indication Valid (WIV) R/W. Set to 1 by BIOS to indicate that the WOL indication setting in bit 30 of this register is valid. WOL Enable Setting by BIOS (WESB) R/W. 1 = WOL Enabled in BIOS. 0 = WOL Disabled in BIOS. Reserved
30 29:0
12.2.5 GBECSR5Gigabit Ethernet Capabilities and Status Register 5 Address Offset: MBARA + F00h Attribute: R/W Default Value: 00010008h Size: 32 bits
Bit 31:6 5 4:0 Reserved SW Semaphore FLAG (SWFLAG) R/W. This bit is set by the device driver to gain access permission to shared CSR registers with the firmware and hardware. Reserved Description
49
12.2.6 GBECSR6Gigabit Ethernet Capabilities and Status Register 6 Address Offset: MBARA + F10h Attribute: R/W/SN Default Value: 0004000Ch Size: 32 bits
Bit 31:7 6 5:4 3 Reserved Global GbE Disable (GGD) R/W/SN. Prevents the PHY from auto negotiating 1000Mb/s link in all power states. Reserved GbE Disable at non D0a R/W/SN. Prevents the PHY from auto negotiating 1000Mb/s link in all power states except D0a. This bit must be set since GbE is not supported in Sx states. LPLU in non D0a (LPLUND) R/W/SN. Enables the PHY to negotiate for the slowest possible link in all power states except D0a. LPLU in D0a (LPLUD) R/W/SN. Enables the PHY to negotiate for the slowest possible link in all power states. This bit overrides bit 2. Reserved Description
1 0
12.2.7 GBECSR7Gigabit Ethernet Capabilities and Status Register 7 Address Offset: MBARA + 5400h Attribute: R/W Default Value: XXXXXXXXh Size: 32 bits
Bit 31:0 Description Receive Address Low (RAL) R/W. The lower 32 bits of the 48 bit Ethernet Address.
12.2.8 GBECSR8Gigabit Ethernet Capabilities and Status Register 8 Address Offset: MBARA + 5404h Attribute: R/W Default Value: XXXXXXXXh Size: 32 bits
Bit 31 30:16 15:0 Address Valid R/W. Reserved Receive Address High (RAH) R/W. The lower 16 bits of the 48 bit Ethernet Address. Description
12.2.9 GBECSR9Gigabit Ethernet Capabilities and Status Register 9 Address Offset: MBARA + 5800h Attribute: R/W/SN Default Value: 00000008h Size: 32 bits
Bit 31:1 0 Reserved Advanced Power Management Enable (APME) R/W/SN. 1 = APM Wakeup is enabled 0 = APM Wakeup is disabled Description
50
b. Bit and register attributes of the type R/W/SN are defined as follows. This is added to the beginning of chapter 9: R/W/SN Read/Write register initial value loaded from NVM
7.
Measured ICC Corrections

The following updates are made in table 8-5:
Voltage (V) S0 Iccmax Current Integrated Graphics5 (A) S0 Iccmax Current External Graphics5 (A) S0 Idle Current Integrated Graphics4,5 (A) S0 Idle Current External Graphics5 (A) Sx Iccmax Current5 (A) Sx Idle Current (A)
Voltage Rail
G3
VccADPLLA VccDSW3_3
1.05 3.3
0.08 0.001
0.02 0.001
0.073 0.001
0.01 0.001
0 0.002
0 0.001
8.
Miscellaneous Documentation Corrections

a. Sections 23.1.1.17 PIDPCI Power Management Capability ID Register and 23.2.1.16 PIDPCI Power Management Capability ID Register default is changed to 8C01h and the register is modified as shown:
Bit 15:8 Description Next Capability (NEXT) RO. Value of 8Ch indicates the location of the next pointer.
b. Sections 23.1.1.8 and 23.2.1.8 naming is updated to be consistent with section 23.1.2 and 23.2.2 respectively.
Section Mnemonic MEI0_MBAR MEI1_MBAR Register Name Intel MEI 1 MMIO Base Address Intel MEI 2 MMIO Base Address
23.1.1.8 23.2.1.8
c. In table 8-5 Measured ICC (Desktop Only) VccDMI voltage is changed from 1.05 V to 1.05 V / 1.0 V. d. In table 4-2 CLKOUTFLEX2 is changed to reflect that it is muxed with GPIO66. e. Section 10.1.20 D31IPDevice 31 Interrupt Pin Register (RCBA+3100) bits 27:24 are changed as shown:
Bit Description Thermal Sensor Pin (TSIP) R/W. Indicates which pin the Thermal Sensor controller drives as its interrupt 27:24 0h = No interrupt 1h = INTA# 2h = INTB# (Default) 3h = INTC# 4h = INTD# 5hFh = Reserved
f. Section 17.1.2.41 is renamed to ISDFIFOSInput Stream Descriptor FIFO Size Register and section 17.1.2.42 is renamed to OSDFIFOSOutput Stream Descriptor FIFO Size Register.
51
g. 82C37 is changed to 8237 throughout document. h. 82C54 is changed to 8254 throughout document. i. 82C59 is changed to 8259 throughout document. j. The second paragraph of section 5.10 is changed as shown: The PCH supports a message for 21 serial interrupts. These represent the 15 ISA interrupts (IRQ01, 315), the four PCI interrupts, and the control signals SMI# and IOCHK#. The serial IRQ protocol does not support the additional APIC interrupts (2023). k. Section 5.13.11 Clock Generators is removed. l. Section 5.8.4.6 Cascade Mode is removed. m. THERM_ALERT# is changed to TEMP_ALERT# throughout document. n. Section 10.1.36 PRSTSPower and Reset Status Register (RCBA+3310h) bit 4 is changed as shown:
Bit 4 Description PRSTS Field 1 R/WC. BIOS may write to this bit field.
o. The following table lists changes to terms (bit names) made throughout the document to ensure consistent naming throughout the document.
Old Term
CPUSCI_STS CPUSMI_STS USB2_STS USB2_EN SWGPE SPI_SMI_STS SMI_ON_SLP_EN_STS SMI_ON_SLP_EN OS_TCO_SMI
New (Correct) Term

DMISCI_STS DMISMI_STS INTEL_USB2_STS INTEL_USB2_EN SWGPE_EN SPI_STS SLP_SMI_STS SLP_SMI_EN SW_TCO_SMI
p. The following sentence is removed from section 5.16.7: By using the PCHs built-in Intel Rapid Storage Technology, there is no loss of PCI resources (request/grant pair) or add-in card slot. q. Section 14.4.2.5 PxISPort [5:0] Interrupt Status Register (ABAR+110h, 190h, 210h, 290h, 310h, 390h) bit 23 is changed as shown:
Bit 23 Description Incorrect Port Multiplier Status (IPMS) R/WC. The PCH SATA controller does not support Port Multipliers.
r. Section 14.4.2.6 PxIEPort [5:0] Interrupt Enable Register (ABAR+114h, 194h, 214h, 294h, 314h, 394h) bit 23 is changed as shown:
52
Bit 23
Description Incorrect Port Multiplier Enable (IPME) R/W. The PCH SATA controller does not support Port Multipliers. BIOS and storage software should keep this bit cleared to 0.
s. The first sentence of section 2.20 is changed to All signals are Mobile Only, except as noted that are also available in Desktop. t. Table 8-17 title is changed from HDMI Interface Timings (DDP[D:B][3:0])Timings to HDMI Interface Timings (DDP[D:B][3:0]). u. Table 3-3 is updated to show that the PMSYNCH signal is Defined in Cx States. v. Table 3-2 SML0ALERT# / GPIO60 note in Immediately after Reset is changed from 11 to 12. w. Tables 3-2 and 3-3 note 7 removed from GPIO8 and GPIO27. x. In section 13.8.3.5 GPE0_STSGeneral Purpose Event 0 Status Register, the SMBus Wake Status (SMB_WAK_STS) bit description is updated remove SCI to reflect that the SMBus controller can only generate an SMI#. y. References to the Coprocessor Error Enable bit (RCBA+31FEh bit 9) mnemonic COPROC_ERR_EN are changed to CEN to represent the actual mnemonic.
9.
25 MHz Flex Clock AC Timings

a. The following rows are added to table 8-24 Clock Timings:
Sym Parameter Min 25 MHz Flex Clock t51 t52 t53 Period High Time Low Time Duty Cycle Rising Edge Rate Falling Edge Rate Jitter (25 MHz configured on CLKOUTFLEX2) 39.84 16.77 16.37 45 1.0 1.0 40.18 21.78 21.58 55 4 4 ns ns ns % V/ns V/ns ps 5 5 16 8-11 8-11 8-11 Max Unit Notes Figure
b. The following note is added to table 8-24: 16. The 25 MHz output option for CLKOUTFLEX2 is derived from the 25 MHz crystal input to the PCH. The PPM of the 25 MHz output is equivalent to that of the crystal.
10.
Fan Speed Control Signals Functional Description Introduction

The following is added immediately before section 5.24.9: 5.25 Fan Speed Control Signals (Server/Workstation Only) The PCH implements 4 PWM and 8 TACH signals for integrated fan speed control. Note: Integrated fan speed control functionality requires a correctly configured system, including an appropriate processor, Server/Workstation PCH with Intel ME, Intel ME Firmware, and system BIOS support.
53
11.
SMBus/SMLink Timing Naming Corrections

a. The following table lists changes to SMBus/SMLink timings symbols.
Old Symbol t22 t23 t24 t25 t22_SML t23_SML t24_SML t25_SML New (Correct) Symbol t18 t19 t20 t21 t18_SML t19_SML t20_SML t21_SML
b. Figure 8-20 name is changed from SMBus Transaction to SMBus/SMLink Transaction and Figure 8-21 name is changed from SMBus Timeout to SMBus/SMLink Timeout. c. The following note is added to Figure 8-20: txx also refers to txx_SML, txxx also refers to txxxSMLFM, SMBCLK also refers to SML[1:0]CLK, and SMBDATA also refers to SML[1:0]DATA in Figure 8-20. d. The following note is added to Figure 8-21: Note: SMBCLK also refers to SML[1:0]CLK and SMBDATA also refers to SML[1:0]DATA in Figure 8-21.
12.
PCI Express* Lane Reversal Bit Change

The Lane Reversal bit is moved from section 19.1.50 MPCMiscellaneous Port Configuration Register to 19.1.63 PEETM PCI Express* Extended Test Mode Register and modified as shown:
Bit Description Lane Reversal (LR) RO. This register reads the setting of the PCIELR1 soft strap for port 1 and the PCIELR2 soft strap for port 5. 0 = No Lane reversal (default). 1 = PCI Express lanes 0-3 (register in port 1) or lanes 4-7 (register in port 5) are reversed. NOTES: 1. The port configuration straps must be set such that Port 1 or Port 5 is configured as a x4 port using lanes 03, or 47 when Lane Reversal is enabled. x2 lane reversal is not supported. 2. This register is only valid on port 1 (for ports 14) or port 5 (for ports 58).
54
13.
Auxiliary Trip Point Lock Bit Correction

Section 22.2.5 TSTTPThermal Sensor Temperature Trip Point Register bits 23:16 are changed as shown:
Bit Description Auxiliary Trip Point Setting (ATPS) R/W. These bits set the Auxiliary trip point. 23:16 These bits are lockable using programming the policy-lock down bit (bit 7) of TSPC register. These bits may only be programmed from 0h to 7Fh. Setting bit 23 is not supported.
14.
Top Swap Updates

a. Section 10.1.44 BUCBacked Up Control Register bit 0 is changed as shown:
Bit Top Swap (TS) R/W. 0 = PCH will not invert A16. 1 = PCH will invert A16, A17, or A18 for cycles going to the BIOS space. 0 If booting from LPC (FWH), then the boot-block size is 64 KB and A16 is inverted if Top Swap is enabled. If booting from SPI, then the BIOS Boot-Block size soft strap determines if A16, A17, or A18 should be inverted if Top Swap is enabled. If PCH is strapped for Top Swap (GNT3#/GPIO55 is low at rising edge of PWROK), then this bit cannot be cleared by software. The strap jumper should be removed and the system rebooted. Description
b. BOOT_BLOCK_SIZE soft strap name is changed to BIOS Boot-Block size soft strap. c. Table 2-27 is updated as shown:
Signal Usage When Sampled Comment The signal has a weak internal pull-up. If the signal is sampled low, this indicates that the system is strapped to the top-block swap mode. GNT3# / GPIO55 Top-Block Swap Override Rising edge of PWROK The status of this strap is readable using the Top Swap bit (Chipset Config Registers: Offset 3414h:Bit 0). NOTES: 1. The internal pull-up is disabled after PLTRST# deasserts. 2. Software will not be able to clear the Top Swap bit until the system is rebooted without GNT3#/GPIO55 being pulled down.
55
15.
Miscellaneous Documentation Corrections II

a. Section 13.10.15 GP_IO_SEL3GPIO Input/Output Select 3 Register is modified as shown:
Bit GP_IO_SEL3[75:64] R/W. 11:0 0 = GPIO signal is programmed as an output. 1 = Corresponding GPIO signal (if enabled in the GPIO_USE_SEL3 register) is programmed as an input. Description
b. Section 13.10.16 GP_LVL3GPIO Level for Input or Output 3 Register is modified as shown:
Bit GP_LVL[75:64] R/W. These registers are implemented as dual read/write with dedicated storage each. Write value will be stored in the write register, while read is coming from the read register which will always reflect the value of the pin. If GPIO[n] is programmed to be an output (using the corresponding bit in the GP_IO_SEL register), then the corresponding GP_LVL[n] write register value will drive a high or low value on the output pin. 1 = high, 0 = low. When configured in native mode (GPIO_USE_SEL[n] is 0), writes to these bits are stored but have no effect to the pin value. The value reported in this register is undefined when programmed as native mode. This register corresponds to GPIO[75:64]. Bit 0 corresponds to GPIO64 and bit 11 corresponds to GPIO75. Description
11:0
c. Note 5 is removed from SPI_MOSI in table 3-1. d. Default value of 19.1.38 LCTL2Link Control 2 Register (PCI Express*D28:F0/F1/F2/F3/F4/F5/F6/F7) is changed from 0001h to 0002h. e. Section 16.1.20 PWR_CNTL_STSPower Management Control/Status Register bits 1:0 are modified as shown
Bit Description Power State R/W. This 2-bit field is used both to determine the current power state of EHC function and to set a new power state. The definition of the field values are: 00 = D0 state 11 = D3HOT state 1:0 If software attempts to write a value of 10b or 01b in to this field, the write operation completes normally; however, the data is discarded and no state change occurs. When in the D3HOT state, the PCH does not accept accesses to the EHC memory range; but the configuration space is still accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically, the EHC interrupt is not asserted by the PCH when not in the D0 state. When software changes this value from the D3HOT state to the D0 state, an internal warm (soft) controller reset is generated, and software must re-initialize the function.
f. Section 10.1.35 OICOther Interrupt Control Register note is corrected as shown: FEC1_0000hFEC4_FFFFh is allocated to PCIe when I/OxAPIC Enable (PAE) bit is set. g. Table 9-4 PCIe memory ranges are corrected as shown:
56
Memory Range FEC1 8000hFEC1 FFFFh FEC2 8000hFEC2 FFFFh FEC3 8000hFEC3 FFFFh
Target PCI Express* Port 2 PCI Express* Port 4 PCI Express* Port 6
Dependency/Comments PCI Express* Root Port 2 I/OxAPIC Enable (PAE) set PCI Express* Root Port 4 I/OxAPIC Enable (PAE) set PCI Express* Root Port 6 I/OxAPIC Enable (PAE) set
h. SUSPWRDNACK is mobile only - this is more clearly indicated in table 2-8 and table 8-9. i. ACPRESENT is mobile only - this is more clearly indicated in table 2-8 and sections 5.13.7.6.1 and 5.13.7.6.2. j. HDA_DOCK_EN# and HDA_DOCK_RST# pin functionality are mobile only - this is more clearly indicated in table 2-14. k. Section 13.10.2GP_IO_SEL register default value is changed to EEFF66EFFh. l. Section 13.10.15GP_IO_SEL3 register default value is changed to 00000FF0h. m. Intel RST SSD Caching is changed to Intel Smart Response Technology and note 11 is removed from table 1-2. n. The register named GPIO_SEL3 (GPIOBASE +44h) is changed to GP_IO_SEL3.
16.
Ballout Documentation Changes

a. In table 6-1, the following changes are made: Remove BATLOW# from GPIO72 Remove HDA_DOCK_RST# from GPIO13 Remove HDA_DOCK_EN# from GPIO33 Remove CLKRUN# from GPIO32 Remove SUSPWRDNACK from SUSWARN# / GPIO30 (and add spaces)
17.
Integrated Digital Display Audio Device and Revision IDs

a. The title of section 17.2 is changed to Integrated Digital Display Audio Registers, Verb IDs, and Device/Revision IDs b. The following section is added at the conclusion of section 17.2.1: Integrated Digital Display Audio Device ID and Revision ID The Intel 6 Series Chipset/Intel C200 Series Chipset provides a Device ID of 2805h for the integrated digital display audio codec. This is not a PCI Device ID. Instead, it is a Device ID associated with the Intel HD Audio bus. The integrated digital display codec Revision ID is 00h for all PCH steppings.
57
18.
Miscellaneous Documentation Corrections III

a. In section 10.1.2 RPCRoot Port Configuration Register, the encoding for bits 10:8 is corrected as shown:
Bit Description GbE Over PCIe Root Port Select (GBEPCIERPSEL) R/W. If the GBEPCIERPEN is a 1, then this register determines which port is used for GbE MAC/PHY communication over PCI Express. This register is set by soft strap and is writable to support separate PHY on motherboard and docking station. 111 = Port 8 (Lane 7) 110 = Port 7 (Lane 6) 10:8 101 = Port 6 (Lane 5) 100 = Port 5 (Lane 4) 011 = Port 4 (Lane 3) 010 = Port 3 (Lane 2) 001 = Port 2 (Lane 1) 000 = Port 1 (Lane 0) The default value for this register is set by the GBE_PCIEPORTSEL[2:0] soft strap. Note: GbE and PCIe will use the output of this register and not the soft strap
b. Section 22.1.13 TBARHThermal Base High DWord bit description is changed from Thermal Base Address High (TBAH) R/W. TBAR bits 61:32. to Thermal Base Address High (TBAH) R/W. TBAR bits 63:32. c. Table 5-24 System Power Plane the plane labeled as Deep S4/S5 Well is changed to Suspend. d. t238 parameter is changed from DPWROK falling to any of VccDSW, VccSUS, VccASW, VccASW3_3, or Vcc falling to DPWROK falling to any of VccDSW, VccSUS, VccASW, or Vcc falling e. VccASW3_3 in Figure 8-31 is replaced with VccSPI.
19.
SPI Documentation Changes

a. Section 5.24.4.4.2 Serial Flash Discoverable Parameters (SFDP) is removed. b. Bits 7 and 6 of section 21.1.18 SSFSSoftware Sequencing Flash Status Register (SPI Memory Mapped Configuration Registers) are added as:
Bit 7 6 Description Fast Read Supported RO. This bit reflects the value of the Fast Read Support bit in the flash Descriptor Component Section. Dual Output Fast Read Supported RO. This bit reflects the value of the Dual Output Fast Read support bit in the Flash Descriptor Component Section
c. Section 21.1.23 BBARBIOS Base Address Configuration Register (SPI Memory Mapped Configuration Registers) is removed and the register is Reserved. d. Section 21.4.2 HSFSHardware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) bit 2 is modified as shown:
58
Bit
Description Access Error Log (AEL) R/WC. Hardware sets this bit to a 1 when an attempt was made to access the GbE region using the direct access method or an access to the GbE Program Registers that violated the security restrictions. This bit is simply a log of an access security violation. This bit is cleared by software writing a 1.
e. Section 21.4.4 FADDRFlash Address Register (GbE LAN Memory Mapped Configuration Registers) bits 24:0 are modified as shown:
Bit 24:0 Description Flash Linear Address (FLA) R/W. The FLA is the starting byte linear address of a SPI Read or Write cycle or an address within a Block for the Block Erase command. The Flash Linear Address must fall within a region for which GbE has access permissions.
f. Section 21.4.6 FRAPFlash Regions Access Permissions Register (GbE LAN Memory Mapped Configuration Registers) is modified as shown:
Bit Description GbE Master Write Access Grant (GMWAG) R/W. Each bit 31:24 corresponds to Master[7:0]. GbE can grant one or more masters write access to the GbE region 3 overriding the permissions in the Flash Descriptor. Master[1] is Host Processor/BIOS, Master[2] is Intel Management Engine, Master[3] is Host processor/GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit. GbE Master Read Access Grant (GMRAG) R/W. Each bit 23:16 corresponds to Master[7:0]. GbE can grant one or more masters read access to the GbE region 3 overriding the read permissions in the Flash Descriptor. Master[1] is Host processor/BIOS, Master[2] is Intel Management Engine, Master[3] is GbE. Master[0] and Master[7:4] are reserved. The contents of this register are locked by the FLOCKDN bit GbE Region Write Access (GRWA) RO. Each bit 15:8 corresponds to Regions 7:0. If the bit is set, this master can erase and write that particular region through register accesses. The contents of this register are that of the Flash Descriptor. Flash Master 3. Master Region Write Access OR a particular master has granted GbE write permissions in their Master Write Access Grant register OR the Flash Descriptor Security Override strap is set. GbE Region Read Access (GRRA) RO. Each bit 7:0 corresponds to Regions 7:0. If the bit is set, this master can read that particular region through register accesses. The contents of this register are that of the Flash Descriptor. Flash Master 3. Master Region Write Access OR a particular master has granted GbE read permissions in their Master Read Access Grant register.
31:24
23:16
15:8
7:0
g. Bits 7 and 6 of section 21.4.13 SSFSSoftware Sequencing Flash Status Register (GbE LAN Memory Mapped Configuration Registers) are added as:
Bit 7 6 Description Fast Read Supported RO. This bit reflects the value of the Fast Read Support bit in the flash Descriptor Component Section. Dual Output Fast Read Supported RO. This bit reflects the value of the Dual Output Fast Read support bit in the Flash Descriptor Component Section
59
20.
Miscellaneous Documentation Corrections IV

a. References to MPGIO9 are removed. b. The Opcodes for Enable Write to Status Register in table 5-58 Hardware Sequencing Commands and Opcode Requirements is change from 50h or 60h to 06h or 50h. c. 17.1.1.20 HDINIT1Intel High Definition Audio Initialization Register 1 register attribute changed to R/W. d. References to GEN_PMCON3 are changed to GEN_PMCON_3.
60
21.
Mobile SFF PCH Ballout

The following replaces section 6.3 Mobile SFF PCH Ballout:
Figure 6-9. Mobile SFF PCH Ballout (Top View - Upper Left)
51 BL BK BJ BH BG BF BE BD BC BB BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG
LVD_VR EFH LVDSB_ DATA#2 LVDSB_ DATA#3 LVD_VR EFL LVDSB_ DATA1 LVDSA_ DATA1 LVDSB_ DATA#0 LVDSB_ DATA#1 LVDSA_ CLK SDVO_S TALLN DDPC_A UXN SDVO_I NTN SDVO_S TALLP DDPB_A UXN DDPB_3 P DDPB_0 P DDPB_A UXP DDPC_0 P DDPC_3 P DDPC_1 P DDPC_0 N DDPB_2 P Vss_NCT F Vss_NCT F DDPD_0 N Vss_NCT F TP21 DDPD_2 N Vss_NCT F
50
49
48
47
46
45
DDPD_3 N
44
43
PERp8
42
41
PERp7
40
39
PERp5
38
37
PERp4
36
35
PERp2
34
33
PERp1
32
31
TP34
30
29
TP33
28
27
TP35
26
Vss_NCT Vss_NCT DDPD_2 F F P
Vss
DDPD_H PD DDPD_3 P
Vss
PERp6
Vss
PERp3
Vss
Vss
Vss
Vcc3_3
Vss
PERn8
PERn7
PERn5
PERn4
PERn2
PERn1
TP38
TP37
TP39
TP41
Vss
Vss
Vss
Vss
PERn6
Vss
PERn3
Vss
Vss
Vss
Vss
Vss
DDPD_0 P DDPC_2 DDPC_2 N P DDPC_H PD DDPC_1 N DDPD_1 N VccADPL LA
Vss
Vss
PETp6
PETp4
PETn3
TP29
TP30
TP32
DDPC_3 N
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
DDPD_1 P
VccADPL LB
PETn6
PETn4
PETp3
TP25
TP26
TP28
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
DDPB_2 N
TP42
PETp8
PETp7
PETp5
PETn2
PETn1
TP31
CLKIN_ GND1_N
DDPB_3 N DDPB_0 N DDPB_1 P
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
DDPB_1 N
DDPB_H PD
PETn8
PETn7
PETn5
PETp2
PETp1
TP27
CLKIN_ GND1_P
Vss
Vss
Vss
Vss
Vss
VccIO
VccAPLL DMI2
Vss
Vss
Vss
Vss SDVO_T VCLKIN N Vss Vss
DDPC_A UXP SDVO_I NTP
DDPD_A UXN
DDPD_A UXP
SDVO_T VCLKINP
Vss
VccIO
DcpSus
DcpSus
VccIO
VccIO
Vss
Vss
LVDSA_ DATA#0
LVDSA_ DATA0
TP9
TP8
Vss
Vss
DcpSus
Vss
VccIO
VccIO
Vss
Vss
Vss
Vss
Vss
VccClkD MI
Vss
Vss
Vss
Vss
Vss
VccIO
LVDSA_ DATA#1 LVDSB_ DATA0
LVDSA_ DATA2
LVDSA_ DATA#2
TP6
TP7
Vss
VccCore
VccCore
Vss
Vss
VccSus3 _3
Vss
Vss
Vss
Vss
Vss
Vss
LVDSA_ CLK#
LVDSA_ DATA3
LVDSA_ DATA#3
Vss
Vss
VccCore
VccCore
VccCore
Vss
LVDSB_ DATA2 LVDSB_ DATA3 LVDSB_ CLK#
Vss
Vss
Vss
Vss
VccTX_L VDS
Vss
Vss
VccCore
VccCore
VccCore
LVDSB_ CLK
LVD_IBG
LVD_VB G VccTX_L VDS VccTX_L VDS VccALVD S
Vss
Vss
Vss
Vss
Vss
Vss
VccCore
61
Figure 6-10. Mobile SFF PCH Ballout (Top View - Lower Left)
AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
Vss_NCT F Vss_NCT Vss_NCT PIRQE# F F / GPIO2 CLKIN_P CILOOP BACK Vss_NCT F Vss_NCT F CLKOUT _PCI0 CLKOUT FLEX3 / GPIO67 CLKOUT FLEX0 / GPIO64 CLKOUT FLEX2 / GPIO66 Vss Vss L_DDC_ CLK CRT_VS YNC CRT_HS YNC L_BKLTC TL L_DDC_ DATA DAC_IR EF VccADA C DDPC_C TRLCLK CRT_DD C_CLK XTAL25_ OUT VSSA_D AC CLKOUT _PCIE3P CLKOUT _PCIE4P XTAL25_ IN VccAClk CLKOUT _PCIE1P CLKOUT _PCIE0P XCLK_R COMP CLKOUT _PCIE6P Vss Vss CLKOUT _PEG_A _P Vss CLKOUT _PEG_A _N Vss CLKOUT _PEG_B _P Vss CLKOUT _PEG_B _N VccDIFF CLKN CLKOUT _PCIE2N VccDIFF CLKN VssALVD S VccTX_L VDS VccDIFF CLKN Vss VccALVD S VssALVD S Vss Vss Vss
CLKOUT _PCIE1N CLKOUT _PCIE0N
Vss
VccASW
VccASW
VccASW
TP20
TP19
CLKOUT _PCIE2P
Vss
Vss
Vss
VccVRM
VccSSC
VccASW
VccASW
VccASW
Vss
Vss
CLKOUT _PCIE6N
CLKOUT _PCIE5P
CLKOUT _PCIE5N
Vss
Vss
Vss
VccASW
VccASW
VccASW
CLKOUT _PCIE3N CLKOUT _PCIE4N CLKOUT _PCIE7P
Vss
Vss
Vss
Vss
Vss
Vss
Vss
VccASW
VccASW
VccASW
CLKOUT _PCIE7N
SDVO_C TRLCLK
TP23
Vss
Vss DDPC_C TRLDAT A Vss SDVO_C TRLDAT A
Vss DDPD_C TRLDAT A Vss
Vss
Vcc3_3
Vcc3_3
Vss
Vss
VccSusH DA
Vss
Vss
Vss
CRT_RE D CRT_IRT N CRT_GR EEN
NC_1
Vcc3_3
VccSus3 _3
VccSus3 _3
Vss
VCCPUS B
VCCPUS B
Vss
Vcc3_3
L_CTRL_ CLK
Vcc3_3
Vss
VccSus3 _3
VccSus3 _3
Vss
VccSus3 _3
VccSus3 _3
Vss
Vss
CRT_DD C_DATA DDPD_C TRLCLK CRT_BL UE
Vss
Vss
Vss
Vss
V5REF HDA_DO CK_RST #/ GPIO13 Vss HDA_DO CK_EN# / GPIO33 Vss
Vss
Vss
Vss
VccSus3 _3
L_BKLTE N
L_VDD_ EN
L_CTRL_ DATA
V5REF_ Sus
USBP13 N
TP11
USBP8N
USBP4N
Vss
Vss
Vss FWH4 / LFRAME # Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
REQ2# / GPIO52 CLKOUT _PCI3
GPIO68
HDA_SD O
USBP13 P
TP24
USBP8P
USBP4P
REFCLK1 4IN CLKOUT _PCI2
Vss
Vss
Vss
Vss
Vss
Vss
GNT2# / GPIO53 REQ1# / CLKOUT GPIO50 _PCI4 REQ3# / PIRQG# GPIO54 / GPIO4
LDRQ0#
HDA_SY NC
HDA_BC LK
USBP11 N
USBP12 N
USBP3N
USBP6N
Vss
Vss
Vss LDRQ1# / GPIO23
Vss
Vss
Vss
Vss
Vss
GNT1# / GPIO51
PIRQH# / GPIO5
HDA_RS T#
USBP11 P
USBP12 P
USBP3P
USBP6P
CLKOUT _PCI1 CLKOUT PIRQA# FLEX1 / GPIO65 Vss_NCT PIRQB# PIRQC# F GNT3# / GPIO55 HDA_SD IN0 FWH3 / LAD3 HDA_SD IN1 FWH0 / LAD0 HDA_SD IN3 HDA_SD IN2
Vss
Vss
GPIO70
Vss
Vss
USBP7N
Vss
USBP5N
Vss
PIRQD#
GPIO6
PIRQF# / GPIO3
FWH2 / LAD2
USBRBI AS#
USBP10 N
USBP9N
USBP2N
Vss
GPIO17
Vss
GPIO1
Vss
Vss
USBP7P
Vss
USBP5P
Vss
GPIO7
GPIO69
GPIO71
FWH1 / LAD1
USBRBI AS
USBP10 P
USBP9P
USBP2P
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
62
Figure 6-11. Mobile SFF PCH Ballout (Top View - Upper Right)
25
TP36
24
23
DMI1RX N
22
21
DMI0RX N
20
19
DMI2RX P
18
17
DMI3RX N
16
15
FDI_RXP 1
14
13
FDI_RX N0
12
11
FDI_RXP 3
10
9
FDI_RXP 6
7
TP22
1
Vss_NCT F
Reserve Vss_NCT Vss_NCT d F F Reserve d
BL BK
TP2
Vss
DMI2RBI AS DMI0RX P DMI2RX N
Vss
TP4
Vss
FDI_LSY NC0 FDI_RXP 0 FDI_FSY NC0 FDI_RX N3
Vss
FDI_FSY NC1 FDI_RX N6 FDI_LSY NC1 Reserve d
TP40
DMI1RX P
DMI3RX P
FDI_RX N1
Reserve Reserve Vss_NCT d d F Reserve Reserve d d Reserve d
Vss_NCT F Vss_NCT F Reserve d
BJ BH BG BF
TP1
Vss
TP3
Vss
TP5
Vss
Vss
Vss
Vss
DMI0TX P
DMI_ZC OMP
CLKIN_ DMI_P
Vss
FDI_RXP 2
FDI_RX N7
Reserve Reserve d d Reserve d
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Reserve d Reserve d Reserve d Reserve d
Reserve d
BE BD
Vss
DMI0TX N
DMI_IRC OMP
CLKIN_ DMI_N
Vss
FDI_RX N2
FDI_RXP 7 THRMTR IP# PMSYNC H
Vss
Vss
Vss
Vss
Vss
Vss
Vss
DF_TVS
Reserve d
BC BB
CLKOUT _DMI_N
DMI1TX N
DMI2TX N
DMI3TX N
FDI_RXP 4
FDI_RXP 5
FDI_INT
Reserve d
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Reserve d Reserve d Reserve d Reserve d Reserve d
Reserve d
BA AY
CLKOUT _DMI_P
DMI1TX P
DMI2TX P
DMI3TX P
FDI_RX N4
FDI_RX N5
Vss
Reserve d
Vss
Vss
VccVRM
VccVRM
VccDMI
Vss
Vss
Vss
Vss
Reserve d
AW AV
Vss
Vss
VccIO
VccIO
VCCADM I_VRM
VCCAFD I_VRM
Vss
VccDMI
PECI
PROCPW RGD
Reserve d
Reserve d
SATA0TX N
SATA0TX P
AU AT
VccIO CLKOUT _ITPXDP _N VccAFDI PLL CLKOUT _DP_P V_PROC _IO
Vss CLKOUT _ITPXDP _P Vss
Vss
Vss
TP14
TP15
VccIO
VccIO
Vss
Vss
Vss
VccIO
Vss
Vss
SATA1TX N
SATA1TX P
AR AP
Vss
Vss
Vss
VccAPLL EXP
Vss
VccAFDI PLL
Vss
Vss
Vss
Vss
CLKOUT _DP_N
SATA1R XP
SATA1R XN
SATA0R XN VCCAPLL _SATA3 SATA2TX N
SATA0R XP
AN AM
Vss
VccDMI
VccIO
Vss
Vss
TP13
VccDFTE RM VccDFTE RM VccDFTE RM VccDFTE RM TS_VSS 2 TS_VSS 3
Vss
Vss
Vss
SATA2TX P
AL AK
Vss
Vss
VccIO
Vss
Vss
TS_VSS 1
CLKIN_S ATA_N
CLKIN_S ATA_P
Vss
Vss
VccCore
VccCore
VccCore
Vss
VccIO
Vss
Vss
Vss
SATA5TX N SATA4TX P SATA3R BIAS SATA3TX N
SATA5TX P
AJ AH
TS_VSS 4
SATA4TX N
Vss
VccCore
VccCore
VccCore
Vss
Vss
VccIO
VccIO
Vss
Vss
Vss
SATA3TX P
AG
63
Figure 6-12. Mobile SFF PCH Ballout (Top View - Lower Right)
Vss VccCore VccCore Vss VccVRM VccIO SATA3C OMPI SATA3R COMPO Vss Vcc3_3 Vss Vss
AF
SATA4R XP
Vss
VccCore
VccCore
VccVRM
Vss
Vss
Vss
Vss
Vss
Vss
SATA4R XN SATA3R XP SATA2R XN SATA5R XN SPI_CS1 # SATA2R XP
AE AD
SPI_CLK
TP16
SATA3R XN
Vss
VccCore
VccCore
Vcc3_3
Vss
VccIO
VccIO
Vss
Vss
Vss
SATA5R XP
AC AB
Vss
VccCore
VccCore
Vcc3_3
Vss
VccIO
SATAICO MPI
SATAICO MPO
SPI_CS0 #
Vss
Vss SATA5G P/ GPIO49 / TEMP_A LERT# SPI_MIS O SCLOCK / GPIO22 BMBUSY #/ GPIO0 Vss SDATAO UT1 / GPIO48 CLKRUN #/ GPIO32 STP_PCI #/ GPIO34 SATA1G P/ GPIO19 Vss
VccIO
Vss
Vss
Vss
SATA4G P/ GPIO16
AA
VccASW
VccASW
VccASW
VccSPI
Vss
Vss SATA2G P/ GPIO36 Vss PCIECLK RQ1# / GPIO18 Vss PEG_A_ CLKRQ# / GPIO47 Vss
SERIRQ
Y W V U T R P
SPKR
GPIO35
SATALED #
SPI_MO SI
VccASW
VccASW
VccASW
VccASW
Vss
Vss
DcpSus
Vss SDATAO UT0 / GPIO39 Vss
Vss
Vss
VccIO
VccIO
VccASW
VccASW
DcpSST
DcpRTC
JTAG_TD I
RCIN# PCIECLK RQ2# / GPIO20 INIT3_3 V#
A20GAT E
Vss
VccIO
VccIO
Vss
VccASW
Vss
DcpRTC
VccDSW 3_3
DcpSusB yp
Vss
Vss CLKIN_ DOT_96 N Vss CLKIN_ DOT_96 P Vss
Vss
Vss PCIECLK RQ4# / GPIO26 Vss
VccIO
VccRTC
Vss
Vss
Vss
Vss SATA3G P/ GPIO37 Vss PCIECLK RQ5# / GPIO44 PCIECLK RQ0# / GPIO73
SLOAD / GPIO38 SATA0G P/ GPIO21 CL_CLK1
N M
PWROK
JTAG_TC K
JTAG_T MS
JTAG_TD O
SYS_PW ROK
CL_RST 1#
Vss
Vss
Vss
Vss
Vss
Vss
SYS_RE SET#
L K
INTRUD ER#
PWRBTN #
GPIO57
GPIO24
SML0CL K
SLP_S4 #
GPIO15
Vss PCIECLK RQ6# / GPIO45 PCIECLK RQ7# / GPIO46
Vss
Vss SML0AL ERT# / GPIO60 Vss
Vss ACPRES ENT / GPIO31 Vss
Vss
Vss
Vss SMBALE RT# / GPIO11 VSS
Vss BATLOW #/ GPIO72 Vss
Vss
Vss
CL_DAT A1
J H
USBP0P
GPIO8
OC7# / GPIO14
PME#
Vss
Vss
Vss
Vss
Vss
SUS_ST AT# / GPIO61 Vss
APWROK
GPIO28
G F
USBP0N
DSWVR MEN
RTCRST #
SMBCLK
SUSACK #
RI#
SMBDAT A
SLP_S5 PLTRSTB #/ # GPIO63
Vss
TP12 SML1CL K/ GPIO58 SUSWAR N#/SUS PWRDNA CK/GPIO 30 Vss DRAMP WROK OC2# / GPIO41 OC4# / GPIO43 SML1DA TA / GPIO75 SUSCLK SLP_S3 / # GPIO62 LAN_PH PEG_B_ Y_PWR_ CLKRQ# Vss_NCT F CTRL / / GPIO12 GPIO56 Vss SLP_LAN #/ GPIO29
Vss_NCT F Vss_NCT F
E D C B
TP18
Vss
TP10
Vss
OC3# / GPIO42
Vss
Vss SML1AL ERT# / PCHHOT #/ GPIO74 Vss
WAKE#
Vss
USBP1N
OC6# / GPIO10
INTVRM EN
RTCX2
OC0# / GPIO59
GPIO27
SLP_A#
TP17
Vss
RSMRST # DPWRO K
Vss
OC5# / GPIO9 OC1# / GPIO40 SLP_SU S#
PCIECLK RQ3# / GPIO25 SML0DA TA
USBP1P
SRTCRS T#
RTCX1
Vss_NCT Vss_NCT F F
A 3 2 1
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
64
Table 6-3. Mobile SFF PCH Ballout By Signal Name

SFF Ball Name Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
CLKOUT_PCIE6N CLKOUT_PCIE6P CLKOUT_PCIE7N CLKOUT_PCIE7P CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_PEG_B_N CLKOUT_PEG_B_P CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67 CLKRUN# / GPIO32 CRT_BLUE CRT_DDC_CLK CRT_DDC_DATA CRT_GREEN CRT_HSYNC CRT_IRTN CRT_RED CRT_VSYNC DAC_IREF DcpRTC DcpRTC DcpSST DcpSus DcpSus DcpSus DcpSus DcpSusByp DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPB_AUXN DDPB_AUXP DDPB_HPD
AB44 AB46 W44 W46 AF44 AF46 AF40 AF42 H50 D48 G49 J51 T2 M46 R49 N49 R46 M50 T48 U46 N51 R51 R15 U15 U17 AR33 AU31 AU33 V13 R10 AY48 AY50 AY44 AY46 BB44 BB46 BA49 BA51 AW51 AW49 AY42
DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPC_AUXN DDPC_AUXP DDPC_CTRLCLK DDPC_CTRLDATA DDPC_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P DDPD_AUXN DDPD_AUXP DDPD_CTRLCLK DDPD_CTRLDATA DDPD_HPD DF_TVS DMI_IRCOMP DMI_ZCOMP DMI0RXN DMI0RXP DMI0TXN DMI0TXP DMI1RXN DMI1RXP DMI1TXN DMI1TXP DMI2RBIAS DMI2RXN DMI2RXP DMI2TXN DMI2TXP DMI3RXN DMI3RXP
BC49 BC51 BD48 BD50 BF46 BF45 BE49 BE51 AU51 AU49 T50 U44 BE46 BG51 BG49 BF42 BD42 BJ47 BL47 BL45 BJ45 AU46 AU44 M48 U42 BK44 BC7 BD19 BF19 BL21 BJ21 BD22 BF22 BL23 BJ23 BB22 AY22 BK20 BJ19 BL19 BB19 AY19 BL17 BJ17
A20GATE ACPRESENT / GPIO31 APWROK BATLOW# / GPIO72 BMBUSY# / GPIO0 CL_CLK1 CL_DATA1 CL_RST1# CLKIN_DMI_N CLKIN_DMI_P CLKIN_DOT_96N CLKIN_DOT_96P CLKIN_GND1_N CLKIN_GND1_P CLKIN_PCILOOPBA CK CLKIN_SATA_N CLKIN_SATA_P CLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_DP_N CLKOUT_DP_P CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 CLKOUT_PCIE0N CLKOUT_PCIE0P CLKOUT_PCIE1N CLKOUT_PCIE1P CLKOUT_PCIE2N CLKOUT_PCIE2P CLKOUT_PCIE3N CLKOUT_PCIE3P CLKOUT_PCIE4N CLKOUT_PCIE4P CLKOUT_PCIE5N CLKOUT_PCIE5P
U3 H19 G3 H10 W1 L3 J1 M8 BD17 BF17 M24 K24 BB26 AY26 E51 AK8 AK6 BB24 AY24 AN10 AN12 AR12 AR10 G51 E49 H48 J43 G45 AD48 AD50 AE49 AE51 AD40 AD42 AA49 AA51 Y48 Y50 AB40 AB42
65
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
DMI3TXN DMI3TXP DPWROK DRAMPWROK DSWVRMEN FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1 FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 FWH4 / LFRAME# GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 GPIO1 GPIO6 GPIO7 GPIO8 GPIO15 GPIO17 GPIO24 GPIO27 GPIO28 GPIO35 GPIO57
BB17 AY17 A21 B12 F22 BH12 BK8 BB10 BK12 BH8 BL13 BJ15 BD12 BJ11 AY15 AY12 BJ9 BF10 BJ13 BL15 BF12 BL11 BB15 BB12 BL9 BD10 A37 A39 C39 C37 K40 F42 H42 D44 B40 C43 A45 H17 K6 B44 K15 C15 G1 W12 K17
GPIO68 GPIO69 GPIO70 GPIO71 HDA_BCLK HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13 HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_SYNC INIT3_3V# INTRUDER# INTVRMEN JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS L_BKLTCTL L_BKLTEN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN LAN_PHY_PWR_CTR L / GPIO12 LDRQ0# LDRQ1# / GPIO23 LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK LVDSA_CLK# LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0
K42 A43 D40 A41 H35 K35 M35 F35 D36 B36 C35 A35 K37 H37 R6 K22 C21 M17 U12 M12 M15 L49 M44 R42 M40 L51 K46 M42 C5 H40 F37 AH42 AH40 AG51 AG49 AK46 AK44 AR46 AN49 AN44 AK40 AR44
LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK LVDSB_CLK# LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3 NC_1 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 PCIECLKRQ0# / GPIO73 PCIECLKRQ1# / GPIO18 PCIECLKRQ2# / GPIO20 PCIECLKRQ3# / GPIO25 PCIECLKRQ4# / GPIO26 PCIECLKRQ5# / GPIO44 PCIECLKRQ6# / GPIO45 PCIECLKRQ7# / GPIO46 PECI PEG_A_CLKRQ# / GPIO47 PEG_B_CLKRQ# / GPIO56 PERn1 PERn2 PERn3 PERn4
AN51 AN46 AK42 AH44 AH46 AM50 AL49 AJ51 AH50 AM48 AL51 AJ49 AH48 U40 C17 A17 A13 D16 A11 B16 C23 H15 M4 U8 T4 B8 M19 K8 J3 H4 AU12 R8 C4 BJ33 BJ35 BH36 BJ37
66
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
PERn5 PERn6 PERn7 PERn8 PERp1 PERp2 PERp3 PERp4 PERp5 PERp6 PERp7 PERp8 PETn1 PETn2 PETn3 PETn4 PETn5 PETn6 PETn7 PETn8 PETp1 PETp2 PETp3 PETp4 PETp5 PETp6 PETp7 PETp8 PIRQA# PIRQB# PIRQC# PIRQD# PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5 PLTRST# PME# PMSYNCH PROCPWRGD PWRBTN# PWROK RCIN# REFCLK14IN
BJ39 BH40 BJ41 BJ43 BL33 BL35 BK36 BL37 BL39 BK40 BL41 BL43 BB30 BB33 BF33 BD35 AY35 BD37 AY37 AY40 AY30 AY33 BD33 BF35 BB35 BF37 BB37 BB40 D49 C48 C47 C45 A47 C41 F45 F40 F7 H2 BB8 AU10 K19 M22 U6 J49
REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RI# RSMRST# RTCRST# RTCX1 RTCX2 SATA0GP / GPIO21 SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1GP / GPIO19 SATA1RXN
G46 K44 F46 AU6 AU8 AW1 AW3 AY2 AY4 AY6 AY8 BA1 BA3 BB6 BC1 BC3 BD2 BD4 BE1 BE3 BE6 BF6 BF7 BG1 BG3 BH3 BH4 BJ4 BJ5 BJ7 BK6 BL5 F12 B20 F19 A19 C19 M2 AN3 AN1 AU3 AU1 R1 AN6
SATA1RXP SATA1TXN SATA1TXP SATA2GP / GPIO36 SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3COMPI SATA3GP / GPIO37 SATA3RBIAS SATA3RCOMPO SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4GP / GPIO16 SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5GP / GPIO49 / TEMP_ALERT# SATA5RXN SATA5RXP SATA5TXN SATA5TXP SATAICOMPI SATAICOMPO SATALED# SCLOCK / GPIO22 SDATAOUT0 / GPIO39 SDATAOUT1 / GPIO48 SDVO_CTRLCLK SDVO_CTRLDATA SDVO_INTN SDVO_INTP SDVO_STALLN SDVO_STALLP SDVO_TVCLKINN SDVO_TVCLKINP SERIRQ SLOAD / GPIO38
AN8 AR3 AR1 W6 AD4 AD2 AL3 AL1 AF12 M6 AH4 AF10 AD8 AD6 AG3 AG1 AA3 AE3 AE1 AH8 AH6 AA1 AC3 AC1 AJ3 AJ1 AB12 AB10 W10 W3 U10 U1 W42 R44 AT50 AT48 AR51 AR49 AU40 AU42 Y4 N3
67
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SLP_A# SLP_LAN# / GPIO29 SLP_S3# SLP_S4# SLP_S5# / GPIO63 SLP_SUS# SMBALERT# / GPIO11 SMBCLK SMBDATA SML0ALERT# / GPIO60 SML0CLK SML0DATA SML1ALERT# / PCHHOT# / GPIO74 SML1CLK / GPIO58 SML1DATA / GPIO75 SPI_CLK SPI_CS0# SPI_CS1# SPI_MISO SPI_MOSI SPKR SRTCRST# STP_PCI# / GPIO34 SUS_STAT# / GPIO61 SUSACK# SUSCLK / GPIO62 SUSWARN#/SUSPW RDNACK/GPIO30 SYS_PWROK SYS_RESET# THRMTRIP# TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10
C7 A7 D4 K10 F6 A15 H12 F17 F10 H22 K12 A9 C9 D12 C11 AD12 AB8 AB6 Y2 W8 N1 A23 R3 G6 F15 D3 C13 M10 L1 BC9 BH24 BK24 BH20 BK16 BH16 AN42 AN40 AR40 AR42 D20
TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 TP41 TP42 TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N
M30 E3 AM4 AT4 AT2 AD10 B24 D24 AD44 AD46 BJ48 BL7 W40 K30 BJ25 BJ27 BJ31 BJ29 BL25 BL27 BL31 BL29 BF26 BB28 BF28 BF30 BD26 AY28 BD28 BD30 BH49 BB42 AK10 AH12 AK12 AH10 F24 H24 C25 A25 C27 A27 H28 F28 M26
USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS USBRBIAS# V_PROC_IO V5REF V5REF_Sus Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 Vcc3_3 VccAClk VccADAC VccADPLLA VccADPLLB VccAFDIPLL VccAFDIPLL VccALVDS VccALVDS VccAPLLDMI2 VccAPLLEXP VccAPLLSATA VccASW
K26 D28 B28 H26 F26 D32 B32 M28 K28 C29 A29 C31 A31 H33 F33 H30 F30 M33 K33 A33 C33 AM17 N36 M37 AB19 AC19 AF6 BK28 R40 T39 U37 V37 V39 AC51 U51 BF40 BD40 AP13 AP15 AF33 AG33 AW31 AP19 AM2 AB27
68
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccASW VccClkDMI VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore VccCore
AB29 AB31 AC27 AC29 AC31 AE27 AE29 AE31 R19 U19 U21 V19 V21 V23 V25 Y21 Y23 Y25 Y27 Y29 Y31 AP39 AB21 AB23 AC21 AC23 AE21 AE23 AF21 AF23 AG21 AG23 AG25 AG27 AJ21 AJ23 AJ25 AJ27 AJ29 AJ31 AK29 AK31 AK33 AM33
VccCore VccDFTERM VccDFTERM VccDFTERM VccDFTERM VccDIFFCLKN VccDIFFCLKN VccDIFFCLKN VccDMI VccDMI VccDMI VccDSW3_3 VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccIO VccRTC VccSPI VccSSC VccSus3_3
AM35 AJ13 AJ15 AK15 AL13 AC37 AE37 AE39 AM23 AU15 AW16 R12 AA13 AB15 AC13 AC15 AF15 AG13 AG15 AJ17 AK21 AM21 AP27 AR15 AR23 AR25 AR27 AR29 AT13 AU23 AU25 AU27 AU29 AU35 AW34 N18 R23 R25 U23 U25 N16 Y19 AC35 AM27
VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSus3_3 VccSusHDA VccTX_LVDS VccTX_LVDS VccTX_LVDS VccTX_LVDS VccVRM VccVRM VccVRM VccVRM VccVRM VccVRM VccVRM Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss
N27 R27 R29 R33 R35 U27 U29 U33 U35 V31 AF37 AG37 AG39 AJ37 AC39 AE19 AF17 AU19 AU21 AW18 AW21 AA11 AA39 AA41 AA43 AA45 AA7 AA9 AB17 AB2 AB25 AB33 AB35 AB37 AB4 AB48 AB50 AC11 AC17 AC25 AC41 AC43 AC45 AC7
69
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss
AC9 AE11 AE13 AE15 AE17 AE25 AE35 AE41 AE43 AE45 AE7 AE9 AF19 AF2 AF25 AF27 AF29 AF31 AF35 AF4 AF48 AF50 AF8 AG11 AG17 AG19 AG29 AG31 AG35 AG41 AG43 AG45 AG7 AG9 AH2 AJ11 AJ19 AJ33 AJ35 AJ39 AJ41 AJ43 AJ45 AJ7 AJ9
AK17 AK19 AK2 AK23 AK25 AK27 AK35 AK37 AK4 AK48 AK50 AL11 AL39 AL41 AL43 AL45 AL7 AL9 AM15 AM19 AM25 AM29 AM31 AM37 AP11 AP17 AP2 AP21 AP23 AP25 AP29 AP31 AP33 AP35 AP37 AP4 AP41 AP43 AP45 AP48 AP50 AP7 AP9 AR17 AR19
AR21 AR31 AR35 AR37 AR6 AR8 AT11 AT39 AT41 AT43 AT45 AT7 AT9 AU17 AU37 AV2 AV4 AV48 AV50 AW11 AW13 AW23 AW25 AW27 AW29 AW36 AW39 AW41 AW43 AW45 AW7 AW9 AY10 B10 B14 B18 B22 B26 B30 B34 B38 B42 B46 B6 BA11
70
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss
BA13 BA16 BA18 BA21 BA23 BA25 BA27 BA29 BA31 BA34 BA36 BA39 BA41 BA43 BA45 BA7 BA9 BB2 BB4 BB48 BB50 BC11 BC13 BC16 BC18 BC21 BC23 BC25 BC27 BC29 BC31 BC34 BC36 BC39 BC41 BC43 BC45 BD15 BD24 BE11 BE13 BE16 BE18 BE21
BE23 BE25 BE27 BE29 BE31 BE34 BE36 BE39 BE41 BE43 BE45 BE7 BE9 BF15 BF2 BF24 BF4 BF48 BF50 BH10 BH14 BH18 BH22 BH26 BH28 BH30 BH32 BH34 BH38 BH42 BH44 BH46 BH48 BH6 BK10 BK14 BK18 BK22 BK26 BK30 BK32 BK34 BK38 BK42
BK46 D10 D14 D18 D22 D26 D30 D34 D38 D42 D46 D6 F2 F4 F48 F50 G11 G13 G16 G18 G21 G23 G25 G27 G29 G31 G34 G36 G39 G41 G43 G7 G9 J11 J13 J16 J18 J21 J23 J25 J27 J29 J31 J34
71
SFF Ball Name
Ball #
SFF Ball Name
Ball #
SFF Ball Name
Ball #
J36 J39 J41 J45 J7 J9 K2 K4 K48 K50 L11 L13 L16 L18 L21 L23 L25 L27 L29 L31 L34 L36 L39 L41 L43 L45 L7 L9 N11 N13 N21 N23 N25 N29 N31 N34 N39 N41 N43 N45 N7 N9 P2 P4 P48
Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF
P50 R17 R21 R31 R37 T11 T13 T41 T43 T45 T7 T9 U31 U49 V11 V15 V17 V2 V27 V29 V33 V35 V4 V41 V43 V45 V48 V7 V9 Y15 Y17 Y33 Y35 Y37 A4 A48 A49 A5 A51 BH1 BH51 BJ1 BJ3 BJ49 BJ51
Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF Vss_NCTF VssADAC VssALVDS VssALVDS WAKE# XCLK_RCOMP XTAL25_IN XTAL25_OUT
BL1 BL3 BL4 BL48 BL49 BL51 C3 C49 C51 D1 D51 E1 V50 AC33 AE33 D8 AC49 W49 W51
72
22.
Thermal Sensor Thermometer Read Register Updates

Section 22.2.4 TSTRThermal Sensor Thermometer Read Register is modified as shown: Offset Address: TBARB+03h Attribute: RO Default Value: yFh (y = x111b) Size: 8 bit This register provides the calibrated current temperature from the thermometer circuit when the thermometer is enabled.
Bit 7 Reserved Thermometer Reading (TR) RO. Value corresponds to the thermal sensor temperature. A value of 00h means the hottest temperature and 7Fh is the lowest. The range is approximately between 40 C to 130 C. Temperature below 40 C will be truncated to 40 C. Description
6:0
23.
DC Inputs Characteristics Tables Corrections

a. All notes are removed from the end of table 8-7 DC Characteristic Input Signal Association. b. (1) removed from SML[1:0]CLK, SML[1:0]DATA in table 8-7 DC Characteristic Input Signal Association. c. Table 8-8 DC Input Characteristics and its notes are modified as follows: i) Note 11 is removed from VIL6. ii) Note 10 is removed from VIL16. iii) Note 8 is removed from the table.
24.
CPU_PWR_FLR Removal
In table 5-39 Event Transitions that Cause Messages, the CPU_PWR_FLR event is removed from the table as this is no longer a valid event.
25.
Miscellaneous Documentation Corrections V

a. t121gen3 max is changed to 0.48. b. Usages of display port not referring to the DisplayPort interface are changed to digital port or display interface throughout the document as well as changing display port to DisplayPort when referring to the interface. c. The attribute of TCO_EN (PMBASE+30h:bit 13) is changed from R/W to R/WL. d. The attribute of GBL_SMI_EN (PMBASE+30h:bit 0) is changed from R/W to R/WL. e. The second paragraph of section 5.21.3.1 Supported Addresses is removed.
73
f. The following sentence in section 5.21.3.6 Temperature Comparator and Alert: In general the TEMP_ALERT# signal will assert within a 14 seconds, depending on the actual BIOS implementation and flow. is changed to: In general the TEMP_ALERT# signal will assert within 14 seconds, depending on the actual BIOS implementation and flow. g. Section 5.21.3.8.2 title is changed from Power On to Block Read Special Handling h. Note 1 is added to PWM[3:0] in table 8-9 DC Characteristic Output Signal Association.
26.
PCI Express* Initialization Registers Corrections

19.1.62 PECR2 PCI Express* Configuration Register 2 and 19.1.64 PEC1 PCI Express Configuration Register 1 are removed from the Datasheet. No BIOS programming is required.
27.
VccSus3_3 Description
The description for VccSus3_3 in table 2-26 is changed as shown:
Name VccSus3_3
Description 3.3 V supply for suspend well I/O buffers. This power may be shut off in the Deep S4/S5 or G3 states.
28.
Register Default Value Corrections

The following table lists the correct default value for the given register at the location of the incorrect value.
Register Name
USBOCM1 BIOS_CNTL CAP EHCIIR1 XCAP DCAP SLCAP CEM SSFC FRAP CC CC HTYPE HTYPE HERES HERES ME_CB_RW ME_CB_RW
Location of Incorrect Default Value

Table 10-1 Table 13-1 Table 15-1 Section 16.1.31 Table 19-1 Table 19-1 Table 19-1 Table 19-1 Table 21-1 Table 21-2 Table 23-1 Table 23-3 Table 23-1 Table 23-3 Section 23.1.1.26 Section 23.2.1.25 Table 23-2 Table 23-4 20h 70h
Correct Default Value

C0300C03h
83088E01h 0042h 00008000h 00040060h 00002000h F80000h 00000088h 078000h 078000h 80h 80h 40000000h 40000000h FFFFFFFFh FFFFFFFFh
74
Register Name
INTR INTR ME_UMA KTIIR KTLCR SCTLBA
Location of Incorrect Default Value

Table 23-3 Section 23.2.1.12 Table 23-1 Section 23.4.2.6 Section 23.4.2.8 Section 23.3.1.11 0200h 0200h
Correct Default Value
80000000h 01h 03h 00000001h
29.
Miscellaneous Documentation Corrections VI

a. Section 15.1.33 title is changed to ATS-APM Trapping Status Register. b. Section 16.1.37 mnemonic is changed to FLR_STAT.
30.
Miscellaneous Documentation Correction VII

Section 10.1.80 FDSWFunction Disable SUS Well Register is updated as shown:
Bit Description Function Disable SUS Well Lockdown (FDSWL) R/W 7 0 = FDSW registers are not locked down. 1 = FDSW registers are locked down and this bit will remain set until a global reset occurs. NOTE: This bit must be set when Intel Active Management Technology is enabled.
31.
Function Level Reset Pending Status Register Correction

Section 10.1.4 FLRSTATFunction Level Reset Pending Status Register is updated as shown:
Bit 31:24 23 22:16 15 14:0 Reserved FLR Pending Status for EHCI #1 (D29) RO. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. Reserved FLR Pending Status for EHCI #2 (D26) RO. 0 = Function Level Reset is not pending. 1 = Function Level Reset is pending. Reserved Description
32.
Miscellaneous Documentation Correction VIII

In section 21.1 Serial Peripheral Interface Memory Mapped Configuration Registers, the RCBA register cross reference is corrected to be Section 13.1.39 (the RCBARoot Complex Base Address Register).
75
33.
SPI Required Region Correction

The second paragraph of section 5.24.1.2.1 SPI Flash Regions is changed to the following: Only three masters can access the four regions: Host processor running BIOS code, Integrated Gigabit Ethernet and Host processor running Gigabit Ethernet Software, and Intel Management Engine. The Flash Descriptor and Intel ME region are the only required regions. The Flash Descriptor has to be in Region 0 and Region 0 must be located in the first sector of Device 0 (offset 10).
34.
High Precision Event Timers Functional Description

a. The following replaces section 5.17: 5.17 High Precision Event Timers (HPET) This function provides a set of timers that can be used by the operating system. The timers are defined such that the operating system may be able to assign specific timers to be used directly by specific applications. Each timer can be configured to cause a separate interrupt. The PCH provides eight timers. The timers are implemented as a single counter, and each timer has its own comparator and value register. The counter increases monotonically. Each individual timer can generate an interrupt when the value in its value register matches the value in the main counter. The registers associated with these timers are mapped to a memory space (much like the I/O APIC). However, it is not implemented as a standard PCI function. The BIOS reports to the operating system the location of the register space. The hardware can support an assignable decode space; however, the BIOS sets this space prior to handing it over to the operating system. It is not expected that the operating system will move the location of these timers once it is set by the BIOS. 5.17.1 Timer Accuracy 1. The timers are accurate over any 1 ms period to within 0.05% of the time specified in the timer resolution fields. 2. Within any 100 microsecond period, the timer reports a time that is up to two ticks too early or too late. Each tick is less than or equal to 100 ns, so this represents an error of less than 0.2%. 3. The timer is monotonic. It does not return the same value on two consecutive reads (unless the counter has rolled over and reached the same value). The main counter is clocked by the 14.31818 MHz clock. The accuracy of the main counter is as accurate as the 14.31818 MHz clock. 5.17.2 Interrupt Mapping The interrupts associated with the various timers have several interrupt mapping options. When reprogramming the HPET interrupt routing scheme (LEG_RT_CNF bit in the General Configuration Register), a spurious interrupt may occur. This is because the other source of the interrupt (8254 timer) may be asserted. Software should mask interrupts prior to clearing the LEG_RT_CNF bit.
Mapping Option #1 (Legacy Replacement Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is set. This forces the mapping found in Table 5-41.
76
Table 5-41 Legacy Replacement Routing

Timer 0 1 2&3 4, 5, 6, 7 8259 Mapping IRQ0 IRQ8 Per IRQ Routing Field. not available APIC Mapping IRQ2 IRQ8 Per IRQ Routing Field not available Comment In this case, the 8254 timer will not cause any interrupts In this case, the RTC will not cause any interrupts.
NOTE: The Legacy Option does not preclude delivery of IRQ0/IRQ8 using processor message interrupts.
Mapping Option #2 (Standard Option)

In this case, the Legacy Replacement Rout bit (LEG_RT_CNF) is 0. Each timer has its own routing control. The interrupts can be routed to various interrupts in the 8259 or I/O APIC. A capabilities field indicates which interrupts are valid options for routing. If a timer is set for edge-triggered mode, the timers should not be shared with any PCI interrupts. For the PCH, the only supported interrupt values are as follows: Timer 0 and 1: IRQ20, 21, 22 & 23 (I/O APIC only). Timer 2: IRQ11 (8259 or I/O APIC) and IRQ20, 21, 22 & 23 (I/O APIC only). Timer 3: IRQ12 (8259 or I/O APIC) and IRQ 20, 21, 22 & 23 (I/O APIC only). Interrupts from Timer 4, 5, 6, 7 can only be delivered using processor message interrupts.
Mapping Option #3 (Processor Message Option)

In this case, the interrupts are mapped directly to processor messages without going to the 8259 or I/O (x) APIC. To use this mode, the interrupt must be configured to edge-triggered mode. The Tn_PROCMSG_EN_CNF bit must be set to enable this mode. When the interrupt is delivered to the processor, the message is delivered to the address indicated in the Tn_PROCMSG_INT_ADDR field. The data value for the write cycle is specified in the Tn_PROCMSG_INT_VAL field. Notes: 1. The processor message interrupt delivery option has HIGHER priority and is mutually exclusive to the standard interrupt delivery option. Thus, if the Tn_PROCMSG_EN_CNF bit is set, the interrupts will be delivered directly to the processor rather than via the APIC or 8259.
77
2. The processor message interrupt delivery can be used even when the legacy mapping is used. 3. The IA-PC HPET Specification uses the term FSB Interrupt to describe these type of interrupts. 5.17.3 Periodic vs. Non-Periodic Modes
Non-Periodic Mode
Timer 0 is configurable to 32 (default) or 64-bit mode, whereas Timers 1:7 only support 32-bit mode (See Section 20.1.5). Warning: Software must be careful when programming the comparator registers. If the value written to the register is not sufficiently far in the future, then the counter may pass the value before it reaches the register and the interrupt will be missed. The BIOS should pass a data structure to the OS to indicate that the OS should not attempt to program the periodic timer to a rate faster than 5 microseconds. All of the timers support non-periodic mode. Refer to Section 2.3.9.2.1 of the IA-PC HPET Specification for more details of this mode.
Periodic Mode
Timer 0 is the only timer that supports periodic mode. Refer to Section 2.3.9.2.2 of the IA-PC HPET Specification for more details of this mode. If the software resets the main counter, the value in the comparators value register needs to reset as well. This can be done by setting the TIMERn_VAL_SET_CNF bit. Again, to avoid race conditions, this should be done with the main counter halted. The following usage model is expected: 1. Software clears the ENABLE_CNF bit to prevent any interrupts. 2. Software Clears the main counter by writing a value of 00h to it. 3. Software sets the TIMER0_VAL_SET_CNF bit. 4. Software writes the new value in the TIMER0_COMPARATOR_VAL register. 5. Software sets the ENABLE_CNF bit to enable interrupts. The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-bit write in a 32-bit environment except if only the periodic rate is being changed during run-time. If the actual Timer 0 Comparator Value needs to be reinitialized, then the following software solution will always work regardless of the environment: 1. Set TIMER0_VAL_SET_CNF bit. 2. Set the lower 32 bits of the Timer0 Comparator Value register. 3. Set TIMER0_VAL_SET_CNF bit. 4. Set the upper 32 bits of the Timer0 Comparator Value register. 5.17.4 Enabling the Timers The BIOS or operating system PnP code should route the interrupts. This includes the Legacy Rout bit, Interrupt Rout bit (for each timer), and interrupt type (to select the edge or level type for each timer).
78
The Device Driver code should do the following for an available timer: 1. Set the Overall Enable bit (Offset 10h, bit 0). 2. Set the timer type field (selects one-shot or periodic). 3. Set the interrupt enable. 4. Set the comparator value. 5.17.5 Interrupt Levels Interrupts directed to the internal 8259s are active high. See Section 5.9 for information regarding the polarity programming of the I/O APIC for detecting internal interrupts. If the interrupts are mapped to the 8259 or I/O APIC and set for level-triggered mode, they can be shared with PCI interrupts. If more than one timer is configured to share the same IRQ (using the TIMERn_INT_ROUT_CNF fields), then the software must configure the timers to level-triggered mode. Edge-triggered interrupts cannot be shared. 5.17.6 Handling Interrupts Section 2.4.6 of the IA-PC HPET Specification describes Handling Interrupts. 5.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors Section 2.4.7 of the IA-PC HPET Specification describes Issues Related to 64-Bit Timers with 32-Bit Processors. b. The following replaces section 5.27.5: 5.27.5 Virtualization Support for High Precision Event Timer (HPET) The Intel VT-d architecture extension requires Interrupt Messages to go through the similar Address Remapping as any other memory requests. This is to allow domain isolation for interrupts such that a device assigned in one domain is not allowed to generate interrupts to another domain. The Address Remapping for Intel VT-d is based on the Bus:Device:Function field associated with the requests. Hence, it is required for the HPET to initiate processor message interrupts using unique Bus:Device:Function. The PCH supports BIOS programmable unique Bus:Device:Function for each of the HPET timers. The Bus:Device:Function field does not change the HPET functionality in anyway, nor promoting it as a stand-alone PCI device. The field is only used by the HPET timer in the following: As the Requestor ID when initiating processor message interrupts to the processor As the Completer ID when responding to the reads targeting its Memory-Mapped registers The registers for the programmable Bus:Device:Function for HPET timer 7:0 reside under the Device 31:Function 0 LPC Bridges configuration space.
79
35.
Miscellaneous Documentation Corrections IX

a. Remove 1.05 V Core Voltage from Platform Controller Hub Features section. b. The GPIO bullet in the Platform Controller Hub Features section is replaced with the following:
GPIO Inversion; Open-Drain (not available on all GPIOs) GPIO lock down
c. The first sentence of the seventh paragraph of section 1.1 About This Manual is changed to: This manual assumes a working knowledge of the vocabulary and principles of interfaces and architectures such as PCI Express*, USB, AHCI, SATA, Intel High Definition Audio (Intel HD Audio), SMBus, PCI, ACPI and LPC. d. Table 1-1 Industry Specifications is updated as follows: 1. The URL for IA-PC HPET (High Precision Event Timers) Specification, Revision 1.0a is changed to: http://www.intel.com/content/www/us/en/software-developers/software-developers-h pet-spec-1-0a.html 2. The URL for SFF-8485 Specification for Serial GPIO (SGPIO) Bus, Revision 0.7 is changed to: ftp://ftp.seagate.com/sff/SFF-8485.PDF 3. The URL for Advanced Host Controller Interface specification for Serial ATA, Revision 1.3 is changed to: http://www.intel.com/content/www/us/en/io/serial-ata/serial-ata-ahci-spec-rev1_3.ht ml 4. The URL for Intel High Definition Audio Specification, Revision 1.0a is changed to: http://www.intel.com/content/www/us/en/standards/standards-high-def-audio-specsgeneral-technology.html e. The Function Disable bullet of the Manageability subsection of section 1.2.1 Capability Overview is replaced as follows: Function Disable. The PCH provides the ability to disable most integrated functions, including integrated LAN, USB, LPC, Intel HD Audio, SATA, PCI Express, and SMBus. Once disabled, functions no longer decode I/O, memory, or PCI configuration space. Also, no interrupts or power management events are generated from the disabled functions. f. The second paragraph of section 5.16.7 Intel Rapid Storage Technology Configuration is replaced as follows: By using the PCHs built-in Intel Rapid Storage Technology, there is no loss of additional PCIe/system resources or add-in card slot/motherboard space footprint used compared to when a discrete RAID controller is implemented.
80
g. The fourth sentence of the first paragraph of section 5.19.1 [USB 2.0 RMH] Overview is replaces as follows: The RMHs will appear to software like an external hub is connected to Port 0 of each EHCI controller. h. Occurrences of DOCK_RST# are changed to HDA_DOCK_RST#. i. The default value for section 10.1.27 D22IPDevice 22 Interrupt Pin Register is changed from 00000001h to 00004321h. j. R/W/C attribute is changed to R/WC. k. Section 23.1.1.12 INTRInterrupt Information Register (Intel MEI 1D22:F0) is updated as shown: Default Value: 0100h Size: 16 bits
Bit Description Interrupt Pin (IPIN) RO. This indicates the interrupt pin the Intel MEI host controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the MEI1IP bits (RCBA+3124:bits 3:0).
15:8
l. Section 23.1.1.25 HIDMMEI Interrupt Delivery Mode Register (Intel MEI 1D22:F0) is updated as shown:
Bit Description Intel MEI Interrupt Delivery Mode (HIDM) R/W. These bits control what type of interrupt the Intel MEI will send the host. They are interpreted as follows: 1:0 00 = Generate Legacy or MSI interrupt 01 = Generate SCI 10 = Generate SMI
m. Section 23.2.1.12 INTRInterrupt Information Register (Intel MEI 2D22:F1) is updated as shown: Default Value: 0200h Size: 16 bits
Bit Description Interrupt Pin (IPIN) RO. This indicates the interrupt pin the Intel MEI host controller uses. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the MEI2IP bits (RCBA+3124:bits 7:4).
15:8
n. Section 23.2.1.24 HIDMIntel MEI Interrupt Delivery Mode Register (Intel MEI 2D22:F1) is updated as shown:
Bit Description Intel MEI Interrupt Delivery Mode (HIDM) R/W. These bits control what type of interrupt the Intel MEI will send the host. They are interpreted as follows: 1:0 00 = Generate Legacy or MSI interrupt 01 = Generate SCI 10 = Generate SMI
81
o. Section 23.3.1.16 INTRInterrupt Information Register (IDERD22:F2) is updated as shown:

Bit Description Interrupt Pin (IPIN) RO. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the IDERIP bits (RCBA+3124:bits 11:8).
15:8
p. Section 23.4.1.13 INTRInterrupt Information Register (KTD22:F3) is updated as shown: Default Value: 0400h Size: 16 bits
Bit Description Interrupt Pin (IPIN) RO. A value of 1h/2h/3h/4h indicates that this function implements legacy interrupt on INTA/INTB/INTC/INTD, respectively. The upper 4 bits are hardwired to 0 and the lower 4 bits are programmed by the KTIP bits (RCBA+3124:bits 15:12).
15:8
82

6 and c200 Chipset Specification Update

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Intel 6 Series Chipset and Intel C200 Series Chipset

Document Number: 324646-019

Affected Documents/Related Documents

Summary Tables of Changes

Summary Tables of Changes

Codes Used in Summary Tables

Summary Tables of Changes

Summary Tables of Changes

Documentation Changes (Sheet 1 of 2)

Summary Tables of Changes

Documentation Changes (Sheet 2 of 2)

PCH Device and Revision Identification

PCH Device and Revision Identification

04h 04h 04h 04h 04h 04h

05h 05h 05h 05h 05h 05h

PCH Device and Revision Identification

PCH Device and Revision ID Table (Sheet 2 of 3)

PCH Device and Revision Identification

PCH Device and Revision ID Table (Sheet 3 of 3)

Dev ID 1C33h5 1C3Ah 1C3Bh 1C3Ch 1C3Dh

B2 Rev ID 04h 04h 04h 04h 04h

B3 Rev ID 05h 05h 05h 05h 05h

USB Isoch In Transfer Error Issue

Workaround: None. Status: No Plan to Fix.

USB Full-/low-speed Device Removal Issue

Workaround: None. Status:

USB Babble Detected with SW Overscheduling

Workaround: None. Status:

USB Full-/low-speed EOP Issue

Workaround: None. Status:

USB PLL Control FSM not Getting Reset on Global Reset

Workaround: None. Status:

Asynchronous Retries Prioritized Over Periodic Transfers

Workaround: None. Status:

USB FS/LS Incorrect Number of Retries

Workaround: None. Status: No Plan to Fix.

Incorrect Data for FS/LS USB Periodic IN Transaction

Implication: Note: Status:

HDMI* 222 MHz Electrical Compliance Testing Failures

Workaround: None. Status:

SATA Signal Voltage Level Violation

SATA Differential Return Loss Violations

High-speed USB 2.0 Transmit Signal Amplitude

There are no known functional failures. No Plan to Fix.

Delayed Periodic Traffic Timeout Issue

SATA Ports 2-5 Issue

Intel ME Clock Throttling Failure Causes Hang

USB Full-/Low-speed Port Reset or Clear TT Buffer Request

Implication: Note: Status:

Intel 82579 Gigabit Ethernet Controller Transmission Issue

USB RMH Think Time Issue

Implication: Note: Status:

USB RMH False Disconnect Issue

Workaround: None. Status:

USB RMH Think Time Issue

Packet Loss on Intel 82579 Gigabit Ethernet Controller