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    Introduction To VLSI Design: Etching Silicon Ingot

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    Cruise_Ice
    This document provides an introduction and overview of VLSI (Very Large Scale Integration) design. It defines VLSI as integrated circuits containing over 1 million transistors. Modern chips can contain over 100 million transistors on a 1 cm^2 die. The document outlines the VLSI design process including capturing the design, logic simulation, synthesis, layout generation, and testing. Key terms like wafer, die, substrate and dimensions are also defined.

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    Introduction To VLSI Design: Etching Silicon Ingot

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    Cruise_Ice
    282 views11 pages
    This document provides an introduction and overview of VLSI (Very Large Scale Integration) design. It defines VLSI as integrated circuits containing over 1 million transistors. Modern chips can contain over 100 million transistors on a 1 cm^2 die. The document outlines the VLSI design process including capturing the design, logic simulation, synthesis, layout generation, and testing. Key terms like wafer, die, substrate and dimensions are also defined.

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    VLSI

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    Introduction to VLSI

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    This document provides an introduction and overview of VLSI (Very Large Scale Integration) design. It defines VLSI as integrated circuits containing over 1 million transistors. Modern chips can contain over 100 million transistors on a 1 cm^2 die. The document outlines the VLSI design process including capturing the design, logic simulation, synthesis, layout generation, and testing. Key terms like wafer, die, substrate and dimensions are also defined.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    282 views11 pages

    Introduction To VLSI Design: Etching Silicon Ingot

    Uploaded by

    Cruise_Ice
    This document provides an introduction and overview of VLSI (Very Large Scale Integration) design. It defines VLSI as integrated circuits containing over 1 million transistors. Modern chips can contain over 100 million transistors on a 1 cm^2 die. The document outlines the VLSI design process including capturing the design, logic simulation, synthesis, layout generation, and testing. Key terms like wafer, die, substrate and dimensions are also defined.

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    Introduction to VLSI Design

    Etching Silicon Ingot


    1 cm

    1 cm

    Wafers

    Chip or Die

    Overview
    VLSI - Very Large Scale Integration A VLSI device contains more than 106 devices (transistors or logic gates) Currently, VLSI devices containing in excess of 108 transistors on a 1 cm2 die, can be manufactured The design and production of such devices is highly technical and involves many engineering disciplines.....

    Glossary
    Integrated Circuit
    A combination of interconnected circuit elements inseparably associated on or within a continuous substrate

    Substrate
    The supporting material upon or within which an IC is fabricated, or to which an IC is attached

    Monolithic IC
    An IC whose elements are formed in place upon or within a semiconductor substrate with at least one of the elements formed within the substrate

    Wafer
    Basic physical unit used in processing, contains a large number of identical ICs. Typically 6 to 10 inches in diameter, recently 30 cm (12 inch) wafers have been produced

    Chip(Die or Bar)
    One of the repeated ICs on a wafer. A typical wafer may accommodate several hundred ICs depending on the area of the individual IC and the diameter of the wafer

    Microelectronics
    Inert Substrate Thick Film MOS Thin Film

    Taxonomy of IC Fabrication Technologies

    Active Substrate Silicon Bipolar Gallium Arsenide MESFET Bipolar

    NMOS

    PMOS TTL BiCMOS I 2L ECL Linear

    CMOS

    electronics sand

    idea

    engineers CAD layout

    simulation test marketing

    economics cash
    Design funnel

    software

    Chip

    Complexity and Geometry


    Two views of VLSI technology
    Complexity : number of transistors on a die Geometry : dimensions of an individual transistor

    W L 1 million

    Complexity 1/Geometry

    Moores Law
    Gordon Moore, one of the co-founders of the Intel Corporation, projected that due to technological advances, the number of transistors on a chip would double about every 18 months.

    Slow down due to limitations of materials and equipment

    Wafer and Die


    Wafer diameter Pad ring

    ALU DSP RAM Control

    Core logic die or chip Scribe lines

    No. of die per Wafer N Areawafer/Areadie

    Dimensions
    The two most commonly used dimensions used in VLSI are the Micron and the Angstrom Microns are used to express the lateral dimensions of layout shapes Angstroms are used to express the vertical dimensions of layout shapes Angstrom Meter(m) Micron(u) Angstrom(A) 1010A 104A Micron 106u 10-4u Meter 10-6m 10-10m

    MOS Transistor Dimensions


    Silicon Dioxide

    W
    Polysilicon

    N+

    N+

    L
    Oxide thickness (tox, typically 100A)

    P-type substrate

    Since the beginning of the IC era (1958), the minimum MOS length (L) and width (W), along with the oxide thickness (tox) have been reducing due to advances in manufacturing technology. For example, in 1980 a typical process feature size was 5 micron (L = W = 5u). Currently, state-of-the-art processes support sub-micron feature sizes such as 0.13 micron (130 nm or 1300A). The packing density is inversely proportional to the area of a MOS transistor (1/(W*L)): Thus: Density0.13 = 1,480 * Density5 !!!

    Capture Design Description

    Uses HDL and/or Schematic

    VLSI Design Flow


    Logic Simulation Initial Fabrication

    Design Iteration

    Behavioural Simulation Yes Yes Results OK? No Results OK? No


    Design Iteration

    Test and Evaluation

    Library Cells

    Generate Layout

    Design Iteration

    No

    Results OK?

    Yes

    Synthesize Logic
    Design Iteration
    Insert Standard Cells and Custom Cells

    Post-Layout Simulation

    Library Cells
    Includes parasitic delays

    Commence Production

    Results OK? No

    Yes

    Design Iteration

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