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6.004 Computation Structures

Spring 2009

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Synchronization, Metastability and Arbitration

Did you vote for Bush or Gore? Didnt have enough time to decide. Well, which hole did you punch? Both, but not very hard...

The Importance of being Discrete

We avoid possible errors by disciplines that avoid asking the tough questions using a forbidden zone in both voltage and time dimensions:

Digital Values:
Problem: Distinguishing voltages representing 1 from 0 Solution: Forbidden Zone: avoid using similar voltages for 1 and 0
VOUT VOH VIH

Digital Time:
Problem: Which transition happened rst? questions Solution: Dynamic Discipline: avoid asking such questions in close races
tS D Clk
VIN VOL VIL VIH VOH

"If you can't be just, be arbitrary"

- Wm Burroughs, Naked Lunch
- US Supreme Court 12/00

tH

Due tonight: Lab #2 Lab #1 checko meeting

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VIL VOL

Q tCD tPD

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If we follow these simple rules

Can we guarantee that our system will always work?
In

The world doesnt run on our clock!

What if each button input is an asynchronous 0/1 level?
0 1 B0 B1 Lock U
But what About the Dynamic Discipline?

DQ

In
Combinational logic

DQ

Combinational logic

DQ

Out
Combinational logic

DQ

Out

0 1

Clk

Combinational logic

DQ

Combinational logic

DQ

Combinational logic

DQ

Out

To build a system with asynchronous inputs, we have to break the rules: we cannot guarantee that setup and hold time requirements are met at the inputs! So, lets use a synchronizer at each input:
Valid except for brief periods following active clock edges

With careful design we can make sure that the dynamic discipline is obeyed everywhere*...
* well, almost everywhere...

0 1

U(t) (Unsynchronized) Synchronizer

S(t) (Synchronized)

Which edge Came FIRST?

Clock
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The Asynchronous Arbiter:

a classic problem
UNSOLVABLE
B: C: at tB at tC B C Arbiter S

Violating the Forbidden Zone

B: at tB at tC B C Arbiter S C:

For NO nite value of tE and tD is this spec realizable, even with reliable components!
Arbiter Output

Issue: Mapping the continuous variable (tB tC) onto the discrete variable S in bounded time.
With no forbidden zone, all inputs have to be mapped to a valid output. As the input approaches discontinuities in the mapping, it takes longer to determine the answer. Given a particular time bound, you can nd an input that wont be mapped to a valid output within the allotted time.

Arbiter specications: nite tD (decision time) nite tE (allowable error) value of S at time tC+tD: 1 if tB < tC tE 0 if tB > tC + tE 0, 1 otherwise

B: C: S:

>tE tD

>tE tD tD

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o
CASE 1 CASE 2 CASE 3
B Earlier
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(tB=tC )

C Earlier

tB-tC

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Unsolvable?
that cant be true... Lets just use a D Flip Flop:
B: C: at tB at tC D Q
DECISION TIME is TPD of op. ALLOWABLE ERROR is max(tSETUP, tHOLD) Our logic: TPD after TC, well have Q=0 i tB + tSETUP < tC Q=1 i tC + tHOLD < tB Q=0 or 1 otherwise.

The Mysterious Metastable State

Vin
0 1

Vout

Q Y

Vout

VTC of closed latch

Latched in a 1 state

Were lured by the digital abstraction into assuming that Q must be either 1 or 0. But lets look at the input latch in the ip op when B and C change at about the same time...
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Recall that the latch output is the solution to two simultaneous constraints:
D G Q

Latched in an undefined state

VTC of feedback path (Vin=Vout)

D G

1. The VTC of path thru MUX; and 2. Vin = Vout

Latched in a 0 state

master

slave

Vin

In addition to our expected stable solutions, we nd an unstable equilibrium in the forbidden zone called the Metastable State
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Metastable State: Properties

1. It corresponds to an invalid logic level the switching threshold of the device. 2. Its an unstable equilibrium; a small perturbation will cause it to accelerate toward a stable 0 or 1. 3. It will settle to a valid 0 or 1... eventually. 4. BUT depending on how close it is to the Vin=Vout xed point of the device it may take arbitrarily long to settle out. 5. EVERY bistable system exhibits at least one metastable state!
EVERY bistable system? Yep, every last one. Coin ip?? Could land on edge. Horse race?? Photo nish. Presidential Election?? (Wheres this twit been hiding???)
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Observed Behavior:
typical metastable symptoms
Following a clock edge on an asynchronous input:

CLK D
We may see exponentially-distributed metastable intervals:

Q
Or periods of high-frequency oscillation (if the feedback path is long):

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Mechanical Metastability
If we launch a ball up a hill we expect one of 3 possible outcomes:
State A State B

How do balls relate to digital logic?

Our hill is analogous to the derivative of the VTC (Voltage Transfer Curve) at the metastable point, the derivative (slope) is ZERO. Notice that the higher the gain thru the transition region, the steeper the peak of the hill... making it harder to get into a metastable state We can decrease the probability of getting into the metastable state, but assuming continuous models of physics we cant eliminate the slope=0 point!
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Vout

Metastable State

a) Goes over b) Rolls back c) Stalls at the apex That last outcome is not stable. - a gust of wind - Brownian motion - it doesnt take much
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Vout Vin

State A

State B

Vin

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The Metastable State:

Why is it an inevitable risk of synchronization?
Our active devices always have a xed-point voltage, VM, such that VIN=VM implies VOUT = VM Violation of dynamic discipline puts our feedback loop at some voltage V0 near VM The rate at which V progresses toward a stable 0 or 1 value is proportional to (V - VM) The time to settle to a stable value depends on (V0 - VM); its theoretically innite for V0 = VM Since theres no lower bound on (V0 - VM), theres no upper bound on the settling time. Noise, uncertainty complicate analysis (but dont help).

Sketch of analysis I.
Assume asynchronous 0->1 at TA, clock period CP: Whats the FF output voltage, V0, immediately after TA?
0 1 A Synchronizer C Clock S(t) (Synchronized)

Potential trouble comes when V0 is near the metastable point, VM V0 VM

1. Whats the probability that the voltage, V0, immediately after TA is within of VM? tA-tC
< tS+tH CP

P[ V 0 VM
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(tS + tH ) 2 CP (VH VL )
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Sketch of analysis II.

Vout

Failure Probabilities vs Delay

Slope = A
Vin

Vin

0
A

1
C

Vout

We can model our combinational cycle as an amplier with gain A and saturation at VH, VL

VH

Making conservative assumptions about the distribution of V0 and system time constants, and assuming a 100 MHz clock frequency, we get results like the following: Average time Delay P(Metastable) between failures 31 ns 33.2 ns 3x10-16 3x10-17 10-45 1 year 10 years 1030 years!

VL e t(A-1)/RC e t/ (T) (VH VM) e -T/

2. For Vout near VM, Vout(t) is an exponential whose time constant reects RC/A: 3. Given interval T, we can compute a minimum value of = |V0-VM| that will guarantee validity after T: 4. Probability of metastability after T is computed by probability of a V0 yielding (T)
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Vout(t)- VM

100 ns

[For comparision: Age of oldest hominid fossil: 5x106 years Age of earth: 5x109 years]

PM(T) P[|V0-VM| < (T)]

K e -T/
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Lesson: Allowing a bit of settling time is an easy way to avoid metastable states in practice!
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The Metastable State:

a brief history

Ancient Metastability
Metastability is the occurrence of a persistent invalid output an unstable equilibria.

Antiquity: Early recognition

Buridens Ass, and other fables The idea of Metastability is not new:

Denial: Early 70s

Widespread disbelief. Early analyses documenting inevitability of problem rejected by skeptical journal editors.

The Paradox of Buridans Ass Buridan, Jean (1300-58), French Scholastic philosopher, who held a theory of determinism, contending that the will must choose the greater good. Born in Bethune, he was educated at the University of Paris, where he studied with the English Scholastic philosopher William of Ockham (whom you might recall from his razor business). After his studies were completed, he was appointed professor of philosophy, and later rector, at the same university. Buridan is traditionally, but probably incorrectly, associated with a philosophical dilemma of moral choice called "Buridan's ass. In the problem an ass starves to death between two alluring bundles of hay because it does not have the will to decide which one to eat.

Folk Cures: 70s-80s

Popular pastime: Concoct a Cure for the problem of synchronization failure. Commercial synchronizer products. Acceptance of the reality: synchronization takes time. Interesting special case solutions.
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Reconciliation: 80s-90s

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Folk Cures
the perpetual motion machine of digital logic Bad Idea # 1: Detect metastable state & Fix
Async Input "Clean" Output

Theres no easy solution

so, embrace the confusion.

"Metastable States":
Bug: detecting metastability is itself subject to metastable states, i.e., the xer will fail to resolve the problem in bounded time.

FF

"FIXER"

Inescapable consequence of bistable systems Eventually a metastable state will resolve itself to valid binary level. However, the recovery time is UNBOUNDED ... but inuenced by parameters (gain, noise, etc) Probability of a metastable state falls o EXPONENTIALLY with time -- modest delay after state change can make it very unlikely. Our STRATEGY; since we cant eliminate metastability, we will do the best we can to keep it from contaminating our designs

delay

Bad Idea #2: Dene the problem away by making metastable point a valid output
valid "0"
The ima ge can not

valid "1"

The ima ge can not

Bug: the memory element will ip some valid 0 inputs to 1 after a while. Many other bad ideas involving noise injection, strange analog circuitry, have been proposed.
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The ima ge can not

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Modern Reconciliation:
delay buys reliability
A metastable state here will probably resolve itself to a valid level before it gets into my circuit.

Things we CANT build

1. Bounded-time Asynchronous Arbiter:
B C S=0 i B edge rst, 1 i C edge rst, 1 or 0 if nearly coincident

Synchronizers, extra ip ops between the asynchronous input and your logic, are the best insurance against metastable states. The higher the clock rate, the more synchronizers should be considered.

Arbiter

S valid after tpd following (either) edge

In

DQ

DQ

Combinational logic

DQ

Out

2. Bounded-time Synchronizer:
Asynchronous Input
D Q

Clk

Output = D at active clock edge, either 1 or 0 i D invalid near clock edge

And one here will almost certainly get resolved.

Q valid after tpd following active clock edge

SETTLING TIME
Cures Metastability!
In

3. Bounded-time Analog Comparator:

DQ DQ DQ
Combinational logic

DQ

Out

Clk

Continuous Variable

> 3.14159 ?

0 or 1, nite tpd

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Some things we CAN build

1. Unbounded-time Asynchronous Arbiter:
B C

Interesting Special Case Hacks

Predictive periodic synchronization:
Data1 CLK2 CLK1 Data2 Exploits fact that, given 2 periodic clocks, close calls are predictable. Predicts, and solves in advance, arbitration problems (thus eliminating cost of delay) For systems with unsynchronized clocks of same nominal frequency. Data goes to two ops clocked a half period apart; one output is bound to be clean. An observer circuit monitors the slowly-varying phase relationship between the clocks, and selects the clean output via a lenient MUX.

Arbiter Done

S valid when Done=1; unbounded time.

S=0 i B edge rst, 1 i C edge rst, 1 or 0 if nearly coincident

2. Unbounded-time Analog Comparator:

Continuous Variable

> 3.14159 ?
Done

0 or 1

After arbitrary interval, decides whether input at time of last active clock edge was above/below threshold.

Mesochronous communication:
Data1 CLK2 Data2 delay

3. Bounded-time combinational logic:

Produce an output transition within a xed propagation delay of rst (or second) transition on the input.

CLK1 CLK2

Constraints on clock timing periodicity, etc can often be used to hide time overhead associated with synchronization.
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Every-day Metastability - I
GIVEN:
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Every-day Metastability - II
Normal trac light: GREEN, YELLOW, RED sequence 55 MPH Speed Limit Suciently long YELLOW, GREEN periods Analog POSITION input digital RED, YELLOW, GREEN inputs digital GO output

Ben Bitdiddle tries the famous 6.004 defense: Ben leaves the Bit Bucket Caf and approaches fork in the road. He hits the barrier in the middle of the fork, later explaining I cant be expected to decide which fork to take in bounded time!. Is the accident Bens fault?
Yes; he should have stopped until his decision was made. Judge R. B. Trator, MIT 86

Can one reliably obey....

Image by MIT OpenCourseWare.

Bit Bucket Cafe

LAW #1: DONT CROSS LINE while light is RED. GO = GREEN LAW #2: DONT BE IN INTERSECTION while light is RED.

PLAUSIBLE STRATEGIES:
A. Move at 55. At calculated distance D from light, sample color (using an unbounded-time synchronizer). GO ONLY WHEN stable GREEN. B. Stop 1 foot before intersection. On positive GREEN transition, gun it.
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Summary
The most dicult decisions are those that matter the least.
As a system designer Avoid the problem altogether, where possible
Use single clock, obey dynamic discipline Avoid state. Combinational logic has no metastable states!

Delay after sampling asynchronous inputs: a fundamental cost of synchronization

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