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GATE DRIVERS
THE POWER MANAGEMENT LEADER

By Chris Chey and John Parry, International Rectifier
Managing Transients in Control IC Driven Power Stages

tracks are lumped together and arbitrarily labeled LS1,2 and LD1,2. Further parasitics will exist in the gate drive circuit and these should also be considered during circuit layout but for now, we will focus on the bridge itself as the highest currents and di/dt will occur here. During switching, rapidly changing bridge current induces voltage transients across all parasitics shown. Left unchecked, these transients may couple into other circuits causing noise problems, increased switch dissipation or even IC damage in extreme cases.
1. CONTROL IC PRODUCT RANGE

International Rectifier offers a broad range of control ICs from single channel to complete three-phase bridge drivers. All types employ high-integrity level shifting techniques to simplify control of power transistors from logic circuits. Our latest products further enhance this capability to drive power switches relatively displaced by up to 1200V. As leading edge performance demands switching more current at ever higher speeds, the unwanted effects of parasitics are magnified and warrant heightened attention. The aim here is to locate their source, quantify the immunity of the IC against a potentially troublesome effect and finally, show how to maximize the margin between the two.
3. VS UNDERSHOOT: CAUSE
Of the problems caused by parasitics, one of the main issues for control ICs is a tendency for the VS node to undershoot ground following switching events. Conversely, overshoot does not generally cause a problem due to the high differential voltage capability of International Rectifiers proven HVIC process. With inductive loading of the bridge, high side transistor turn-off causes load current to suddenly flow in the low side free-wheeling diode. On top of the slack from diode
2. PARASITIC ELEMENTS OF THE BRIDGE CIRCUIT

The circuit shown in figure 1 depicts a typical application in which two power MOSFETs are driven by a control IC in a half bridge configuration. Unwanted inductance in the power circuit from die bonding in the transistors, pinning and PCB
For more information in North America call +1 310 252 7105, in Europe call +49 6102 884 311, or visit us at www.irf.com
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turn-on delay and forward voltage drop, stray inductance LS1+LD1 contribute to undershoot of the Vs node beyondground, as shown in the graph of figure 1. If the load circuit does not totally self-commutate in the dead-time (both transistors off) VS undershoot or ringing may occur when the low side device is hard switched.
4. VS UNDERSHOOT: EFFECTS ON THE CONTROL IC

International Rectifier control ICs are guaranteed completely immune to VS undershoot of at least 5V, measured with respect to COM. If undershoot exceeds this level, the high side output will temporarily latch in its current state. Provided VS remains within absolute maximum limits the IC will not suffer damage, however the high-side output buffer will not respond to input transitions while undershoot persists beyond 5V. This mode should be noted but proves trivial in most applications, as the high-side is not usually required to change state immediately following a switching event.
5. AVOIDING LATCH-UP
The parasitic diode structure for a typical control IC is shown in appendix 1. - As with any CMOS device, driving any of these diodes into forward conduction or reverse breakdown may cause parasitic SCR latch-up. The ultimate outcome of latchup often defies prediction and can range from temporary erratic operation to total device failure.
The control IC may also be damaged indirectly by a chain of events following initial overstress. By way of example, latchup could conceivably result in both output drivers assuming a high state, causing cross-conduction followed by switch failure and finally catastrophic damage to the IC. This failure mode should be considered a possible root cause if power transistors and/or control IC are destroyed in the application. The following theoretical extremes can be used to help explain the relationship between excessive VS undershoot and the resulting latch-up mechanism. In the first case an ideal bootstrap circuit is used in which VCC is driven from a zero-ohm supply with an ideal diode feeding VB. Undershoot now sums with Vcc causing the bootstrap capacitor to overcharge as shown in figure 2. By way of example, if VCC =15V then VS undershoot in excess of 10V forces the floating supply above 25V, risking breakdown in diode D1 and subsequent latchup. Suppose now that the bootstrap supply is replaced with the ideal floating supply of figure 3 such that VBS is fixed under all circumstances. Note that using a low impedance auxiliary supply in place of a bootstrap circuit can approach this situation. This time, latch-up risk appears if VS undershoot exceeds VBS, since parasitic diode D2 will ultimately enter conduction. A practical circuit is likely to fall somewhere between these two extremes, resulting in both a small increase of VBS and some VB droop below VCC as depicted by Figure 4. Exactly which of the two extremes is prevalent can be checked as follows.
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For more information in North America call +1 310 252 7105, in Europe cal l +49 6102 884 311, or visit us at www.irf.com
6. MONITOR AND VERIFY

The signals listed below should be observed both in normal operation and during high-stress events such as short circuit or over current shutdown, when di/dt is highest. Readings should always be taken directly across IC pins as shown in figure 5, so that contributions from parasitics in the drive coupling are included in the measurement. Measurements to verify undershoot severity (1) High side offset with respect to common; VS- COM (2) The floating supply; VB - VS Most bridge circuits employ a bus of several hundred volts
which means selecting an insensitive Y-axis scale to prevent distortion from saturation of the input amplifier. This can make the comparatively small Vs undershoot difficult to quantify. For best resolution, check your oscilloscope manual and then select the highest useable sensitivity level. For the second measurement, the signal of interest is permanently superimposed on the changing bridge voltage. The oscilloscope may be floated with a transformer, but this method is discouraged because capacitive loading can alter circuit performance and sometimes mask underlying problems by inadvertently reducing dv/dt. A high-bandwidth differential voltage probe (or an isolated differential-input oscilloscope) can give good results here, allowing other ground referenced signals to be viewed at the
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same time. However, be aware of propagation delay mismatch between differential and conventional probes when comparing relative event times. Always measure the noise floor prior to making measurements. Common-mode noise on high side referenced signals (Vb,HO) can be observed by joining probe tip and ground lead directly to the Vs node. Do not assume that low-side referenced signals are free from common-mode noise. Measure the noise floor by joining probe tip and ground lead together at the COM node. this capacitor supports both the low-side output buffer and bootstrap recharge, we recommend a value at least ten times higher than Cb. 3c. Connect decoupling capacitors directly across appropriate pins as shown in figure 7. 3d. If a resistor is needed in series with the bootstrap di ode, verify that VB does not fall below COM, especially during start-up and extremes of frequency and duty cycle. Granted proper application of the above guidelines, the effects of VS undershoot will be minimized at source. If the level of undershoot is still considered too high, then some reduction of dv/dt may be necessary. External snubbing and/or increasing gate drive resistance may be used to trade efficiency for lower switching rate. If the system will not tolerate this, then fast anti-parallel clamping diodes may be considered appropriate. HEXFRED diodes are ideal for this purpose.
7. GENERAL RECOMMENDATIONS
The following guidelines represent good practice in control IC circuits and warrant attention regardless of the observed latch-up safety margin. Design tip DT94-15 Design Check List for IR21xx MGDs may be consulted for pictorial representation of the suggestions listed below. Minimize the parasitics of figure 1 1a. Use thick, direct tracks between switches with no loops or deviation. 1b. Avoid interconnect links. These can add significant in ductance. 1c. Reduce the effect of lead-inductance by lowering pack age height above the PCB. 1d. Consider co-locating both power switches to reduce track lengths. Reduce control IC exposure. 2a. Connect VS and COM as shown in figure 6. 2b. Minimize parasitics in the gate drive circuit by using short, direct tracks. 2c. Locate the control IC as close as possible to the power switches. Improve local decoupling. 3a. Increase the bootstrap capacitor (Cb) value using at least one low-ESR capacitor. This will reduce overcharging from severe Vs undershoot. See Design Tip DT98-2 for more information. 3b. Use a second low-ESR capacitor from Vcc to COM. As
8. BOOSTING VS UNDERSHOOT IMMUNITY.

If the key signals measured fall within specified limits under worst case conditions, then no further action should be necessary. However, in very noisy environments, where Vs undershoot remains excessive despite the measures above, then further steps may be taken to increase control IC tolerance. We recommend two different methods for improving undershoot immunity.
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Method B: By way of an alternative approach, we also recommend the insertion of a single resistor between COM and the low side source or emitter as depicted by figure 9. Since the boot strap capacitor is not charged through the resistor, this method grants flexibility to choose a higher resistance and afford greater protection to the control IC. A resistor in this location has the effect of limiting peak cur rent flow in the 600V diode D2 shown in figure 3. Again, drive symmetry requires that the total resistance in both gate drive circuits be equal, so the low-side gate resistor should be slightly reduced to accomplish this.
Method A: A resistor between the VS pin and the bridge center may be used to limit the current flow into the Vs pin during un dershoot. This method is viable for resistor values of around 5 Ohms or less. Since the bootstrap capacitor charges through this resistor, as shown in figure 8, inadvertent shootthrough may occur at start-up if the value is too high. If there is a series gate resistor, this should be reduced in value so the nett gate resistance of both high and low side transistors remains equal.
Note: When using control ICs which do not have a separate logic ground, i.e. those which share COM for both input and out put ground references, either of the two methods discussed may be applied. However, care should be taken to ensure that logic inputs fall within the permitted levels.
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Managing Transients in Control IC Driven Power Stages 9. APPENDIX 1.

IR2110 PARASITIC DIODE STRUCTURE The parasitic diode structure of the IR2110 control IC is shown in Figure 10. This is, in essence, a pictorial representation of our Absolute Maximum Ratings table. The IR2110 has separate logic and output supply rails, however, these rails are combined in some control IC types due to pinning restrictions. Further details on the parasitic diode structure and latchup mechanism may be found in design tip DT94-9, Maximizing Latch Immunity of the IR2151 and IR2152 In Ballast Applications.
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GATE DRIVERS

THE POWER MANAGEMENT LEADER

Managing Transients in Control IC Driven Power Stages

1. CONTROL IC PRODUCT RANGE

2. PARASITIC ELEMENTS OF THE BRIDGE CIRCUIT

Managing Transients in Control IC Driven Power Stages

4. VS UNDERSHOOT: EFFECTS ON THE CONTROL IC

Managing Transients in Control IC Driven Power Stages

6. MONITOR AND VERIFY

Managing Transients in Control IC Driven Power Stages

8. BOOSTING VS UNDERSHOOT IMMUNITY.

Managing Transients in Control IC Driven Power Stages

Managing Transients in Control IC Driven Power Stages 9. APPENDIX 1.

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