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Circuit controls microneedle etching

Stephen Woodward, Marine Sciences, Chapel Hill, NC

t its invention roughly two decades ago, STM (scanning tunneling microscopy) created a sensation because it was the first technology to make atomic-scale-resolution imaging a routine procedure. An essential requirement for the practical application of STM is some means for the reproducible fabrication of supersharp, atomic-scale needle tips. One way to make the tips is to etch them from short pieces of platinum wire in a calcium-chloride electrolyte bath. Applying an ac voltage between the electrolyte and the wire generates a chemical reaction accompanied by vigorous fizzing at the surface of the liquid. This reaction etches the platinum, causing the wire to neck down and eventually break into two
60 Hz AC FROM VARIAC OUT/IN

pieces. If the etching current turns off within milliseconds of the wires breaking, then the point of separation remains supersharp. This sharp point is suitable for use as a high-quality STM tip. Swift interruption of the current, however, is essential to tip sharpness, because only a few milliseconds of overetch suffice to dull and ruin the tip. The circuit in Figure 1 achieves precision etch-termination by using relay-actuated etch turnoff based on the sudden drop in etch current that occurs when the wire parts. Precision sensing and full-wave rectification of the etch current is critical to circuit operation; the circuit achieves this precision by using an unusual differential-input rectifier.

Precision, full-wave rectification of low-level ac signals to a dc format is a common signal-processing function; many classic rectifier topologies accomCircuit controls microneedle etching......................................87 Circuit removes relay-contact bounce ....................................88 Log-ratio amplifier has six-decade dynamic range ..........................90 VCXO makes inexpensive dual-clock reference ......................................92
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4 1N4004 FULL-WAVE PRECISION RECTIFIER RELAY: RS275-248 15V 12V AC + START STOP 470 F 25V G 1N914 820 Q3 2N4401 5.6k 7 12V COMPARATOR 10k* Q2 2N3906 14 D2 C1 47 F 10V + 10k 1N914 100k 100k* 0.22 F 0.39 F 390k 3 + 11 NOTES: 1 ALL OP-AMPS ARE 4 LM324s. * = 1% METAL FILM. RUN + FILTER 2 4 IC1C 1 10-TURN + DIAL 5 6 10k IC1D THRESHOLD SET: 0 TO 100 7812 O 120V AC

~40 mA

1N914

Figure 1

9 IC1A 10 + R2 453* 12V + 100 F C2 6V 13 3k 12 IC1B + 8

D1 Q1 2N3906

0.3 5W R1

ETCH CURRENT

This etch-control circuit produces supersharp microneedles by terminating the etching process at precisely the right time. www.edn.com November 27, 2003 | edn 87

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put. Amplifier IC1B responds with a negative output excursion, forcing transistor Q2 to conduct sufficiently to cause the inverting input of IC1A and the bottom end of R1 to track. Q2s emitter current, and, therefore, collector current is then I VIN/R2 VR1/R2; Q2 is a high-alpha transistor. The respective roles of the amplifiers reverse for input excursions of the opposite polarity, with D2 and Q2 conducting. The match of Q1 and Q2 alpha values, which is typically 0.3% or better, is the only limit on rectification symmetry. This precision rectifier is therefore unique in that neither rectification symmetry nor common-mode rejection, which exceeds 60 dB, depends on resistor matching. Meanwhile, C2 affords ac coupling, which eliminates offset-voltage-related errors. Operation of the rest of the etch controller is straightforward. IC1C implements a unity-gain, two-pole Butterworth lowpass filter for good ripple attenuation without excessive time delay. Etching begins when you push the Start pushbutton. The etch-current comparator, IC1D, then drives Q3 to keep the relay energized until the etch current drops below the level set by the Threshold Set potentiometer. IC1Ds output then drops low, turning Q3 off, opening the relay, and terminating the etch. The result is a serviceable, atomically sharp scan tip almost every time.

plish this function. But the accuracy of typical precision rectifiers depends on the precise matching of resistor ratios. Moreover, op-amp input-offset voltages limit the accuracy of these standard circuits. The offset error generally limits sensitivity to input spans no smaller than some hundreds of millivolts. The converter in this design avoids these faults and adds a number of new and useful features. The differential ac signal to be rectified goes to the noninverting inputs of op amps IC1A and IC1B (Figure 1). Rectification proceeds as follows: Consider a signal excursion,VIN, that drives IC1As input more positive than IC1Bs. Amplifier IC1A responds by driving diode D1 into conduction, thereby forcing R2 to track the in-

Circuit removes relay-contact bounce

John Guy, Maxim Integrated Products, Sunnyvale, CA
drives the relay closed, and that relay closure connects the input of the hot-swap circuitry to the power supply: 28V, in this 10V/DIV case. The hot-swap controller, IC1, keeps the p-channel MOSFET, Q1, off for a minimum of 150 msec after the input supply reaches a valid level. Q1 FROM That delay allows ample time TO SYSTEM MTD20P06 K1 POWER SUPPLY POWER LOAD for contact bounce in the re4 28V 5A/DIV 3 lay to subside. After the 150OUT 100 SEC/DIV 1 msec delay, IC1 drives 2 The mechanical relay, K1, by Figure 2 the MOSFET gate such itself exhibits contact bounce that the output voltage slews on closure as shown. R1 DRIVE 1 2 3 at 9V/msec. This controlled CIRCUIT 100k VS GATE DRAIN ramp rate minimizes the in6 rush current, thereby reducON 5 PGOOD ing stress on the power sup4 GND ply, the relay, and capacitors IC1 Figure 1 downstream from the hotMAX5902 10V/DIV swap controller. GND GND An example of relay contact bounce shows three A hot-swap controller IC and external MOSFET removes conbounces with an inrush-curtact bounce from relay K1. rent peak of almost 30A relays, however, can prove troublesome to (Figure 2). The top trace is output volt- 500 mA/DIV 1 mSEC/DIV downstream circuitry. One approach to age at 10V/division, the lower trace is incontact bounce combines a relay with a put current at 5A/division, and the The Figure 1 circuit removes Figure 3 hot-swap controller. Such controllers are output load is 54 in parallel with relay-contact bounce and increasingly popular as the means for 100 F. Use of the Figure 1 circuit under reduces inrush current. switching system components without these conditions yields a better picture shutting down the system power. In Fig- (Figure 3). The delayed rise in output current shows much less variation, peakure 1, a relay contact replaces the pin of voltage is clearly visible, with no hiccups ing under 1.5A before settling to a steadya mechanical connector. The drive circuit arising from contact bounce. The input state value of 500 mA.

dvances in semiconductor technology have allowed ICs to replace many mechanical relays, but relays still dominate in high-current circuits that must stand off high voltages of arbitrary polarity. Contact bounce in those

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voltage or current; polarity; and scaling; or operations such as log products and ratios. Log-ratio amplifiers find applications in wide-dynamic-range ratiometric measurements, which measure an unknown signal against a variable-current reference. The transfer function of the circuit in Figure 1 is: put range of the ADC sets the 4-mA fullscale input-current range. Programming IREF to a value of 40 to 600 A places the output in the middle of the measurement range. The components give an output-scale factor of 1. This circuit has an output defined over a range of 4.5 decades of signal current, IIN, and 1.5 decades of reference current, IREF (limited by the loaddriving capability of the reference for a total six-decade range. For most applications, you would use only a portion of the entire six-decade range. By determining the range of the expected input signals and computing their ratios, you can use the equations to predict the expected output-voltage range. You can assign IREF and IIN to match device performance to the current range, but you should observe polarity. A log amplifier generally depends on the nonlinear transfer function of a transistor. The general transfer function of a log amplifier is related to IS and VT, which both depend on temperature. IS is the

Log-ratio amplifier has six-decade dynamic range

Reza Moghimi, Analog Devices, San Jose, CA

ou need optical-power monitoring to guarantee overall system performance in fiber-optic communication systems. Logarithmic-signal processing can maintain precise measurements over a wide dynamic range. The wide-dynamic-range signal undergoes compression, and the use of a lower resolution measurement system then saves cost. As an example of this technique, consider a photodiode with responsivity of 0.5A/W that converts light energy to a current of 100 nA to 1 mA. With a fourdecade dynamic range and 1% error, the required measurement resolution is 0.01 10 4, or 1 ppm. This measurement requires a 20-bit ADC. Instead, you can compress this input to a 0 to 4V range using a log-ratio amplifier and then use a 10-bit ADC, substantially reducing the system cost. Programming the reference current allows shifting the output voltage to the desired level. You can customize and use the circuit in Figure 1 in applications involving unusual combinations of dynamic range; input signal, such as
50-k9 33-TURN DIGITAL AD5201 POTENTIOMETER DIGITAL TRIM FROM 3600 TO 50,000 VCC

where K is the output scale factor, IIN is the current that the photodiode generates, VT is a temperature-dependent term (typically, 26 mV at 25 C and proportional to absolute temperature), and IREF is the reference current. VOUT 0 when IIN IREF. For proper operation, IIN/IREF should always be greater than 0. The output of the log-ratio circuit can be positive, negative, or bipolar, depending on the ratio of IIN/IREF. The 4V full-scale in-

5V VCC 1 C1

330 pF MAT02/AD C2 7 2 2 B1 3 E1 B2 6 E2 5 1 V V+ + 3 LARGE-AREA PHOTODIODE IIN

2 VS 3 SLEEP OUT 6 A 3600 AD5201 W B IREF

1/2 AD8626 V+ V 1

GND 4 REF191 2.048V REFERENCE

CS SDI CLK SHDN

VEE 5V 330 pF

R3 2.2k

1/2 AD8626

R1(T) 1k TEMPERATURE COMPENSATED

R2 15.7k

VCC

10 F

1 F BAND-WIRE SERIAL INTERFACE

VRE VIN

VD SCL MICROPROCESSOR

AD7810 DOU VIN

Figure 1
This circuit is a programmable, temperature-compensated log-ratio amplifier.

AGN

CONV

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4V

ideas
3V

Figure 2
3V

Figure 3
2V

IREF=570 A, IIN=100 nA TO 4 mA. 2V 1V

IREF=40 A; IIN=100 nA TO 4 mA.

1V 10 30 V (V65:OUT)

100

300 I (R86)/ I (V43)

1k

3k

10k

0V 1 3 V (V65:OUT)

10

30 I (R86)/ I (V43)

100k

300k

1k

VOUT has IREF programmed to full scale of 570 A.

VOUT has IREF programmed to zero scale of 40 A.

transistors collector saturation current, and VT is the transistors thermal voltage. To overcome this temperature dependency, this design uses a matched pair of MAT02 transistors to cancel the IS temperature drift and a temperaturesensitive resistive voltage divider to compensate for the temperature coefficient of VT. The heart of the IREF generator is a REF191. You adjust its output with an AD5201 digital potentiometer. This modification allows you to program the

reference current in 33 steps, from 40 to 600 A. The combination of the REF191 and the AD5201 provides a current source that is stable with respect to time and temperature. For higher resolution, you can use the 1024-position AD5231. The AD8626 is a dual precision-JFET-input amplifier with true single-supply operation to 26V, low power consumption, and rail-to-rail output swing, allowing a wide dynamic range. Its output is stable with

capacitive loads in excess of 500 pF. Figures 2 and 3 show the transfer function of the log-ratio amplifier at the input of the ADC. The output is limited to 0 to 4V to match the unipolar input-voltage range of the AD7810 ADC. Reference 1. Sheingold, Dan, Editor, Nonlinear Circuits Handbook, Analog Devices, ISBN: 0-916550-01-X.

VCXO makes inexpensive dual-clock reference

Said Jackson, Equator Technologies Inc, Campbell, CA
his Design Idea describes an inexpensive circuit to generate two extremely high-quality, crystal-clockreference-signals, one of which is a PWM-controlled VCXO (voltage-controlled crystal oscillator) clock signal (Figure 1). The design also includes circuitry to statically switch and hold the VCXO at its nominal fixed frequency of operation (equivalent to 50% PWM) without requiring any external PWM stimulus. Most digital audio/video microprocessor-based systems today require several independent clocks with low jitter and the potential adjustability a VCXO provides. The described circuit replaces two expensive monolithic VCXO and crystal oscillators at a fraction of their cost and provides much higher quality output signals than the monolithic solutions can generate, especially at the control limits of the VCXO ( 100% deviation). The circuit generates signals with higher stability, much lower jitter, lower operating voltage (3.3 versus 5V)

and a wider VCXO pull range than comparable monolithic approaches at less than one-third of their cost. You can use the circuit in a wide variety of applications; the indicated component values make it a perfect fit for a digital audio/video system, such as a digital video recorder, digital camera, or settop box. The circuit is well-suited to single-chip, media-processing applications that require adjustability, low cost, and low-jitter performance, such as systems based on Equators (www.equator.com) broadband-signal processors. These types of systems generally require a fixed frequency, such as 25 or 33 MHz, for the processor subsystem (Ethernet, PCI bus, for example) and an adjustable 27-MHz reference clock for the audio/video reference subsystem. A PLL system generally controls the 27-MHz reference clock. (This PLL is usually implemented in software with PWM outputs from the microprocessor controlling the 27-MHz clocks deviation.) This approach guar-

antees a correct synchronization of the audio and the video data streams to each other and the broadcast source. The clock requires 50-ppm adjustability, and the circuit in Figure 1 provides more than 70 ppm. The circuit suits high-volume manufacturing, the highest quality signal (lowest jitter), and the lowest production cost. The design incorporates several novel circuit features, such as both overtoneand harmonic-crystal operation, use of inexpensive voltage-controlled capacitors (varactor diodes), a single 3.3V powersupply operating voltage, and a selectable 50%-duty-cycle, 27-MHz-operation, fixed-frequency mode. The fixed-frequency mode allows operation at 27 MHz without the PLL-PWM circuits having to provide a 50% duty cycle, potentially freeing up hardware and software resources in the microprocessor that usually generates the PWM signal. This mode is usually invoked when the audio/video signals are generated internalwww.edn.com

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C3 10 pF R3 560 1 2 C1 1000 pF EPCOS B82494-A1472-K L1 47 H AUDIO/VIDEO VCXO R5 1M R6 56 REF_27 MHz

32-MHz, THIRD-OVERTONE FOXSD/320-20 Y1 1 2 C2 10 pF

R1 1M

IC3B 74LVC04

IC1A 74LVC04

IC1B 74LVC04

REF_32 MHz 3.3V

IC3A 74LVC04

R7 560

TSSOP14 74LVC00APWDH 5 6 4 IC2B

TSSOP14 74LVC00APWDH 32 MHz 2 3 1 IC2A 14 C4 22 F 10V 14 IC2D 11

R4 3.3 Y2 1 R8 3.3k C8 0.01 F R9 3.3k C9 1 F

20-PPM, 18 pF-LOAD, 27-MHz CRYSTAL SMD CITIZEN HCM49-27.000MDDUT 2

Figure 1

14 C5 0.1 F

14 9 10 IC2C

PWM SIGNAL

CONTROL VOLTAGE C6 R10 0.01 F 47k D1 BB133 PHILIPS R11 47k C11 0.01 F D2 BB133 PHILIPS C7 0.01 F

TSSOP14 74LVC00APWDH

FIXED_VS_ VCXO_SELECT

12 13

PWM_INPUT PWM FROM PLL PHASE COMPARATOR

TSSOP14 74LVC00APWDH PWM MULTIPLEXER

C10 3.3 pF

This circuit, ideal for A/V applications, generates two high-quality clock-reference signals.

ly to the system, such as when playing back from a hard drive, and audio/video synchronization to an external source is unnecessary. The circuit includes IC1, a 32-MHz, PCI-based fixed-frequency reference clock; IC2, a PWM multiplexer; and IC3, a 27-MHz VCXO clock. A Fox (www.fox online.com) 32-MHz, third-overtone crystal serves to generate both the PCI reference clock and the 50%-duty-cycle reference for the fixed-frequency mode. A third-overtone, 32-MHz part is less expensive and more mechanically robust than a 33-MHz, fundamental-mode crystal at the expense of running the PCI clock slightly slower. The tank circuit around inductor L1 and capacitors C1 and C3 prevent the crystal from oscillating at its fundamental mode of approximately 11 MHz. This tank circuit works by creating an LC series-resonant circuit between L1 and C3 that has natural resonance at approximately 24 MHz, which is approximately 75% of the desired 32MHz frequency. Note that C1 is large enough to have no effect on this tank circuits resonance frequency; it merely acts as a dc blocker for inductor L1. One thing to avoid is to connect this tank circuit to

the input side of inverter IC1A. Connecting it to the input side of IC1A could potentially create a resonant RC circuit with resistor R1 and capacitor C1 acting as the RC components. This circuit could oscillate at less than 1 kHz, a frequency at which L1 would effectively be a short circuit, and crystal Y1 would be an open circuit. Placing C1 and L1 on the output side of IC1A prevents this spurious-oscillation mode. By tuning L1 and C3, you can adjust the circuit to oscillate at a frequency higher than the third overtone. Oscillation at the fifth, seventh, or even ninth overtone is possible and is limited only by the performance of IC1A and the parasitic capacitance. The 32-MHz PCI referenceclock output also serves as a 50%duty-cycle reference for the VCXO when the VCXO is operating in its fixed-frequency, 27-MHz mode. Multiplexer IC2 selects either this 32-MHz, 50% PWM clock signal or the PWM clock signal from a PLL phase comparator (usually implemented in the microprocessor and not shown in the schematic) to set the VCXO to its fixed-frequency mode. The advantage of using the PCI clock for this feature is that traditional circuits would

have to generate an analog one-half-VDD voltage and use an analog multiplexer to set the VCXO at its nominal frequency. Thus, this design avoids the necessity of using accurate and expensive analog circuitry and also generates a reference signal with much higher immunity to temperature, for example, than analog approaches could provide. Digital multiplexer IC2 forwards one of two PWM signals to the VCXO based on the state of the fixed-versus-VCXO selected input signal. The PWM-input signal serves as the PWM reference input to the VCXO if the select pin is high, and the design uses the 50%-duty-cycle PWM signal from the PCI clock circuit if the select pin is low. The design uses a 74LVC00 chip as a multiplexer because of its ready availability and low cost. IC2C buffers the PWM signal, and the cascaded RC filter comprising R8, R9, C8, and C9 then lowpass-filters the signal. The analog-voltage stability of the VCXO control voltage at the output of this RC filter depends on the quality of the VDD supply to IC2C. IC2 receives its 3.3V power through an RC filter: R4 with C4 and C5. IC2 with R8, R9, C8, and C9 thus form a highly accurate D/A converter.
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approximately 27 MHz 2 kHz, which calculates to approximately 74 ppm. The circuit is stable with very low jitter throughout its entire 0 to 100% VCXOadjustment range. You can use the VCXO subcircuit by itself to generate a spreadspectrum clock for EMI compliance. You drive the VCXO voltage or PWM duty cycle from 0V (0%) to 3.3V (100%) with a triangular-shaped drive signal. The frequency of the triangular wave must be below the PWM RC filters cutoff frequency of 24 Hz to be effective. The oscillator circuits jitter depends on the power-supply quality of IC1, IC2, and IC3 and on the noise inside these chips. To avoid crosstalk between 32 MHz and 27 MHz, the design uses two chips. Implementing buffers IC1B and IC3B with separate chips, thus separating the powersupply loading from the sensitive buffers, IC1A and IC3A, could further reduce jitter. With independent clock buffers and a low-noise power supply, this circuit has exhibited a maximum cycle-to-cycle jitter of less than the 60-psec limitation of the HP54720D oscilloscope that measures it. This figure betters the jitter characteristics of popular crystal oscillators and VCXO chips available for consumer applications. It also does not suffer from unstable operation at its adjustment margins (operating at 100% deviation), as designers commonly encounter with monolithic components. Another added benefit is that it achieves its 74ppm adjustment range with only a single 3.3V power supply, whereas monolithic approaches usually require a 5V power supply and control voltage. Finally, it offers all this performance at a total price of less than $1.40 in large quantities by using only commonly available, off-theshelf components. This figure compares to $3 to $6 parts cost with monolithic approaches.

The VCXOs lowpass filter uses a cascaded design, because stray 32-MHz noise could pass across the small parasitic capacitance inherent in R8 into the analog VCXO-control voltage. Cascading also has the advantage of filtering noise with 12 dB of attenuation per octave for frequencies greater than 5 kHz, thus creating a noise-free VCXO control voltage. The 27-MHz audio/video VCXO circuit uses a fundamental-mode crystal that varactor diodes D1 and D2 load with adjustable capacitance. These backbiased diodes junction capacitance depends highly on the bias voltage. Larger bias voltages lower their capacitance, thus lowering the load across the crystal and increasing its oscillation frequency. Diodes D1 and D2 find use in many tuners and are widely available. Capacitors C6 and C7 again function as dc blockers. The adjustment range of the VCXO is

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