CES 2013 Everspin Presentation
CES 2013 Everspin Presentation
CES 2013 Everspin Presentation
8-bit I/O
Part Number Density Congurat|on Temp
MR4A08B 16Mb 2M x 8 C,I,A
MR2A08A 4Mb 512K x 8 C,I
MR0A08B 1Mb 128K x 8 C,I
MR256A08B 256Kb 32K x 8 C,I
MR0D08B 1Mb 128K x 8, 1.8v I/O C
MR256D08 256Kb 32K x 8, 1.8v I/O C
SPI I/O
Part Number Density Congurat|on Temp
MR25H40 4Mb 512K x 8 I, A
MR25H10 1Mb 128K x 8 I, A
MR25H256 256Kb 32K x 8 I, A
Temperatures
Commercial 0 to +70 C
Industrial -40 to +85 C
Extended -40 to +105 C
Automotive -40 to +125 C
5
MRAM Adoption Accelerating
7.0M+
MRAM
Shipments
MRAM
Customers
MRAM
Design Wins
(1)
MRAM
Applications
MRAM
Products
500+ 100+ 100+ 200+
(1)
New Design Wins in CY2012
7M
13M
0
2
4
6
8
10
12
14
16
Everspin Toggle MRAM
Cumulative Shipments (Mu)
* Projections
6
2006 2007 2008 2009 2010 2011 2012 2013 2014 2015
Spin Torque
MRAM
64Mb
DDR3
Serial SPI
Compatible
256Kb,
1Mb
4Mb
Next
Gen Hi-
Speed
SRAM
Compatible
SOIC
256Kb,
1Mb
(x8)
SRAM
Compatible
BGA
256Kb,
1Mb,4Mb
(x16 x8)
1 Mb,256Kb
3.3/1.8V
(x8)
16 Mb
(x16)
16 Mb
(x8)
ST-
MRAM
SRAM
Compatible
TSSOP
4Mb
(x16)
1Mb
(x16)
256Kb,
1Mb, 4Mb
(x16 x8)
1 Mb,256Kb
3.3/1.8V
(x8)
16 Mb
(x16)
16 Mb
(x8)
ST-
MRAM
Product Roadmap
Production
Sampling
Design
Concept
Pre-
Production
Rapidly Increasing
From Mb to Gb Density
Increasing
density and
speed
Increasing
density as
defined
by market
requirements
Increasing
density as
defined
by market
requirements
7
Spin-Torque Next Generation MRAM
Current Toggle MRAM uses a magnetic field for switching
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Next generation MRAM enables scaling to Gb densities
Everspin on track to deliver industrys first ST-MRAM
8
Toggle Write Spin-Torque Write
Everspin Introduces the
64Mb DDR3 ST-MRAM
CES 2013
Propriotary & Conhdontial
ST-MRAM
^
ST-
What weve announced
G Everspin debuts first Spin-Torque MRAM for high
performance storage systems,
G The EMD3D064M - 64Mb DDR3 ST-MRAM
G A new type of high performance and ultra-low latency memory that
will transform storage architecture
G A performance-optimized Storage Class Memory (SCM) that bridges
the role of todays conventional memory with the demands of
tomorrows storage systems
G Provides non-volatility and high endurance
G Compatible with the industry standard JEDEC DDR3 specification
G 1600 million transfers per second per I/O, Bandwidth of 3.2 GBytes/second
G Select customers are now evaluating working samples.
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Propriotary & Conhdontial
ST-MRAM
^
ST-
Product Overview
64Mb DDR3 ST-MRAM
G Non-volatile 64Mb DDR3
G DDR3-1600 ST-MRAM
G 16Mbx4, 8Mbx8, and 4Mbx16 configurations
G Supports Standard DDR3 SDRAM Features
G No refresh required
G Burst length: 8 (programmable Burst Chop of 4)
G DDR3 SDRAM Standard FBGA Package Pinout:
G VDD = 1.5V +/-.075V
G On-device termination
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Propriotary & Conhdontial
ST-MRAM
^
ST-
Building the ST-MRAM Eco System
G FPGA Evaluation Boards
G Using DDR3 ST-MRAM DIMMs
G DDR3 ST-MRAM controller IP
G Enabling Memory Subsystems
G Enabling Storage Subsystems
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Why its needed
Scalability Issues: Application Performance degrading
Faster & consistent data storage access is
needed to deliver acceptable performance
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MORE DATA + MORE USERS + INSTANT ACCESS
What the industry is saying
G Three new low latency memories on the horizon:
Phase Change Memory, Memristor and Spin-Torque MRAM
G Processor architectures & filing systems need dramatic
redesign to take advantage of new NVM technologies
G Systems must be ready for low latency NVM in 3-5 years
G Huge power savings and much faster data transfer
G Changing the memory hierarchy has huge knock-on effects
on how computation works!
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Justin Rattner, CTO Intel, IDF 2012 San Francisco
Bifurcation of Moores Law
G Continuous demand for exponential cost declines in
computational power and storage density
G Radical advances in memory density & performance
will relieve processor memory performance bottleneck
G Processor chips dominated by memory, not logic
G Long wait time when accessing off-chip memory
G Big Data driving $28B of IT Spending in 2012
Ultra-low latency MRAM extends Moores Law
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Compute needs ultra-low latency NVM
NAND improved storage I/O performance & latency
BUT still several orders of magnitude latency GAP
ST-MRAM is closest to RAM and
to high volume mass production
16
l
a
t
e
n
c
y
(
n
s
)
10
-1
10
0
CPU RAM
10
9
TAPE DISK
10
6
10
4
NAND
MRAM
10
1
Delivering 10x better Price/Performance
Cloud Storage Needs:
More content & users, instant access
Better response times from storage
Predictable balanced performance
Nanosecond-class MRAM Storage
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at only 50x Cost/GB
500x Performance
NAND SSD
MRAM SSD
Key Metrics NAND MRAM
Density 64Gb 1Gb
Latency 50us 45ns
4kB Write IOPS 800 400k
Cost/GB 1 50
Delivering 100x Power/Performance
Data Center needs:
Number of servers & CPU cores exploding
Better bandwidth & IOPS to handle Big Data
More performance @ less power to scale up
High Performance, Power-Efficient MRAM Storage
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Key Metrics NAND MRAM
Density 64Gb 1Gb
Power 80mW 400mW
4kB Write IOPS 800 400k
Cost/GB 1 50
at only 5x Power
500x Performance
NAND SSD
MRAM SSD
Faster, more reliable Enterprise Storage
G Enterprise Storage: Cant lose data if power fails!
G Historically using batteries/caps to protect data in RAM
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Areas of concern DRAM with battery/caps Spin-Torque MRAM
Write performance Temporary persistent cache Truly persistent write cache
Complexity Power fail circuitry Simplified system
Reliability Lifetime reliability issues Truly persistent RAM
Form factor Large battery/caps No battery/caps
Temperature Commercial Automotive
Environmental Battery/caps concerns Truly green storage
Storage Solutions craving ST-MRAM
ST-MRAM complements solid state & magnetic storage
Improved response time due to low latency & high bandwidth
ST-MRAM as Buffer Memory
MRAM instead of low density DRAM
Better performance & reliability
ST-MRAM as I/O & Network Cache
MRAM instead of NV-DRAM
Better reliability & overall TCO
ST-MRAM as Fast Storage-Tier
MRAM in addition to SSD/HDD
Better IOPS/$/W & reliability
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Multi-billion dollar market opportunity
21
Advancing Storage Architecture
G Storage OEMs are tuning storage to application needs
Capacity, Performance, Power, Uptime/Service and Reliability
OEMs need to balance storage capacity and performance
HDD leveraged as capacity optimized data storage
qBenefits : Lowest cost per GB/TB for data storage
qChallenges: Random access, active power & power fail
NAND SSD leveraged as performance optimized storage
qBenefits : More IOPS, reduced latency & less overall power
qChallenges: Write latency & variability, endurance, power fail
ST-MRAM leveraged as non-volatile buffer/cache for storage
qBenefits : DRAM like access, unlimited endurance & power fail
qChallenges: New storage architecture, density & cost scaling
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Positioned for Extraordinary Growth
Eversp|n |s the |eader |n MRAM techno|ogy
G Proven track record - manufacturing MRAM since 2006
G Top tier 1 customers Dell, LSI, Siemens, BMW, Airbus etc
G Deployment in many applications with exemplary quality
Continued MRAM leadership
G Leadership ST-MRAM R&D with initial silicon demonstrated
G On traok to dolivor tno industry's hrst ST-MPAM produot
Sca||ng to meet future demand
G Expanding Togglo MPAM oapaoity and souroing hoxibility
G Establishing 300mm ST-MRAM capacity to reduce cost
G Asset light approach in collaboration with partners
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CES 2013