INTEGRATED CIRCUITS

DATA SHEET
For a complete data sheet, please also download:

• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT166
8-bit parallel-in/serial-out shift
register
Product specification December 1990
File under Integrated Circuits, IC06
Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

FEATURES an active LOW parallel enable (PE) input. When PE is

LOW one set-up time prior to the LOW-to-HIGH clock
• Synchronous parallel-to-serial applications
transition, parallel data is entered into the register. When
• Synchronous serial data input for easy expansion PE is HIGH, data is entered into the internal bit position Q0
• Clock enable for “do nothing” mode from serial data input (Ds), and the remaining bits are
shifted one place to the right (Q0 → Q1 → Q2, etc.) with
• Asynchronous master reset
each positive-going clock transition.
• For asynchronous parallel data load see “165” This feature allows parallel-to-serial converter expansion
• Output capability: standard by tying the Q7 output to the Ds input of the succeeding
• ICC category: MSI stage.
The clock input is a gated-OR structure which allows one
GENERAL DESCRIPTION input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
The 74HC/HCT166 are high-speed Si-gate CMOS devices and can be reversed for layout convenience. The
and are pin compatible with low power Schottky TTL LOW-to-HIGH transition of input CE should only take place
(LSTTL). They are specified in compliance with JEDEC while CP is HIGH for predictable operation. A LOW on the
standard no. 7A. master reset (MR) input overrides all other inputs and
The 74HC/HCT166 are 8-bit shift registers which have a clears the register asynchronously, forcing all bit positions
fully synchronous serial or parallel data entry selected by to a LOW state.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V
CP to Q7 15 20 ns
MR to Q7 14 19 ns
fmax maximum clock frequency 63 50 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 41 41 pF

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V

ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 Ds serial data input
2, 3, 4, 5, 10, 11, 12, 14 D0 to D7 parallel data inputs
6 CE clock enable input (active LOW)
7 CP clock input (LOW-to-HIGH edge-triggered)
8 GND ground (0 V)
9 MR asynchronous master reset (active LOW)
13 Q7 serial output from the last stage
15 PE parallel enable input (active LOW)
16 VCC positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

Fig.4 Functional diagram.

FUNCTION TABLE

INPUTS Qn REGISTER OUTPUT

OPERATING MODES
PE CE CP DS D0-D7 Q0 Q1-Q6 Q7
I I ↑ X I-I L L-L L
parallel load
I I ↑ X h-h H H-H H
h I ↑ I X-X L q0 - q5 q6
serial shift
h I ↑ h X-X H q0 - q5 q6
hold “do nothing” X h X X X-X q0 q 1 - q6 q7

Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

Fig.5 Logic diagram.

Fig.6 Typical clear, shift, load, inhibit, and shift sequences.

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HC
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay 50 150 190 225 ns 2.0 Fig.7
CP to Q7 18 30 38 45 4.5
14 26 33 38 6.0
tPHL propagation delay 47 160 200 240 ns 2.0 Fig.8
MR to Q7 17 32 40 48 4.5
14 27 34 41 6.0
tTHL/ tTLH output transition time 19 75 95 110 ns 2.0 Fig.7
7 15 19 22 4.5
6 13 16 19 6.0
tW clock pulse width 80 17 100 120 ns 2.0 Fig.7
HIGH or LOW 16 6 20 24 4.5
14 5 17 20 6.0
tW master reset pulse width 100 25 125 150 ns 2.0 Fig.8
LOW 20 9 25 30 4.5
17 7 21 26 6.0
trem removal time 0 −19 0 0 ns 2.0 Fig.8
MR to CP 0 −7 0 0 4.5
0 −6 0 0 6.0
tsu set-up time 80 14 100 120 ns 2.0 Fig.9
Dn, CE to CP 16 5 20 24 4.5
14 4 17 20 6.0
tsu set-up time 100 33 125 150 ns 2.0 Fig.8
PE to CP 20 12 25 30 4.5
17 10 21 26 6.0
th hold time 2 −8 2 2 ns 2.0 Fig.8
Dn, CE to CP 2 −3 2 2 4.5
2 −2 2 2 6.0
th hold time 0 −28 0 0 ns 2.0 Fig.9
PE to CP 0 −10 0 0 4.5
0 −8 0 0 6.0
fmax maximum clock pulse 6.0 19 4.8 4.0 MHz 2.0 Fig.7
frequency 30 57 24 20 4.5
35 68 28 24 6.0

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

D0 to D7 0.35
Ds 0.35
CP 0.80
CE 0.80
MR 0.40
PE 0.60

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; tr = tf = 6 ns; CL = 50 pF

Tamb (°C) TEST CONDITIONS

74HCT
SYMBOL PARAMETER UNIT VCC WAVEFORMS
+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay 23 40 50 60 ns 4.5 Fig.7
CP to Q7
tPHL propagation delay 22 40 50 60 ns 4.5 Fig.8
MR to Q7
tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.7

tW clock pulse width 20 9 25 30 ns 4.5 Fig.7

HIGH or LOW
tW master reset pulse width 25 11 31 38 ns 4.5 Fig.8
LOW
trem removal time 0 −7 0 0 ns 4.5 Fig.8
MR to CP
tsu set-up time 16 8 20 24 ns 4.5 Fig.9
Dn, CE to CP
tsu set-up time 30 15 38 45 ns 4.5 Fig.8
PE to CP
hold time
th 0 −3 0 0 ns 4.5 Fig.9
Dn, CE to CP
hold time
th 0 −13 0 0 ns 4.5 Fig.9
PE to CP
maximum clock pulse
fmax 25 45 20 17 MHz 4.5 Fig.7
width

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

AC WAVEFORMS

The changing to output assumes internal Q6 opposite state from Q7.

The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3V.

Fig.7 Waveforms showing the clock (CP) to output (Q7) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency.

The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3V.

Fig.8 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7) propagation delay
and the master reset to clock (CP) removal time.

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Philips Semiconductors Product specification

8-bit parallel-in/serial-out shift register 74HC/HCT166

The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3V; VI = GND to 3V.

Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds), the data inputs (Dn), the
clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).

PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

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