CHAPTER 12

CMOS CHIP DESIGN

Introduction The design description for an integrated circuit may be described in terms of three domains, namely: behavioral, structural and physical domains. In each of these domains, there are a number of design options that may be selected to solve a particular problem. For instance, at the behavioral level, the freedom to choose, say, a sequential or a parallel algorithm is available. In the structural domain, the decision about which particular logic family, clocking strategy, or circuit style to use is initially unbound. At the physical level, how the circuit is implemented in terms of chips, boards, and cabinets also provides many options to the designer. These domains may be hierarchically divided into levels of design abstraction. lassically, these include the following: Architectural or functional level !egister Transfer"level #!T$% $ogic level ircuit level The relationship between description domains and levels of design abstraction are elegantly shown by the &" hart in Fig.'(.'. In this diagram, the three radial lines represent the three description domains namely, behavioral, structural and physical domains. Along each line are enumerated types of ob)ects in that domain. oncentric circles around the centre indicate the various levels of abstraction that are common in electronic design. The particular abstraction levels and design ob)ects may differ slightly, depending on the design method. In this chapter, we begin by discussing the various design strategies available to the *+, I designer, the *+, chip design options: i.e., the different types of ircuits #A,I s%, programmable logic structures, A,I Application ,pecific Integrated design flow etc.

Fig. &" hart showing description domains and levels of design abstraction Design Strategies A good -$,I design system should provide for consistent descriptions in all three description domains #behavioral, structural, and physical% and at all levels of abstraction. The means by which this is accomplished may be measured in terms of various design parameters as summari.ed below: /erformance " speed, power, function, fle0ibility. ,i.e of die and its cost. Time of design and hence cost of engineering and schedule. 1ase of test generation and testability.

2esign is a continuous trade off to achieve the adequate results for all levels of the above parameters. The tools and methodologies used for a particular chip will be a function of these parameters. 3iven that the process of designing a system on silicon is complicated, the role of good -$,I design aids is to reduce this comple0ity, increase productivity, and assure the designer of a working product. A good method of simplifying the approach to a design is by the use of constraints and abstractions. Structured design strategies The successful implementation of almost any I requires an attention to the

details of the engineering design process. A number of structured design techniques have been developed to deal with both comple0 hardware and software pro)ects. 4hether under consideration is a small chip designed by a single designer or a large systen designed by a team of designers, the basic principles of structured design will improve the prospects of success. Hierarchy The use of hierarchy, or 5divide and conquer5, involves dividing a module into submodules until the comple0ity of the submodules is at an appropriately comprehensive level of detail. This parallels the software case where large programs are split into smaller and smaller sections until simple subroutines, with well"defined functions and interfaces, can be written. Regu arity 6ierarchy involves dividing a system into a set of submodules. 6owever, hierarchy alone does not necessarily solve the comple0ity problem. For instance, we could repeatedly divide the hierarchy of a design into different submodules but still end up with a large number of different submodules. 4ith regularity, the designer attempts to divide the hierarchy into a set of similar building blocks. The use of iteration to form arrays of identical cells is an illustration of the use of regularity in an I design. !egularity can e0ist at all levels of the design hierarchy. At the circuit level, uniformly si.ed transistors might be used. At the logic"module level, identical gate structures might be employed. At higher levels, one can construct architectures that use a number of identical processor structures. !egularity allows an improvement in productivity by reusing specific designs in a number of places, thereby reducing the number of different designs that need to be completed. Modu arity The principle of modularity adds to hierarchy and regularity the condition that submodules have well"defined functions and interfaces. If modules are 7well"formed8, the interaction with other modules may be well characteri.ed. A good starting point is the criteria placed on a 7well"formed8 software subroutine. A well"defined interface is required which in the case of software is an argument list with typed variables. In the I case, this corresponds to a well"defined behavioral, structural, and physical interface that

indicates the position, name, layer type, si.e and signal type of e0ternal interconnections, along with logic function and electrical characteristics. *odularity helps the designer to clarify and document an approach to a problem, and also allows a design system to more easily check the attributes of a module as it is constructed. The ability to divide the task into a set of well"defined modules aids in a team design where each of a number of designers has a portion of a complete chip to design. !oca ity 9y defining well"characteri.ed interfaces for a module, the other internals of the module become unimportant to any e0terior interface. In this way, by performing a form of 7information hiding8, the apparent comple0ity of the module is reduced. In software, this is accomplished by reducing the global variables to a minimum #to .ero%. CMOS chi" design o"tions In this section, a range of design options that may be used to implement a *+, system design will be e0amined. The design options include different types of Application ,pecific Integrated ircuits #A,I s% like full custom A,I s, ,tandard cell hannelled, hannelless and ,tructured gate based A,I s, 3ate array based A,I s,

array, and programmable logic such as programmable logic structures, programmable interconnect and reprogrammable gate arrays. A"" ication S"eci#ic Integrated Circuits $ASICs% An Application ,pecific Integrated ircuit #A,I % is an integrated circuit#I % customised for a particular use, rather than intended for general"purpose use. For e0ample, a chip designed solely to run a cell phone is an A,I . In contrast, the :;<< series and ;<<< series integrated circuits are logic building blocks that can be wired together to perform many different applications. Intermediate between A,I s and standard products are Application ,pecific ,tandard /roducts #A,,/s%. The ma0imum comple0ity and hence functionality possible in an A,I has grown from =<<< gates to over '<< million. *odern A,I s often include entire >("bit processors, memory blocks including !+*, !A*, 11/!+*, Flash and other logic building blocks. ,uch an A,I is often termed as ,ystem "on a hip #,o %. 2esigners of digital A,I s use a 6ardware 2escription $anguage #62$%, such as -erilog or -62$, to describe the functionality of A,I s. A,I s are commonly used in networking devices

to ma0imi.e performance. Ty"es o# ASICs I s are made on a thin #a few hundred microns thick%, circular silicon wafer, with each wafer holding hundreds of die #sometimes people use dies or dice for the plural of die%. The transistors and wiring are made from many layers #usually between '< and '= distinct layers% built on top of one another. 1ach successive mask layer has a pattern that is defined using a mask similar to a glass photographic slide. The first half"do.en or so layers define the transistors. The last half"do.en or so layers define the metal wires between the transistors #the interconnect%. A #u &custo' IC includes some #possibly all% logic cells that are customi.ed and all mask layers that are customi.ed. e.g. a microprocessor ?designers spend many hours squee.ing the most out of every last square micron of microprocessor chip space by hand. ustomi.ing all of the I features in this way allows designers to include analog circuits, optimi.ed memory cells, or mechanical structures on an I . Full"custom I s are the most e0pensive to manufacture and to design. The manufacturing lead time #the time it takes )ust to make an I ?not including design time% is typically eight weeks for a full"custom I . 4e shall discuss the different full"custom A,I s briefly ne0t, mainly about se'icusto' ASICs and "rogra''a( e ASICs) In se'icusto' ASICs, all of the logic cells are predesigned and some #possibly all% of the mask layers are customi.ed. @sing predesigned cells from a cell library makes our lives as designers much, much easier. There are two types of semicustom A,I s: standard"cellAbased A,I s and gate"arrayA based A,I s. Following this, the "rogra''a( e ASICs are described. In this, all of the logic cells are predesigned and none of the mask layers are customi.ed. There are two types of programmable A,I s: the programmable logic device #/$2% and the field" programmable gate array #F/3A%. *u &Custo' ASICs In a full"custom A,I , some or all of the logic cells, circuits, or layout are designed specifically for one A,I . This means the designer abandons the approach of using pretested and precharacteri.ed cells for all or part of that design. It makes sense to

take this approach only if there are no suitable e0isting cell libraries available that can be used for the entire design. This might be because e0isting cell libraries are not fast enough, or the logic cells are not small enough or consume too much power. 9ipolar technology has historically been used for precision analog functions. There are some fundamental reasons for this. In all integrated circuits the matching of component characteristics between chips is very poor, while the matching of characteristics between components on the same chip is e0cellent. ,uppose we have transistors T', T(, and T> on an analogBdigital A,I . The three transistors are all the same si.e and are constructed in an identical fashion. Transistors T' and T( are located ad)acent to each other and have the same orientation. Transistor T> is the same si.e as T' and T( but is located on the other side of the chip from T' and T( and has a different orientation. I s are made in batches called wafer lots. A wafer lot is a group of silicon wafers that are all processed together. @sually there are between = and >< wafers in a lot. 1ach wafer can contain tens or hundreds of chips depending on the si.e of the I and the wafer. If we were to make measurements of the characteristics of transistors T', T(, and T> we would find the following: Transistors T' will have virtually identical characteristics to T( on the same I . 4e say that the transistors match well or the tracking between devices is e0cellent. Transistor T> will match transistors T' and T( on the same I very well, but not as closely as T' matches T( on the same I . Transistor T', T(, and T> will match fairly well with transistors T', T(, and T> on a different I on the same wafer. The matching will depend on how far apart the two I s are on the wafer. Transistors on I s from different wafers in the same wafer lot will not match very well. Transistors on I s from different wafer lots will match very poorly. 2evice physics dictates that a pair of bipolar transistors will always match

more precisely than

*+, transistors of a comparable si.e. 9ipolar technology has *+, technology for analog *+, A,I s and

historically been more widely used for full"custom analog design because of its improved precision. 2espite its poorer analog properties, the use of now by far the most widely available I functions is increasing. There are two reasons for this. The first reason is that *+, is technology. *any more *+, standard products are now being manufactured than bipolar I s. The second reason is that increased levels of integration require mi0ing analog and digital functions on the same I : this has forced designers to find ways to use implement analog functions. Standard&Ce +,ased ASICs A ce &(ased ASIC #or C,IC% uses predesigned logic cells #AC2 gates, +! gates, multiple0ers, and flip"flops, for e0ample% known as standard ce s. The standard"cell areas #also called fle0ible blocks% in a 9I are built of rows of standard cells. The standard"cell areas may be used in combination with larger predesigned cells, perhaps microcontrollers or even microprocessors, known as 'egace s. *egacells are also called megafunctions, full"custom blocks, system"level macros #,$*s%, fi0ed blocks, cores, or Functional ,tandard 9locks #F,9s%. The A,I designer defines only the placement of the standard cells and the interconnect in a are customi.ed and are unique to a particular customer. The advantage of 9I s is that designers save time, money, and reduce risk by i(rary. In addition 9I . 6owever, the standard cells can be placed anywhere on the siliconD this means that all the mask layers of a 9I *+, technology to

using a predesigned, pretested, and precharacteri.ed standard&ce

each standard cell can be optimi.ed individually. For e0ample, during the design of the cell library each and every transistor in every standard cell can be chosen to ma0imi.e speed or minimi.e area. The disadvantages are the time or e0pense of designing or buying the standard"cell library and the time needed to fabricate all layers of the A,I for each new design. Fig.'(.( shows a follows: 9I . The important features of this type of A,I are as

All mask layers are customi.ed?transistors and interconnect. ustom blocks can be embedded.

 *anufacturing lead time is about eight weeks.

A cell"based A,I # 9I % die with a single standard"cell area #a fle0ible block% together with four fi0ed blocks. The fle0ible block contains rows of standard cells. The small squares around the edge of the die are bonding pads that are connected to the pins of the A,I package.

1ach standard cell in the library is constructed using full"custom design methods, but these predesigned and precharacteri.ed circuits can be used without having to do any full"custom design. This design style gives the same performance and fle0ibility advantages of a full"custom A,I but reduces design time and reduces risk. ,tandard cells are designed to fit together like bricks in a wall. Fig.'(.> shows an e0ample of a simple standard cell. /ower and ground buses #-22 and 3C2 or -,,% run hori.ontally on metal lines inside the cells.

Fig. This cell would be appro0imately (= microns wide on an A,I with l #lambda% E <.(= microns #a
micron is '< AF m%. ,tandard cells are stacked like bricks in a wallD the abutment bo0 #A9% defines the

7edges8 of the brick. The difference between the bounding bo0 #99% and the A9 is the area of overlap between the bricks. /ower supplies #labeled -22 and 3C2% run hori.ontally inside a standard cell on a metal layer that lies above the transistor layers. 1ach different shaded and labeled pattern represents a different layer. This standard cell has center connectors #the three squares, labeled A', 9', and G% that allow the cell to connect to others.

,tandard"cell design allows the automation of the process of assembling an A,I . 3roups of standard cells fit hori.ontally together to form rows. The rows stack vertically to form fle0ible rectangular blocks #which you can reshape during design%. A fle0ible block built from several rows of standard cells may then be connected to other standard" cell blocks or other full"custom logic blocks. *odern *+, A,I s use two, three, or more levels #or layers% of metal for

interconnect. This allows wires to cross over different layers in the same way that we use copper traces on different layers on a printed"circuit board. In a two"level metal *+, technology, connections to the standard"cell inputs and outputs are usually made using the second level of metal #'eta 2, the upper level of metal% at the tops and bottoms of the cells. In a three"level metal technology, connections may be internal to the logic cell #Fig. '(.>%. This allows for more sophisticated routing programs to take advantage of the e0tra metal layer to route interconnect over the top of the logic cells. A connection that needs to cross over a row of standard cells uses a #eedthrough. The term feedthrough can refer either to the piece of metal that is used to pass a signal through a cell or to a space in a cell waiting to be used as a feedthrough. Fig.'(.; shows two feedthroughs: one in cell A.'; and one in cell A.(>.

Fig.'(.; !outing the 9I #cell"based I % shown in Fig.'(.(. The use of regularly shaped
standard cells, such as the one in Fig.'(.>, from a library allows A,I s like this to be designed automatically. This A,I uses two separate layers of metal interconnect #metal' and metal(% running at right angles to each other #like traces on a printed"circuit board%. Interconnections between logic cells uses spaces #called channels% between the rows of cells. A,I s may have three #or more% layers of metal allowing the cell rows to touch with the interconnect running over the top of the cells.

In both two"level and three"level metal technology, the power buses #-22 and 3C2% inside the standard cells normally use the lowest #closest to the transistors% layer of metal #'eta 1%. The width of each row of standard cells is ad)usted so that they may be aligned using s"acer ce s. The power buses, or rails, are then connected to additional vertical power rails using ro-&end ce s at the aligned ends of each standard"cell block. If the rows of standard cells are long, then vertical power rails can also be run in metal( through the cell rows using special "o-er ce s that )ust connect to -22 and 3C2. @sually the designer manually controls the number and width of the vertical power rails connected to the standard"cell blocks during physical design. A diagram of the power distribution scheme for a 9I is shown in Fig.'(.;. All the mask layers of a 9I are customi.ed. This allows megacells #,!A*, a , ,I controller, or an */13 decoder, for e0ample% to be placed on the same I with behavioral models and some way to test them #a test strategy%. A,I with library standard cells. *egacells are usually supplied by an A,I or library company complete companies also supply compilers to generate fle0ible 2!A*, ,!A*, and !+* blocks. ,ince all mask layers on a standard"cell design are customi.ed, memory design is more efficient and denser than for gate arrays. For logic that operates on multiple signals across a data bus? a data"ath #2/%? the use of standard cells may not be the most efficient A,I design style. ,ome A,I library companies provide a datapath compiler that automatically generates data"ath ogic. A data"ath i(rary typically contains cells such as adders, subtracters, multipliers, and simple arith'etic and ogica units $A!.s%. The connectors of datapath library cells are "itch&'atched to each other so that they fit together. onnecting datapath cells to form a datapath usually, but not always, results in faster and denser layout than using standard cells or a gate array.

,tandard"cell and gate"array libraries may contain hundreds of different logic cells, including combinational functions #CAC2, C+!, AC2, +! gates% with multiple inputs, as well as latches and flip"flops with different combinations of reset, preset and clocking options. The A,I each library element. Gate&Array+,ased ASICs In a gate array #3A% or gate"arrayAbased A,I the transistors are predefined on the silicon wafer. The predefined pattern of transistors on a gate array is the (ase array, and the smallest element that is replicated to make the base array is the (ase ce #sometimes called a "ri'iti/e ce %. +nly the top few layers of metal, which define the interconnect between transistors, are defined by the designer using custom masks. To distinguish this type of gate array from other types of gate array, it is often called a 'as0ed gate array $MGA%) The designer chooses from a gate"array library of predesigned and precharacteri.ed logic cells. The logic cells in a gate"array library are often called 'acros. The reason for this is that the base"cell layout is the same for each logic cell, and only the interconnect #inside cells and between cells% is customi.ed, so that there is a similarity between gate"array macros and a software macro. Inside I9*, gate" array macros are known as (oo0s. 9oth cell"based and gate"array A,I s use predefined cells, but there is a difference?we can change the transistor si.es in a standard cell to optimi.e speed and performance, but the device si.es in a gate array are fi0ed. This results in a trade"off in performance and area in a gate array at the silicon level. The trade"off between area and performance is made at the library level for a standard"cell A,I . 4e can complete the diffusion steps that form the transistors and then stockpile wafers #sometimes we call a gate array a "redi##used array for this reason%. ,ince only the metal interconnections are unique to an *3A, we can use the stockpiled wafers for different customers as needed. @sing wafers prefabricated up to the metalli.ation steps reduces the time needed to make an *3A, the turnaround ti'e, to a few days or at most a couple of weeks. The costs for all the initial fabrication steps for an *3A are shared for each customer and this reduces the cost of an *3A compared to a library company provides designers with a data book in paper or electronic form with all of the functional descriptions and timing information for

full"custom or standard"cell A,I design. There are the following different types of *3A or gate"arrayAbased A,I s: hanneled gate arrays. hannelless gate arrays. ,tructured gate arrays.

In the channeled gate"array architecture,8 the gate array is channeled. There are two common ways of arranging #or arraying% the transistors on a *3A: in a channeled gate array we leave space between the rows of transistors for wiringD the routing on a channelless gate array uses rows of unused transistors. The channeled gate array was the first to be developed, but the channelless gate"array architecture is now more widely used. A structured #or embedded% gate array can be either channeled or channelless but it includes #or embeds% a custom block. Channe ed Gate Array Fig.'(.= shows a channeled gate array. The important features of this type of *3A are: cells. *anufacturing lead time is between two days and two weeks. +nly the interconnect is customi.ed. The interconnect uses predefined spaces between rows of base

FigA channeled gate"array die. The spaces between rows of the base cells are set
aside for interconnect

A channeled gate array is similar to a

9I ?both use rows of cells

separated by channels used for interconnect. +ne difference is that the space for interconnect between rows of cells are fi0ed in height in a channeled gate array, whereas

the space between rows of cells may be ad)usted in a 9I . Channe ess Gate Array Fig.'(.F shows a channelless gate array #also known as a channel"free gate array , sea"of"gates array , or ,+3 array%. The important features of this type of *3A are as follows: +nly some #the top few% mask layers are customi.ed?the interconnect. *anufacturing lead time is between two days and two weeks.

Fig. A channelless gate"array or sea"of"gates #,+3% array die. The core area of the die is completely filled with an array of base cells #the base array%. The key difference between a channelless gate array and channeled gate array is that there are no predefined areas set aside for routing between cells on a channelless gate array. Instead we route over the top of the gate"array devices. 4e can do this because we customi.e the contact layer that defines the connections between metal', the first layer of metal, and the transistors. 4hen we use an area of transistors for routing in a channelless array, we do not make any contacts to the devices lying underneathD we simply leave the transistors unused. Structured Gate Array An e'(edded gate array or structured gate array #also known as 'asters ice or 'asteri'age % combines some of the features of 9I s and *3As. +ne of the disadvantages of the *3A is the fi0ed gate"array base cell. This makes the implementation of memory, for e0ample, difficult and inefficient. In an embedded gate array we set aside some of the I area and dedicate it to a specific function. This embedded area either can contain a different base cell that is more suitable for building memory cells, or it can contain a complete circuit block, such as a microcontroller.

Fig.'(.: shows an embedded gate array. The important features of this type of *3A are the following: embedded. weeks. *anufacturing lead time is between two days and two +nly the interconnect is customi.ed. ustom blocks #the same for each design% can be

Fig. A structured or embedded gate"array die showing an embedded block in the upper
left corner #e.g., a static random"access memory%. The rest of the die is filled with an array of base cells.

An embedded gate array gives the improved area efficiency and increased performance of a 9I but with the lower cost and faster turnaround of an *3A. +ne disadvantage of an embedded gate array is that the embedded function is fi0ed. For e0ample, if an embedded gate array contains an area set aside for a >( k"bit memory, but we only need a 'F k"bit memory, then we may have to waste half of the embedded memory function. 6owever, this may still be more efficient and cheaper than implementing a >( k"bit memory using macros on a ,+3 array. Progra''a( e !ogic De/ices $P!Ds% /rogrammable logic devices # /$2s % are standard I s that are available in standard configurations. 6owever, /$2s may be configured or programmed to create a part customi.ed to a specific application, and so they also belong to the family of A,I s. /$2s use different technologies to allow programming of the device. Fig.'(.H shows a /$2 and the following important features that all /$2s have in common: Co customi.ed mask layers or logic cells

 Fast design turnaround A single large block of programmable interconnect A matri0 of logic macrocells that usually consist of programmable array logic followed by a flip"flop or latch

Fig. A programmable logic device #/$2% die. The macrocells typically consist of programmable array logic followed by a flip"flop or latch. The macrocells are connected using a large programmable interconnect block. The simplest type of programmable I is a read&on y 'e'ory $ROM%) The most common types of !+* use a metal fuse that can be blown permanently #a "rogra''a( e ROM or PROM%. An electrically programmable !+*, or 1/!+*, uses programmable *+, transistors whose characteristics are altered by applying a high voltage. +ne can erase an 1/!+* either by using another high voltage #an e ectrica y erasa( e PROM, or EEPROM% or by e0posing the device to ultraviolet light # .1& erasa( e PROM, or .1PROM%. There is another type of !+* that can be placed on any A,I ?a 'as0& "rogra''a( e ROM #mask"programmed !+* or masked !+*%. A masked !+* is a regular array of transistors permanently programmed using custom mask patterns. An embedded masked !+* is thus a large, speciali.ed, logic cell. The same programmable technologies used to make !+*s can be applied to more fle0ible logic structures. 9y using the programmable devices in a large array of AC2 gates and an array of +! gates, we create a family of fle0ible and programmable logic devices called ogic arrays. The company *onolithic *emories was the first to produce Progra''a( e Array !ogic $PA!% devices. A /A$ can also include registers #flip"flops% to store the current state information so that you can use a /A$ to make a

complete state machine. Iust as we have a mask"programmable !+*, we could place a logic array as a cell on a custom A,I . This type of logic array is called a "rogra''a( e ogic array $P!A%) There is a difference between a /A$ and a /$A: a /$A has a programmable AC2 logic array, or AC2 plane, followed by a programmable +! logic array, or +! planeD a /A$ has a programmable AND " ane and, in contrast to a /$A, a fi0ed OR " ane. 2epending on how the /$2 is programmed, we can have an erasa( e P!D $EP!D%2 or 'as0&"rogra''ed P!D #sometimes called a 'as0ed P!D but usually )ust /$2%. The first /A$s, /$As, and /$2s were based on bipolar technology and used programmable fuses or links. *+, /$2s usually employ floating"gate transistors. *ie d&Progra''a( e Gate Arrays $*PGAs% A step above the /$2 in comple0ity is the field"programmable gate array #F/3A%. There is very little difference between an F/3A and a /$2?an F/3A is usually )ust larger and more comple0 than a /$2. In fact, some companies that manufacture programmable A,I s call their products F/3As and some call them comple0 /$2s. F/3As are the newest member of the A,I family and are rapidly growing in importance, replacing TT$ in microelectronic systems. 1ven though an F/3A is a type of gate array, we do not consider the term gate"arrayAbased A,I s to include F/3As. This may change as F/3As and *3As start to look more alike. Fig.'(.J illustrates the essential characteristics of an F/3A: Cone of the mask layers are customi.ed. A method for programming the basic logic cells and the interconnect. The core is a regular array of programmable basic logic cells that can implement combinational as well as sequential logic #flip"flops%. A matri0 of programmable interconnect surrounds the basic logic cells. /rogrammable IB+ cells surround the core. 2esign turnaround is a few hours.

Fig. A field"programmable gate array #F/3A% die. All F/3As contain a

regular structure of programmable basic logic cells surrounded by programmable interconnect. The e0act type, si.e, and number of the programmable basic logic cells varies tremendously.

The comple0 programmable logic device # /$2% and Field /rogrammable gate array #F/3A% and their programming techniques are described in detail in hapter ''.

Econo'ics o# ASICs
In this section, the economics of using A,I s in a product is discussed and compared for the most popular types of A,I s: an F/3A, an *3A, and a 9I . To make an economic comparison between these alternatives, the A,I itself is considered as a product and e0amined the components of product cost: fi0ed costs and variable costs. The most obvious economic factor in making a choice between the different A,I types is the part cost. /art costs vary enormously?one can pay anywhere from a few dollars to several hundreds of dollars for an A,I . In general, however, F/3As are more e0pensive per gate than *3As, which are, in turn, more e0pensive than 9I s. The price per gate for an F/3A to implement the same function is typically (A= times the cost of an *3A or 9I . Product Cost The total cost of any product can be separated into #i3ed costs and /aria( e costs:

Total product cost E fi0ed product cost K variable product cost 3 products sold

#'(.'%

Fi0ed costs are independent of sa es /o u'e ?the number of products sold. 6owever, the fi0ed costs amorti.ed per product sold #fi0ed costs divided by products

sold% decrease as sales volume increases. -ariable costs include the cost of the parts used in the product, assembly costs, and other manufacturing costs. The total part cost is Total part cost E fi0ed part cost K variable cost per part 0 volume of parts #'(.(%

The fi0ed cost when an F/3A is used can be low?i.e., we )ust have to buy the software and any programming equipment. The fi0ed part costs for an *3A or 9I are higher and include the costs of the masks, simulation, and test program development. Fig.'(.'< shows a (rea0&e/en gra"h that compares the total part cost for an F/3A, *3A, and a 9I with the following assumptions: F/3A fi0ed cost is L(',H<<, part cost is L>J. *3A fi0ed cost is LHF,<<<, part cost is L'<. 9I fi0ed cost is L';F,<<<, part cost is LH.

At low volumes, the *3A and the 9I are more e0pensive because of their higher fi0ed costs. The total part costs of two alternative types of A,I are equal at the break"even volume. In Fig.'(.'< the (rea0&e/en /o u'e for the F/3A and the *3A is about (<<< parts. The break"even volume between the F/3A and the (<,<<< parts. 9I is about ;<<< parts. The break"even volume between the *3A and the 9I is higher?at about

A break"even analysis for an F/3A, a masked gate array #*3A% and a custom cell"based A,I # 9I %.The break"even volume between two technologies is the point at which the total cost of parts are equal. These numbers are very appro0imate.

ASIC *i3ed Costs Fig.'(.'' shows a spreadsheet, 7Fi0ed part costs associated with A,I design. osts,8 that calculates the fi0ed

A spreadsheet, 7Fi0ed osts,8 for a field"programmable gate array #F/3A%, a masked gate array #*3A%, and a cell"based A,I # 9I %. These costs can vary wildly.

The training cost includes the cost of the time to learn any new electronic design auto'ation $EDA% system. For e0ample, a new F/3A design system might require a few days to learnD a new gate"array or cell"based design system might require taking a course. Fig.'(.'' assumes that the cost of an engineer #including overhead, benefits, infrastructure, and so on% is between L'<<,<<< and L(<<,<<< per year or L(<<< to L;<<< per week Ce0t, the hard-are and so#t-are cost for A,I design are considered. Fig.'(.'' shows some typical figures, but one can spend anywhere from L'<<< to L' million #and more% on A,I design software and the necessary infrastructure. The "roducti/ity of an A,I designer in gates #or transistors% per day is

measured. This is like trying to predict how long it takes to dig a hole, and the number of gates per day an engineer averages varies wildly. A,I design productivity must increase as A,I si.es increase and will depend on e0perience, design tools, and the A,I comple0ity. If we are using similar design methods, design productivity ought to be

independent of the type of A,I , but F/3A design software is usually available as a complete bundle on a / . This means that it is often easier to learn and use than semicustom A,I design tools. 1very A,I has to pass a "roduction test to make sure that it works. 4ith that are needed for

modern test tools the generation of any test circuits on each A,I

production testing can be automatic, but it still involves a cost for design #or test. An F/3A is tested by the manufacturer before it is sold to you and before you program it. &ou are still paying for testing an F/3A, but it is a hidden cost folded into the part cost of the F/3A. &ou do have to pay for any "rogra''ing costs for an F/3A, but we can include these in the hardware and software cost. The nonrecurring&engineering $NRE% charge includes the cost of work done by the A,I vendor and the cost of the masks. The production test uses sets of test inputs called test vectors, often many thousands of them. *ost A,I vendors require simulation to generate test vectors and test programs for production testing, and will charge for a test"program development cost. The number of masks required by an A,I fabrication can range from three or four #for a gate array% to '= or more #for a during 9I %.

Total mask costs can range from L=<<< to L=<,<<< or more. The total C!1 charge can range from L'<,<<< to L><<,<<< or more and will vary with volume and the si.e of the A,I . If you commit to high volumes #above '<<,<<< parts%, the vendor may waive the C!1 charge. The C!1 charge may also include the costs of software tools, design verification, and prototype samples. If a design does not work the first time, one has to complete a further design "ass #turn or s"in% that requires additional C!1 charges. Cormally one signs a contract #sign off a design% with an A,I one designed the A,I back. Cowadays it is almost routine to have an A,I work on the first pass. 6owever, if a design fails, it is little consolation to have a second pass for free if the company goes bankrupt in the meantime. Fig.'(.'( shows a "ro#it 'ode that represents the "ro#it # ovendor that guarantees first"pass success"this means that if according to rules specified by the vendor, then the vendor

guarantees that the silicon will perform according to the simulation or one gets his money

during the "roduct i#eti'e. @sing this model, we can estimate the lost profit due to any delay.

Fig. A profit model. If a product is introduced on time, the total sales are LF< million #the area of the higher triangle%. 4ith a three"month #one fiscal quarter% delay the sales decline to L(= million. The difference is shown as the shaded area between the two triangles and amounts to a lost revenue of L>= million. The last fi0ed cost shown in Fig.'(.'' corresponds to an 7insurance policy.8 4hen a company buys an A,I part, it needs to be assured that it will always have a back"up source, or second source, in case something happens to its first or primary source. 1stablished F/3A companies have a second source that produces equivalent parts. 4ith a custom A,I you may have to do some redesign to transfer your A,I to the second source. 6owever, for all A,I types, switching production to a second source will involve some cost. Fig.'(.'' assumes a second"source cost of L(<<< for all types of A,I #the amount may be substantially more than this%. ASIC 1aria( e Costs Fig.'(.'> shows a spreadsheet, 7-ariable osts,8 that calculates some e0ample

part costs. This spreadsheet uses the terms and parameters defined below the figure.

Fig. A spreadsheet, 7-ariable osts,8 to calculate the part cost #that is the variable cost for a product using A,I s% for different A,I technologies. The -a#er si4e increases every few years. From 'JH= to 'JJ<, ;"inch to F"inch diameter wafers were commonD equipment using F"inch to H"inch wafers was introduced between 'JJ< and 'JJ=D the ne0t step is the ><< cm or '("inch wafer. The '("inch wafer will probably take to (<<=. The -a#er cost depends on the equipment costs, process costs, and overhead in the fabrication line. A typical wafer cost is between L'<<< and L=<<<, with L(<<< being averageD the cost declines slightly during the life of a process and increases only slightly from one process generation to the ne0t. Moore5s !a- models the observation that the number of transistors on a chip roughly doubles every 'H months. Cot all designs follow this law, but a 7large8 A,I design seems to grow by a factor of '< every = years #close to *ooreMs $aw%. In 'JJ< a large A,I design si.e was '< k"gate, in 'JJ= a large design was about '<< k"gate, in (<<< it will be ' *"gate, in (<<= it will be '< *"gate. The gate density is the number of gate equivalents per unit area #a gate equivalent, or gate, corresponds to a two"input CAC2 gate%. The gate uti i4ation is the percentage of gates that are on a die that we can use #on a gate array, some gate space is wasted for interconnect%. The die si4e is determined by the design si.e #in gates%, the gate density, and the

utili.ation of the die. The number of die "er -a#er depends on the die si.e and the wafer si.e. The de#ect density is a measure of the quality of the fabrication process. The smaller the defect density the less likely there is to be a flaw on any one die. A single defect on a die is almost always fatal for that die. 2efect density usually increases with the number of steps in a process. A defect density of less than' cm"( is typical and required for a submicron *+, process. The yie d is the fraction of die on a wafer that are good #e0pressed as a percentage%. The yield of a process is the key to a profitable A,I company. &ield depends on the comple0ity and maturity of a process. A process may start out with a yield of close to .ero for comple0 chips, which then climbs to above =< percent within the first few months of production. 4ithin a year the yield has to be brought to around H< percent for the average comple0ity A,I for the process to be profitable. &ields of J< percent or more are not uncommon. The die cost is determined by wafer cost, number of die per wafer, and the yield. +f these parameters, the most variable and the most critical to control is the yield. The "ro#it 'argin #what you sell a product for, less what it costs you to make it, divided by the cost% is determined by the A,I costs. A,I companyMs fi0ed and variable vendors that make and sell custom A,I s have huge fi0ed and

variable costs associated with building and running fabrication facilities #a fabrication plant is a #a(%. F/3A companies are typically #a( ess ?they do not own a fab?they must pass on the costs of the chip manufacture #plus the profit margin of the chip manufacturer% and the development cost of the F/3A structure in the F/3A part cost. The profitability of any company in the A,I varies greatly. The "rice "er gate is determined by die costs and design si.e. It varies with design si.e and declines over time. The "art cost is determined by all of the preceding factors. It will vary widely with time, process, yield, economic climate, A,I si.e and comple0ity, and many business

other factors. As an estimate, the price per gate for any process technology falls at about (< N per year during its life #the average life of a *+, process is (A; years, and can vary widely%. 9eyond the life of a process, prices can increase as demand falls and the fabrication equipment becomes harder to maintain. CMOS Chi" design -ith "rogra''a( e ogic In this section, a range of *+, chip design options wing programmable logic

are e0amined. These are arranged in order of increased design investment. The sequence is also some what in order of comple0ity of device that may be implemented. In *+,, the programmable devices may be divided into three areas: i% hips with programmable logic structures hips with programmable inter connect hips with reprogrammable gate arrays First, it allows the designer to competently assess a particular system requirement for an I other top"level concerns. ii% ,econd, it familiari.es the I system designer with methods of making any chip design re"programmable and hence more useful and of wider spread use. and recommend a solution, given the system comple0ity, the speed" of" operation, cost goals, time"to"market goals, and

The *+, A system designer should be familiar with these options for two reasons:

Progra''a( e !ogic Structures

The first broad class of programmable *+, devices are represented by the programmable logic devices referred to as /A$s #/rogrammable Array $ogics%, 3enerally, these devices are implemented as AC2A+! plane devices. In the design shown, a number of inputs feed vertical wires, which are selectively connected to an AC2A+! gate. 1ach AC2A+! gate has a variable number of product terms that feed the gate. This gate in turn feeds an IB+ cell, which allows registering of the registered result into the AC2A+! plane. /A$ devices come in a large range of si.es with a variable number of inputs, outputs, product terms, and IB+ cell comple0ity. The ((-'< is an industry A standard devices with the following characteristics:

'( inputs '< OB+s Pproduct terms J '< '( '; 'F '; '( '< H (; pins

Progra''ing o# PA!s
The programming of /A$s is done in three main ways: Fusible links @- A erasable 1/!+* 11/!+* #1(/!+*% A 1lectrically 1rasable /rogrammable !+*

*usi( e in0s

Fusible links use a metal such as platinum silicide or titanium tungsten to form links that are blown when a certain current is e0ceeded in the fuse. This is normally accomplished by using a higher than normal programming voltage applied to the device. This technology is normally used in con)unction with a bipolar process #as opposed to a *+, process% where the small devices can readily sink the current needed to blow the fuses. /rogramming is a one"time operation. As an alternative to current, a laser can be used to out aluminium fuses in normal failing one. .1&erasa( e EPROM @- A erasable memories typically use a floating gate structure as shown in Fig.'(.';. 6ere, a floating gate is interposed between the regular *+, transistor gate and the channel. To program the cell, a voltage around '>"';- is applied to the control gate while the drain of the transistor to be programmed is held at around '(-.This results in the floating gate bevominy charged negatively. This increases the threshold of the transistor#to around F-%,this rendering it permanently 7off8 for all normal circuit voltages#ma0imum ="F-%The process can be reversed by illuminating the gate with uv light, 8permanently8 means atleast '< years at '(=c.At elevated temperatures, the storage *+, technologies. +ften this is used in redundant memory techniques where a spare column may be switched in to replace a

time will be reduced programming may be completed numerous times. The chips are usually housed in glassQlidded parkages to allow illumination by uv light.

Fig.'(.'; @-"erasable 1/!+* structure

E ectrica y Erasa( e Progra''a( e ROM

The electrically erasable programmable !+* #11/!+*% technology allows the electrical programming and erasure of *+, !+* cells. This type of programming is most popularly used today for *+,. A typical structure is shown in Fig.'(.'=.

Fig.'(.'= 11/!+* structure

Two transistors are typically used in a !+* cell. +ne is an access transistor while the other is the programmed transistor. A two"poly sandwich is again used in the programmed transistor with the control gate on the top. A very thin o0ide between the floating gate and the drain of the device allows the electrons to 7tunnel8 to or from the

floating gate #thus charging the gate o0ide% to turn the cell off or on respectively. The series A access transistor allows programming of cells. 11/!+* has a testability advantage over fused technologies. 1ach device can be fully tested before shipment. A range of !+* architectures have been used, including the normal C+! !+* structure and CAC2 structures. Progra''a( e Interconnect In a /A$, the device is programmed by changing the characteristics if the switching element. An alternative would be to program the routing. This has been demonstrated via a number of techniques including $aser /antography, where a laser lays down paths of metal under computer control. ommercially, programmable routing approaches are represented by products from Actel, Ruick $ogic, and other companies. The Actel field programmable Arrays are based on an element called a /$I 1 #programmable $ow"Impedance ircuit 1lement% or antifuse. An antifuse is normally high resistance #S'<<* %. +n application of appropriate programming voltages, the antifuse is changed permanently to a low"resistance structure #(<<"=<< %. The structure of an antifuse is shown in Fig.'(.'Fa. It consists of an +C+ #o0ide A nitride A o0ide% layer sand wielded between a polysilicon layer on top and an nK diffusion on the bottom. The Ruicklogic array is based on a structure called a -ia $ink, T which consists of a sandwich of material between metal ' and metal (. This is illustrated in Fig.'(.'Fb. The 7+C8 resistance of this structure is some what lower than that in Fig.'(.'Fa.

#a%

#b% Fig.'(.'F /rogrammable Inter connect structures #a% Antifuse T #b% -ia$ink T +ne chip architecture that uses the anti fuse is shown in Fig.'(.':. elements are arranged in rows separated by hori.ontal interconnect. $ogic Interconnect

permanently connected to the logic elements passes rustically. 9oth hori.ontal and restical segments are segmented into a variety of lengths. ,egments may be )oined by programming anti fuses. ertain special signals such as power and a clock line are routed globally to all logic. The logic elements are surrounded by IB+ pads and programming and diagnostic logic.

Fig. Actel F/3A chip architecture The structure of an Actel logic element shown in Fig.'(.'H. It consists of three input *@Ues and a C+! gate. This structure can implement all ( and > input logic functions and some ;" input functions. A latch may be implemented with one logic element, while a register requires two elements. The Ruick $ogic cell is shown in. In addition to the structure shown in Fig.'(.'H, it includes a resettable register and numerous logic gates. An interesting trade"off in these types of arrays is the granularity of the logic cell verses the amount of routing.

Actel logic cell

Ruick logic cell

The Actel programmable IB+ pad is shown in Fig.'(.(<. Two antifuses allow the configuration to operate as an input pad, output pad, or bidirectional pad. If the 1CA9$1 pin is not programmed, then the pad is bidiractional. If the 1CA9$1 antifuse to -22 is blown, the pad is an output, whereas if the - ,, antifuse is blown, the pad is an input. The isolation devices isolate the pad if necessary during programming and testing. A highly desirable feature of the Actel Architecture is the ability to observe any node in the chip using the series A pan transistors that are used for programming.

Fig. Actel IB+ /ad

At the time of writing, these arrays would implement ==< logic modules and :< IB+ modules. The speed of a particular circuit depends on the logic element speed and the delay through antifuse elements in any routing. A single logic module e0hibits a delay from :ns to '; ns #=- and (=o % depending on fan"out in a ( m technology. $ong route delays through many antifuses can range from '= ns to >= ns. 4ith smaller technologies, the logic module delays would decrease while the routing delays might decrease somewhat. *ore drastic reductions in the routing delays would come with lower 7on" resistance8 antifuses. If a >("bit adder is implemented in an Actel array, 'F< logic modules would be needed, and it would add in appro0imately F= ns. Thus, roughly >.= >("bit adders would fit in a single F/3A chip.

Re"rogra''a( e Gate Arrays

A further class of programmable device is the programmable #or reprogrammable% gate array. These may be further categori.ed into ad"hoc and structured arrays. The different versions of reprogrammable gate arrays are: The Uilin0 programmable 3ate Array, Algotroni0, oncurrent logic, etc. Uilin0 3ate array is an e0ample of an ad"hoc

array. 1g. U

><<< series. An e0ample of a regular programmable array is the

A$

'<(; from Algotroni0. The $I F<<< series is another e0ample of a regular array style F/3A. A detailed description about these versions is given in chapter ''. Su''ary This chapter has covered a broad spectrum of design issues that may be encountered when design designing useful for any kind of *+, chips. The structured design strategies are *+,"chip design method. The Application ,pecific Integrated

ircuits #A,I s% is also described in a detailed manner. A range of implementation options are given to give the reader an appreciation for the wide spectrum of solutions that are available today.