Unit 1

Short Answer Questions (2 marks)

1. Draw Y-chart.

Sol: The Y-chart consists of three domains of representation namely behavioral,

structural and geometrical layout domain.

2. What are the advantages of VLSI design process ?

Advantages of VLSI design process :

 1. Reduced size for circuits.

 2. Increased cost-effectiveness for devices.
 3. Improved performance in terms of the operating speed of circuits.
 4. Requires less power than discrete components.
 5. Higher device reliability.
 6. Requires less space and promotes miniaturization.

3. Define critical path.

 Sol: Thecritical path is defined as the path with the greatest delay between
an input and an output. Once the circuit timing has been determined, the
crucial path can be easily identified using the trace back method.
4. Define VLSI.
Sol: When the number of active devices per chip exceeds hundreds of
thousands, it is referred to as very large scale integration (VLSI). Almost all
current chips use the VLSI approach.
5. State Moore’s law in reference to VLSI design.
Ans. It states that the number of transistors on a microchip increases every
two years, while computer prices are cut in half.
6. Write down the applications of FPGA.

Ans. The applications of FPGA are:

 1. Digital signal processing

 2. Bio-informatics
 3. ASIC prototyping
 4. Medical imaging
7. What is the classification of IC packages ?

Ans. The classification of IC packages is as follows:

Dual In-line Packages (DIP)

Pin Grid Array (PGA) Packages
Chip Carrier Packages (CCP)
Quad Flat Packs (QFP)
Multi-Chip Modules (MCM).

8. What do you mean by regularity ?

Ans. Regularity implies that the hierarchical breakdown of a big system
should provide as many simple and related blocks as possible.
9. Define slack, clock jitter and clock skew?
 Ans. Slack: It is the difference between the required time and the arrival time. A positive slack at a
node indicates that the signal can be slowed down at that node till the slack is zero. Conversely,
negative slack at a node indicates that the signal must be speeded up to meet the arrival time.

Clock skew: It is the variation in clock signals due to different clock traversal path to the clock inputs
of different synchronous elements.

Clock jitter: It is the timing variation in clock signals.

10. What do you mean by Modularity ?

Ans. Modularity is another important aspect of hierarchical decomposition. It means that the
functional blocks must have well-defined interfaces and functionality. Modular design allows
different modules to be designed concurrently and also enables design reuse.

11. Enlist various IC technology?

Ans. “An integrated circuit (IC) is a small semiconductor-based electronic device consisting of
fabricated transistors, resistors and capacitors. Integrated circuits are the building blocks of most
electronic devices and equipment. An integrated circuit is also known as a chip or microchip.”

12. Explain critical path with example.

Ans. The critical path is defined as the path between an input and an output with the maximum delay.
Once the circuit timing has been computed, the critical path can easily be found by using a traceback
method. Critical paths are timing-sensitive functional paths, because of the timing of these paths is
critical, no additional gates are allowed to be added to the path, to prevent increasing the delay of the
critical path.

Long Question Answer

1. Draw the Y-chart and explain the VLSI design process. Mention its advantages.

Ans: The Gajski-Kuhn Y-chart is a model, which captures the considerations in designing semiconductor
devices. The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each of the domains can be
divided into levels of abstraction, using concentric rings. At the top level (outer ring), we consider the
architecture of the chip; at the lower levels (inner rings), we successively refine the design into finer
detailed implementation −Creating a structural description from a behavioral one is achieved
through the processes of high-level synthesis or logical synthesis. Creating a physical description from a
structural one is achieved through layout synthesis.

VLSI Design Flow:

The VLSI design process includes several steps: software requirements, architectural design, behavioral
or functional design, logical design, circuit design, physical design, exemplary design, fabrication and
packaging, and testing and packaging.
1. System specification: The objective of the desired final product is written in this step. During system
specification, the designated cost of the system, its performance, architecture, and how the system will
communicate with the external world are to be determined. During this step, the design specification
should be provided by the users or clients.

2. Architectural design: The basic architecture of the desired design must meet the system specifications
of the desired design. The architecture of the desired design is decided and the layout for the same is
designed by design engineers. Architectural design includes the integration of analog and mixed-signal
blocks, memory management, internal and external communication, power requirements, and choice of
process technology and layer stacks.
3. Functional design or Behavioural design: It consists of refining the design specification of the desired
design in order to design the functional behavior of the desired system. The main objective of this is to
generate design a high-performance architectural design within the cost requirements posed by the
specifications.

4. Logic Design: In this step, the structure of the desired design is added to the behavioral
representation of the desired design. The main specifications to be considered for logic design are logic
minimization, performance enhancement, and testability. Logic design must also consider the problems
associated with test vector generation, error detection, and error correction. Many logic synthesis tools
have been developed for the automation of the process of logic design.

5. Circuit Design: In this step, the logic blocks of the desired design are replaced by the electronic
circuits, which are consists of electronic devices such as resistors, capacitors, and transistors. Circuit
simulation of the desired design is done at this stage, in order to verify the timing behavior of the
desired system. Kirchhoff’s laws are used to know the behavior of the electronic circuit in terms of node
voltages and branch circuits. The result of integrodifferential equations is then solved in discrete- time.
SPICE is a well-known program for circuit simulation.

6. Physical Design: In this step, the actual layout of the desired system is done, where all the
components will be placed in the circuit and all these components are interconnected. The actual layout
of the desired system can affect the area, correctness, and performance of the final desired product.
The correctness of the chip is also controlled by the physical design. A circuit design that passes the test
of a circuit simulator may be faulty after it has been packaged. This is because of geometric design rule
errors. These design rules must be followed to ensure the correctness of the chip fabrication. Errors
such as short circuits, open circuits, open channels, etc may result if the design rules are not respected.

7. Fabrication: After the actual layout and verification of the desired design, the design is sent for
manufacturing. The handoff of the desired design to the manufacturing process is called tapeout.
Generation of the data for manufacturing is referred to as streaming out. The desired design is onto the
different layers of the design using the photolithographic process. ICs are manufactured on round silicon
wafers with a diameter from 200mm to 300mm, these ICs are then tested and are marked as either
functional or defective ICs.

8. Packaging and Testing: After fabrication of desired design, functional chips are then packed. Packaging
is configured early in the desired design process and the application along with the cost and form factor
requirements. Packaged types may include Dual In-Line Packaged (DIPs), Pin Grid Array (PGAs), and Ball
Grid Arrays (BGAs). After a die is positioned in the package cavity, its pins are connected to the pins of
the package, e.g., with wire bonding or solider bumps (flip-chip). The package of the desired design is
then sealed and then sent to the end-users or clients

 Importance of Design Flow in VLSI

The VLSI design flow is essential for several reasons:

I. Systematic Approach: It gives a defined approach to addressing the intricacies of designing ICs,
to the extent that each phase is detail-oriented.
 II. Error Detection and Correction: When the designing process is divided into stages, the mistakes
committed in the designing process are easily detected and corrected before the manufacturing
and development of the product is complete.
III. Performance Optimization: The nature of the design flow means that designs can be refined
over and over for greatest performance, and then further optimized to meet all the
requirements for the product.
IV. Cost Efficiency: One way cost management is achieved through efficient design flow because
during its implementation one is able to notice that there are some problems that could have
been foreseen at an early stage hence it means that one will not incur a lot of money in trying to
correct such mistakes in the later stages.

Q2. Explain the concept of design hierarchy with the help of example.
Ans.
A Design hierarchy:
1. The use of hierarchy involves dividing module into sub-modules until the complexity of the
smaller parts becomes manageable.
2. Similarly, the design of VLSI chip can be represented in three domains.
3. It is important for the simplicity of design that the hierarchies in different domains be
mapped. Fig. 1.4.1 shows the structural decomposition of a CMOS 2 bit adder into its
components.
4. Adder can be decomposed into 1 bit adders, separate carry and sum circuits and individual
logic gates.
5. The above partitioning provides a valuable guidance for realization of these blocks on the
chip. The approximate shape and area of each sub-module should be estimated in order to
provide a useful floor place.

2 Bit Adder
B. Regularity :
1. Regularity means that the hierarchical decomposition of a large system should
result in simple as well as similar blocks as much as possible.
2. Regularity can exist at all level of abstraction. For example, design of array structures
consisting of identical cells at transistor level and at gate level.
3. If the designer has a small library of basic building blocks, a number of different
functions can be constructed by using this principle.
4. Regularity usually reduces the number of different modules that need to be
designed and verified, at all levels of abstraction.
C. Modularity :
1. Modularity in design means that the various functional blocks which make up the
large system must have well-defined functions and interfaces.
2. Each block or module can be designed independent from each other such flexibility is
provided by modularity. All the blocks can be combined easily at the end of the design
process to form the large system.
3. The concepts of modularity enable the parallel process during the design.
D. Locality :
1. The concept of locality ensures that connections between module to module are
mostly between neighbouring modules, avoiding distance connections as much as
possible.
2. During interfacing each module in the system, make sure that the internals of each
module becomes unimportant to the exterior module.
3. Far-interconnections can be avoided as they provide long delays in the system. All the
time-delays operations should be performed locally, without the need to access far
placed modules.

Q3. What are the levels of abstraction ? Explain.

Ans: Abstraction is VLSI could be defined as the amount the information an entity is
hiding within it. Consider you computer for example(system) , its at a higher level of
abstraction, at the next level we have boards(mother board, cd drive, disks,etc) , next
we have chip level( cpu etc), inside those chips (Now we are talking about VLSI
abstraction) we have four levels of abstraction namely:
I. Register level
II. Gate level(logic gates, mux, decoder etc)
III. circuit level (transistor)
IV. layout level (geometry )
i. Behavioral or algorithmic level : This is the highest level of abstraction. A module can
be implemented in terms of the design algorithm. The designer no need to have any
knowledge of hardware implementation.
ii. Data flow level: In this level, the module is designed by specifying the data flow.
Designer must how data flows between various registers of the design.
iii. Gate level : The module is implemented in terms of logic gates and interconnections
between these gates. Designer should know the gate- level diagram of the design.
iv. Switch level : This is the lowest level of abstraction. The design is implemented using
switches/transistors. Designer requires the knowledge of switch-level implementation
details.
Q4. Discuss the hierarchy of various semiconductors with Moore’s law. Draw the Y-chart
and explain the VLSI design process.
Ans. Moore’s law isn’t really a law in the legal sense or even a proven theory in the
scientific sense (such as E = mc2). Rather, it was an observation by the late Gordon
Moore in 1965 while he was working at Fairchild Semiconductor: the number of
transistors on a microchip (as they were called in 1965) doubled about every year.
Moore went on to co-found Intel Corporation and his observation became the driving
force behind the semiconductor technology revolution at Intel and elsewhere.

The IC was invented in February 1959 by Jack Kilby ofTexas Instrument. The planar
version of the IC was developed by Robert Noyce at Fairchild in July 1959. Since then the
evolution of this technology' has been extremely fast paced.
One way to gauge the process of the field is to look at the complexity of IC’s as a
function of time.
When we plot log of the component count as a function of time, we get a straight line,
indicating that there has been an exponential growth in the complexity of chips over
three decades.
The component count has roughly doubled every 18 months, as was noted early by
Gordon Moore. This regular doubling is known as Moore’s law.
 The main factor that has enabled this increase of complexity is the ability to shrink or
scale devices.
Clearly, one can pack a larger number of components with greater functionality on an IC
if they are smaller; also being advantageous in terms of faster IC’s which consume less
power.

It can be observed that in terms of transistor count, logic chips contain significantly
fewer transistors in any given years mainly due to large consumption of chip area for
complex interconnects.
Memory circuits are highly regular and thus more cells can be integrated with much
less area for interconnects.
The demand for digital CMOS IC’s will continue to be strong due to salient features such
as low power, reliable performance, circuit techniques for high speed such as using
dynamic circuits.
It is now projected that the minimum feature size in CMOS ICs can decrease up to 35 nm
within a decade.
Bipolar and gallium arsenide (GaAs) circuits have been used for very high speed circuits,
and this practice may continue. MMIC’s, GaAs MESFET technology has been highly
successful.
As long as the downward scaling of CMOS technology remains strong, other
technologies are likely to remain the technology of tomorrow.
Q3. What are the VLSI design styles ? Explain any one.
Ans: LSI design styles are a set of different methodologies and approaches to design ICs.
The design styles can be implemented either during the physical implementation of the
design or in the field of the application. The article lists a few VLSI design styles below.

FPGA (Field Programmable Gate Array)

An FPGA contains an array of configurable logic blocks, input/output buffers, and
programmable interconnects. There are thousands of logic gates in an FPGA that have
programmable interconnects. The specialty of FPGA is the flexibility to customize and
reconfigure the hardware multiple times after fabrication. This is because no physical
manufacturing step is needed for FPGA customization. Hence, FPGA is a “field-
programmable” IC.

The gates of MOS pass transistors are connected to the output terminals of RAM cells
inside the FPGA structure. By programming the RAM cells and setting up configurable
switches, an FPGA can be reprogrammed. In simple words, a hardware description
language (HDL) can program, and a Boolean function can implement an FPGA VLSI
design style as per the system requirements.

The advantages of FPGAs include clock frequencies up to 800 MHz, fast prototyping, fast
development, customization, ease of reconfiguration, and turnaround time. Typically, a
modern car contains 10-12 FPGAs.

Gate Array Design

Gate array design implementation requires two processes during the manufacturing
process. After initial deep processing steps, the standard mask generates an array of
uncommitted pMOS and nMOS transistors on the chip that can be customized.
Secondly, there is a customization option in the process of metallization. As discussed in
our article "Semiconductor circuit design: key chemical procedures", the process of
embedding metal interconnects is an end procedure of the fabrication process.
Programming custom metal masks can form basic logic gates in the chip.
A gate array design is a set of capabilities between a flexible FPGA and the reliability of
fully custom designs. Unlike FPGAs, gate array design cannot be reconfigured after
manufacturing. The customization option offers reprogrammability during the
manufacturing process. Once the gate array design chip is manufactured, changes to
hardware design are challenging. The advantages of gate array design are high chip
utilization factor, chip speed, and short turnaround time.

Full Custom Design

In a fully custom-designed chip, each mask is designed separately and is unique. In
simple words, each transistor and interconnect is designed and placed by the teams. A
designer is able to design and place up to 10 transistors every day. A single-cell design is
not stored in the library and is not used again. The benefit of choosing a fully custom
design achieving optimal performance and control over the design.

However, it makes fully custom design costly and time-consuming. The drastic increase
in design cycle time may exceed the lifetime technological window of the chip, require
extensive designer time, and spoil the marketing budget. To overcome cost and time,
fully custom designs for memory-based chips are designed once and reused repeatedly
in multiple applications. Logic-based chips can use some portion of a fully custom design
style and integrate it with other designs to form a hybrid design. New ASIC technologies
are designed with a fully custom design.
Standard Cell Design
A standard cell-based design, or poly-cell design, overcomes the limitations of high cost
and design time for fully custom cell design. The standard-designed cell requires
designers to develop a custom-masked cell. The difference between a standard cell-
based design and a fully custom design is storage. While a fully custom design requires
designing a new mask, a standard cell design develops and stores the mask in a library.

The standard pre-designed and pre-characterised library may contain logic gates like
NAND, NOR, XOR, etc, along with inverters, adders, multipliers, flip-flops, and various
other digital electronic components. The floor plan for standard cells places cells with a
fixed height together to form a row. Several logic gates can be implemented multiple
times in this design style. The logic cell has to be extracted from the library and placed in
the row to interconnect with neighboring cells to attain a desirable area, speed, power,
and cost.
Q4. What are the types of common IC packages ? Explain.
Ans. The integrated circuits (ICs) are fabricated on a wafer in a batch. The bunch of
wafers, processed simultaneously, is called a lot. From the processed wafer individual
ICs called die are separated out by cutting the wafers. A die is then packaged in a plastic
or ceramic compound structure to form an IC chip. Figure 1.11 illustrates a schematic
view of the lot, wafer, die. and IC chip. The IC package is a cover to the internal core die
which supports the die, and protects the die from damage. In addition to protection, the
package serves the following important functions: it provides electrical signal exchange
between the core die and the outside environment; it acts as a medium for heat
dissipation; it provides power to the die. But with circuits approaching higher
frequencies, the function of a package is not just limited to the above-mentioned
functions. Initially, the electrical performance of the packaged IC chip was limited by the
die itself and very little because of the package. But with rise in the operating range of
frequency, the parasitics associated with the package started affecting the performance
of the IC. A variety of requirements for smaller, lighter, faster, and less expensive
electronic products have not only led to better fabrication techniques, but also to better
packaging techniques. With increase in the frequency range of operation, the electrical
performance of different packages decides the packaging used for a particular
application.
Types of IC Packages
The IC packages are mainly classified into two types:
> Pin-through-hole (PTH) package pins arc extended in the vertical direction so that
they can be inserted through holes in the circuit board.
> Surface-mount technology (SMT) package pins are extended in the horizontal
direction so that they can be mounted on the surface of the circuit board.
Pin-through-hole Package
In the PTH package, the pins are inserted into holes in the printed circuit board (PCB)
and soldered in place from the opposite side of the board. It can also be inserted in the
socket installed on the PCB. The PTH packages can be classified based on the location of
the pins as follows:
> Single side: Single side package has pins over a single side. The pins can be positioned
in-line or zig-zag. So, again depending on pin positions they are classified as
> SIP (single in-line package)
> ZIP (zig-zag in-line package)
> Dual side: In the dual side package, the pins are located on both sides of the package
in in-line pattern, hence the name DIP (dual in-line package).
> Full surface: Full surface package has pins located in arrays over the four sides of the
package. This type of package is called PGA (pin grid array).
B. Surface-mount Technology Package
The surface-mount technology (SMT) packages have pins that are soldered directly onto
the surface of the circuit board. These packages do not require any hole in the circuit
board. SMT packages are preferred over PTH packages due to many of their advantages,
such as
> SMT package can be mounted on both sides of the circuit board. They arc small in
dimensions.
> Their package parasitics are reduced over PTH packages. > They increase circuit
board wiring density.
> Manufacturing is easier than PTH.
SMT packages are classified into several types based on the pin locations

Types of Packages Based on Package Material

Depending on the material used for packaging, the packages are classified into the
following two types:
> Plastic package: Die-bonding and wire-bonding are used to connect the die bond pad
toa metal lead-frame. The encapsulation is done by an injection of moulded plastic.
These packages arc inexpensive, but they have very high thermal resistance and absorb
moisture. They are prone to early device failure due to package cracking, and hence are
used only for low-cost applications.
> Ceramic package: In the ceramic packages there is no lead-frame. The metal leads arc
directly soldered on the package, and separated by ceramic (AI2O3) layers. These
packages are costlier than the plastic packages, and hence used for high-cost
applications.
Q5. Draw and explain the working of CMOS inverter with its transfer characteristics.
CMOS, short for Complementary Metal-Oxide-Semiconductor, is the type of silicon chip
electronics technology that has been used in many devices, which handle signal passing
in their circuits.
For many electronic devices, a CMOS serves as the brain. It is a small but very significant
part that regulates the flow of signals through circuits

Figure-1 shows the schematic of a CMOS inverter. As we can see it have two transistors
a pull-up pMOS transistor(T1) and a pull-down nMOS transistor(T2). When the input
voltage Vin is equal to Vdd we get an output voltage of Vss(mostly equal to 0) and vice
versa. Since it inverts the logic level of input this circuit is called an inverter. Figure-2
shows the voltage transfer characteristics(VTC) or DC characteristics of an inverter.
The VTC is divided into five regions(1-5) for easy of understanding. The above shown curve is
possible when both T1 and T2 are matched for optimum operation. Optimum operation is
achieved when Vin = Vdd/2 we get Vout = Vdd/2 . This can be achieved by adjusting width and
length of both T1 and T2 as other parameters like mobility, oxide capacitance vary between
different technologies.

Region-1
In this region the input is in the range of (0,Vtn). Since the input voltage is less than Vtn, the NMOS is in cutoff
region. No current flows from Vdd to Vss, The entire Vdd will appear at the Output terminal.
 NMOS is in cutoff as Vgs < Vtn

 PMOS is in linear as Vgsp < Vtp and Vdsp > Vgsp -Vtp.

 Zero current flows from supply voltage and the power dissipation is zero.

Region-2
In this region the input is in the range of (Vtn,Vdd/2). Since the input voltage is greater than Vtn the NMOS is
conducting and it jumps to saturation as it has large Vds across it(Vout is high). PMOS still remains in the linear
region.
 NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

 PMOS is in linear region as Vdsp > Vgsp -Vtp.

 since both the transistors are conducting some amount of current flows from supply in this region.
Region-3
In this region the input voltage is Vdd/2. At this point the output voltage is also Vdd/2 as one can see in figure-
2. At this voltage both the NMOS and PMOS are in saturation and the output drops drastically from Vdd to
Vdd/2. At this point a large amount of current flows from the supply. Most of the power consumed in CMOS
inverter is at this point. So care should be taken that the Input should not stay at Vdd/2 for more amount of
time.
 NMOS is in saturation as Vgs > Vtn and Vout >Vin - Vtn.

 PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

 Large amount of current is drawn from supply and hence large power dissipation.

Region-4
In this region the input voltage is in the range of (Vdd/2 , Vdd-Vtp). Here the PMOS remains in saturation
as Vout < Vin - Vtp and Vgsp < Vtp. But the NMOS moves from saturation to linear region since the drain to
source voltage now is less than Vgsn-Vtn.
 NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

 PMOS is in saturation as Vgsp < Vtp and Vdsp < Vgsp -Vtp.

 A medium amount of current is drawn as NMOS is in linear region and power dissipation is low.

Region-5
In this region the input voltage is in the range of (Vdd-Vtp,Vdd). Here the PMOS moves from saturation to cutoff
as the Vgsp is so high that Vgsp > Vtp. The NMOS still remains in linear as the drain to source voltage now is
less than Vgsn-Vtn.
 NMOS is in linear as Vgs > Vtn and Vout < Vin - Vtn.

 PMOS is in cutoff as Vgsp > Vtp.

 Zero current flows from the supply and so the power dissipation is zero.

Q6. Implement the CMOS logic for the following Boolean expression.

i. Y=(A+B + C)D
ii. Y=(A + B + C)(D+E)-F
Ans.
Q7. Implement the Boolean expression Y = AB + (C + D) (E + F) + (G + H).

Ans.
Q. 8 Explain propagation delay time?

Ans. Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %(
80%) of its maximum value. This is known as “rise time”.
Similarly “fall time” can be defined as the time taken by a signal to fall from 90 %( 80%) to the 10 %(
20%) of its maximum value. Transition is the time it takes for the pin to change state.

Setting Transition Time Constraints

The above theoretical definitions are to be applied on practical designs. Now, the transition time of a
net becomes the time required for its driving pin to change logic values (from 10 %( 20%) to the 90 %(
80%) of its maximum value). This transition time used foe delay calculations are based on the timing
library.

1. max_transition : This attribute is applied to each output of a cell. During optimization, Design
Compiler tries to make the transition time of each net less than the value of themax_transition
attribute.

2. set_max_transition: This command is used to change the maximum transition time restriction
specified in a technology library.

Propagation Delay

Propagation delay is the time required for a signal to propagate through a gate or net. Hence if it is cell,
you can call it as “Gate or Cell Delay” or if it is net you can call it as “Net Delay” Propagation delay of a
gate or cell is the time it takes for a signal at the input pin to affect the output signal at output pin. For
any gate propagation delay is measured between 50% of input transition to the corresponding 50% of
output transition.

Q9. Explain Clock Skew.

Ans. Skew is the time delta between the actual and expected arrival time of a clock signal. Skew
can be either extrinsic or intrinsic. The latter is internal to the driver (generator circuitry) and
defined as the difference in propagation delays between the device outputs. On the other
hand, extrinsic skew is the time difference due to unbalanced trace lengths and/or output
loading.
Propagation Delay
Propagation delay (tpd) is the time between the specified reference points on the input and
output voltage waveforms with the output changing from one defined level (high-to-low) to the
other (low-to-high) defined level (tpd = tPHL or tPLH)
2.1 Propagation Delay Time, High-to-Low Level Output Propagation delay time, high-to-low
level output (tPHL) is the time between the specified reference points on the input and output
voltage waveforms with the output changing from the defined high level to the defined low
level.
2.2 Propagation Delay Time, Low-to-High Level Output Propagation delay time, low-to-high
level output (tPLH) is the time between the specified reference points on the input and output
voltage waveforms with the output changing from the defined low level to the defined high
level.
Types of Clock Skew :

 Positive Skew –
This occurs when the receiving register receives the clock pulse later than it is
required.

 Negative Skew –
This occurs when the receiving register receives the clock pulse earlier than
required.

Q 10. Find the worst path and check if it meets a cycle time of T=12?

Ans.
 Unit 2
Short Question Answer (2 Marks)
Q1. Define the term Interconnect.

Ans. The wires linking transistors together are called interconnect.

Q2. Define the term interconnect impact in brief.

Ans. Interconnect impact examines the delay, energy, and noise impact of cables that
electrically connect two or more circuit parts.

Q3. Define the term interconnect delay.

Ans. While signal propagation via wires limits state-of-the-art circuit speed,
interconnection delay is the fundamental performance metric for wires.

Q4. What do you mean by lumped RC model ?

Ans. A basic approach combines the total wire resistance of each wire segment into a
single R and the capacitance into a single C. The lumped RC model is a simple model.

Q5. Define RC delay model.

Ans. The RC delay model approximates a switching transistor with an effective

resistance and allows for delay estimation via arithmetic rather than differential
equations.

Q6. Estimate tpd for a unit inverter driving m identical unit inverters.

Ans.1. Fig. shows an equivalent circuit for the falling transition.

  2. Since, each load inverter presents 3C units of gate capacitance, therefore total
gate capacitance = 3 mC
 3. Parasitic capacitance at output node = 3C
 4. The resistance is R, so the Elmore delay, tpd = (3 + 3m) RC
Q7. Define logical effort with example.
Ans. The logical effort of a gate is defined as the ratio of the gate’s input capacitance to
the input capacitance of an inverter capable of delivering the same output current.

Q8. What is parasitic delay ?

Ans. A gate’s parasitic delay is the time it takes to drive zero load. It is possible to
estimate it using RC delay models.

Q9. Define the fanout of the gate.

Ans. The fanout of the gate, h, is the ratio of the load capacitance to the input
capacitance.

Q10. What is Miller effect ?

Ans. If the inverter is biased in its linear region near VDD/2, the Cgd is multiplied by the
large gain of the inverter. This is known as the Miller effect.

Q11. What do you mean by scaling ? Also write its techniques.

Ans.
  1. Scaling of MOS transistors is concerned with the gradual reduction of overall
device dimensions as permitted by available technology while keeping the
geometric ratios present in larger devices.
 2. There are two basic types of size-reduction techniques :
 i. Full scaling (also called constant-field scaling) and
 ii. Constant-voltage scaling.
Q12. How to compute the resistance of wire or interconnect ?

Ans. The resistance of a wire is proportional to its length L and inversely proportional to its cross- section
A. The resistance of a rectangular conductor as shown in figure below can be expressed as

Long Question Answer

Q1. What are interconnecting models ? Explain any two of them in brief.

Ans. A Interconnect models: The wires linking the transistors together are called interconnect.
Interconnect models are :

Resistor

Capacitor

Inductor.

B. Interconnect Parameters Advantages of interconnect modeling: The interconnect modeling can be

used efficiently during high-level design space exploration, interconnect-driven design planning, and
synthesis- and timing-driven placement to ensure design convergence for deep sub-micrometer designs.
C. Capacitance model: The wire capacitance has two major components: the parallel plate capacitance
of the bottom of the wire to ground and the fringing capacitance arising from fringing fields along the
edge of a conductor with finite thickness. In addition, a wire adjacent to a second wire on the same layer
can exhibit capacitance to that neighbour.

The fringing capacitance is more complicated to compute. One intuitively appealing approximation
treats a lone conductor above a ground plane as a rectangular middle section with two hemispherical
end capacitance.
The total capacitance is assumed to be the sum of a parallel plate capacitor of width w -t/2 and a
cylindrical capacitor of radius t/2. This results in an expression for the capacitance that is accurate within
10 % for aspect ratios less than 2 and t = h

An empirical formula that is computationally efficient and relatively accurate is

A cross-section of the model used for capacitance upper bound calculations is shown

Q2. How to model the inductance of wires ?

Ans.
Q3. Write a short note on skin effect.

Ans. kin effect is a phenomenon that affects the performance of conductors carrying alternating current
(AC). Unlike direct current (DC), which distributes the current evenly throughout the conductor, AC
current causes non-uniform current distribution on the conductor’s surface. This article will explore the
factors influencing skin effect and its impact on conductor resistance. By understanding these factors,
we can optimize conductor design and minimize the adverse effects on the skin effect.
Factors Affecting Skin Effect
Frequency plays a important role in the magnitude of skin effects. As the frequency increases, the
skin effect becomes more pronounced. Conductors carrying radio frequency (RF) signals experience
a significant skin effect, leading to a substantial increase in resistance. This phenomenon
necessitates the implementation of remedial measures to mitigate its impact.

Conductor Shape The shape of the conductor also influences the skin effect. Solid conductors have a
higher surface area compared to stranded conductors, resulting in a more pronounced skin effect.
Consequently, stranded conductors are favored in applications where minimizing the skin effect is
critical.

Conductor Diameter Skin effect is directly proportional to the diameter of the conductor. With larger
diameters, the skin effect becomes more prominent. Therefore, when designing conductors,
consideration should be given to minimizing diameter to mitigate the impact of skin effect.

Material Permeability Permeability, a material property associated with magnetic field formation,
affects the skin effect. Materials with higher permeability exhibit a more significant skin effect. This
correlation arises from the higher permeability material’s ability to generate a stronger magnetic field
and subsequently increase self-inductance. The resulting higher reactive impedance forces current
to flow primarily on the conductor’s surface

Q4. Explain the Elmore delay model with suitable RC networks. Mention its merits.

Ans. A Lumped RC model: A first approach lumps the total wire resistance of each wire segment into one
single R and similarly combines the capacitance into a single capacitor C. This simple model, called the
lumped RC model. B. Register capacitor network (Elmore delay model): Consider the resistor-capacitor
network of Fig.

The result of this circuit topology is that there exists a unique resistive path between the source node s
and any node i of the network. The total resistance along this path is called the path resistance Ru. For
example, the path resistance between the source node s and node 4 is:
The shared path resistance Rik, which represents the resistance shared among the paths from the root
node s to nodes k and i:

Assume now that each of the N nodes of the network is initially discharged to GND, and that a step input
is applied at node s at time t = 0. The Elmore delay at node i is then given by the following expression:

C. Merits of Elmore delay model:

1.Simple closed-form expression.

2.Useful for interconnect optimization.

3.Upper bound of 50 % delay.

4. High fidelity.

Q5. Draw and explain the working of Lumped 7?C-model for interconnects.

Ans. When the physical dimension, in particular, the length, of a wire channel is much smaller as
compared with the wavelength of the signal passing through the channel, the channel can be treated as
a lumped element with its characteristics depicted by a low-pass RC network, as shown in:

where Ca is the area capacitance per unit area and Cf is the fringe capacitance per unit length of the
wire channel.

A more rigorous criterion on whether lumped models should be used to characterize the behavior of
channels is determined by comparing the round-trip time that the signal travels along the channels,
denoted by 2t where r is the time for the signal to travel from one end of the channel to the other, and
the rise time of the signal tr.

If 2r < tr, lumped models should be used. Otherwise, distributed models should be used.

Q6. Explain distributed RC model.

Ans. A wire is a distributed circuit with a resistance and capacitance per unit length. Its behavior can be
approximated with a number of lumped elements. Three standard approximations are the L-model, x-
model, and T-model, so named because of their shapes. Fig. shows how a distributed RC circuit is
equivalent to N distributed RC segments of proportionally smaller resistance and capacitance, and how
these segments can be modeled with lumped elements.

As the number of segments approaches infinity, the lumped approximation will converge with true
distributed circuit. The L-model is a poor choice because a large number of segments are required for
accurate results. The 7t-model is much better, three segments are sufficient to give results accurate to 3
%. The T-model is comparable to the n-model, but produces a circuit with one more node that is slower
to solve by hand or with a circuit simulator. Therefore, it is common practice to model long wires with a
3-5 segment n-model for simulation.

Q7. Compute the step response (or transient response) of an inverter.

Ans. The most fundamental way to compute delay is to develop a physical model of the circuit of
interest, write a differential equation describing the output voltage as a function of input voltage and
time, and solve the equation. The solution of the differential equation is called the transient response,
and the delay is the time when the output reaches VDD /2. The differential equation is based on
charging or discharging of the capacitances in the circuit. The circuit takes time to switch because the
capacitance cannot change its voltage instantaneously. If capacitance C is charged with a current I, the
voltage on the capacitor varies as: I = C dV dt Every real circuit has some capacitance. In an integrated
circuit, it typically consists of the gate capacitance of the load along with the diffusion capacitance of the
driver’s own transistors, . As will be explored further in Section , wires that connect transistors together
often contribute the majority of the capacitance. The transistor current depends on the input (gate) and
output (source/drain) voltages. To illustrate these points, consider computing the step response of an
inverter. Figure 4.3(a) shows an inverter X1 driving another inverter X2 at the end of a wire. Suppose a
voltage step from 0 to VDD is applied to node A and we wish to compute the propagation delay, tpdf ,
through X1, i.e., the delay from the input step until node B crosses VDD/2. These capacitances are
annotated on Figure 4.3(b). There are diffusion capacitances between the drain and body of each
transistor and between the source and body of each transistor : Cdb and Csb . The gate capacitance Cgs
of the transistors in X2 are part of the load. The wire capacitance is also part of the load. The gate
capacitance of the transistors in X1 and the diffusion capacitance of the transistors in X2 do not matter
because they do not connect to node B. The source-to-body capacitors Csbn1 and Csbp1 have both
terminals tied to constant voltages and thus do not contribute to the switching capacitance. It is also
irrelevant whether the second terminal of each capacitor connects to ground or power because both are
constant supplies, so for the sake of simplicity , we can draw all of the capacitors as if they are
connected to ground . Figure shows the equivalent circuit diagram in which all the capacitances are
lumped into a single Cout. Before the voltage step is applied, A = 0. N1 is OFF, P1 is ON, and B = VDD.
After the step, A = 1. N1 turns ON and P 1 turns OFF and B drops toward 0. The rate of change of the
voltage VB at node B depends on the output capacitance and on the current through N1.

Suppose the transistors obey the long-channel models. The current depends on whether N1 is in the
linear or saturation regime. The gate is at VDD, the source is at 0, and the drain is at VB. Thus, Vgs = VDD
and Vds = VB. Initially , Vds = VDD > Vgs – Vt , so N1 is in saturation . As VB falls below VDD – Vt , N 1
enters the linear regime . Substituting EQ and rearranging, we find the differential equation governing
VB.
Q8. How to estimate the logical effort and parasitic delay ?

Ans. A Logical effort:

A Logical effort of a gate is defined as the ratio of the input capacitance of the gate to the input
capacitance of an inverter that can deliver the same output current. Logical effort indicates how much
worse a gate is at producing output current as compared to an inverter, given that each input of the
gate may only present as much input capacitance as the inverter. Fig. 2.14.1 shows inverter, 3-input
NAND, and 3-input NOR gates with transistors widths chosen to achieve unit resistance assuming pMOS
transistors have twice the resistance of nMOS transistors. The inverter presents three units of input
capacitance. The NAND presents five units of capacitance on each input, so the logical effort is 5/3.
Similarly, the NOR presents seven units of capacitance, so the logical effort is 7/3. This matches our
expectation that NANDs are better than NORs because NORs have slow pMOS transistors in series.

B. Parasitic Delay

The parasitic delay of a gate is the delay of the gate when it drives zero load. It can be estimated with RC
delay models. A crude method good for hand calculations is to count only diffusion capacitance on the
output node. For example, consider the gates in Fig. 2.14.1; assuming each transistor on the output
node has its own drain diffusion contact. Transistor widths were chosen to give a resistance of R in each
gate. The inverter has three units of diffusion capacitance on the output, so the parasitic delay is 3/RC =
t. In other words, the normalized parasitic delay is 1. In general, we will call the normalized parasitic
delay Pinv * Pinv is the ratio of diffusion capacitance to gate capacitance in a particular process.

The parasitic delay also depends on the ratio of diffusion capacitance to gate capacitance.

C. Electrical effort:

The effort delay of 4(b/K)C = 4bC depends on the ratio (b) of external load capacitance to input
capacitance and thus charges with transistor widths. The factor 4 is by the complexity of the gate. The
capacitance ratio is called the electrical effort.

A Logical effort of paths :

Designers often need to choose the fastest circuit topology and gate sizes for a particular logic function
and to estimate the delay of the design. Logical effort provides a simple method “on the back of an
envelope” to choose the best topology and number of stages of logic for a function. Based on the linear
delay model, it allows the designer to quickly estimate the best number of stages for a path, the
minimum possible delay for the given topology, and the gate sizes that achieve this delay.

B. Limitations of logical effort:

Logical effort does not account for interconnect. Logical effort is most applicable to high-speed circuits
with regular layouts where routing delay does not dominate. Such structures include adders, multipliers,
memories, and other data paths and arrays. Logical effort explains how to design a critical path for
maximum speed, but not how to design an entire circuit for minimum area or power given a fixed speed
constraint. Paths with non-uniform branching or reconvergent fanout are difficult to analyze by hand.
The linear delay model fails to capture the effect of input slope. Fortunately, edge rates tend to be
about equal in well-designed circuits with equal effort delay per stage.
Unit 3

Short Questions Answer (2 Marks)

Q1. Write the properties of dynamic circuit.

Ans.

 1. Dynamic logic has higher speed than equivalent static family.

 2. It occupies less area.
 3. It is non-ratioed.
 4. Dynamic logic always require clock.
Q2. Bring out the drawbacks of dynamic logic.

Ans. Drawbacks of dynamic logic are :

 1. Always require clocks.

 2. Design is more difficult.
Q3. Mention the advantages of dynamic logic circuits over static logic circuits.

Ans. In general, dynamic logic implementation of complex functions requires less silicon
area than static logic implementation.

Q4. Write the classification of high performance dynamic CMOS circuits.

Ans. 1. Domino CMOS circuits.

2. NORA CMOS circuits.

3. Zipper CMOS circuits.

Q5. Write short notes on zipper CMOS circuits.

Ans. With the exception of the clock signals, the basic circuit architecture of zipper
CMOS is basically identical to that of NORA CMOS. The zipper CMOS clock signal
architecture necessitates the development of somewhat different clock signals for
precharge and pull-down transistors.

Q6. Write the disadvantages of NORA CMOS logic circuit. How can be eliminated
it.
Ans. Charge sharing and leakage are also issues with NORA CMOS. A circuit
approach known as Zipper CMOS can be utilised to overcome dynamic charge sharing
and soft node leakage.

Q7. What are the advantages of NORA CMOS logic circuit ?

Ans. Advantages of NORA CMOS logic circuit are:

 1. Static CMOS inverter is not required at the output of every dynamic logic
state.
 2. Compatible with domino CMOS logic.
 3. It allows pipelined system architecture.
Q8. Enlist the properties of domino logic gates.

Ans. Properties of domino logic gates are:

 1. Each gate requires N + 4 transistors.

 2. Logic evaluation propagates as falling Dominoes hence minimum evaluation
period is determined by the logic depth.
 3. Inputs must be stable (only one rising transition) during the evaluation period.
 4. Gates are ratioless and non-inverting.
Q9. What are the different types of sequential CMOS circuit?

Ans. Sequential CMOS circuit can be classified into three main groups :

 i. Bistable
 ii. Monostable
 iii. Astable
Q10. What do you mean by bistable circuit ?

Ans. Bistable circuits contain two table states or operation modes that can be achieved
given specific input and output conditions.

Q11. Draw the diagram of SR latch based on NOR gates.

Ans.
Q12. What are the disadvantage of SR latch ?

Ans. The disadvantage of an SR latch is that when both S and R are high, its output
state becomes indeterminant.

Q13 Explain the dynamic CMOS design.

Ans:
Dynamic CMOS
Dynamic CMOS is a digital circuit. It has a single clock signal. It helps the system to
execute the pre charge operation. The capacitors of the dynamic CMOS have ability to
generate high-intensity performance with low power consumption. The dynamic
CMOS relay on continuous electricity to maintain all functions.
Characteristics of Dynamic CMOS
Here are the major characteristics of Dynamic CMOS as mentioned below.
 Dynamic CMOS can perform faster switching. These circuits are designed to
develop high-intensity systems where increase capacity and higher speed are
needed.
 The dynamic CMOS consumes power during the switching time. The circuit does
not need continuous power to maintain the logic state.
 Dynamic CMOS have the capacitors to save the charge and the logic state can be
determined by the capacitors only.
 This type of CMOS needs a CLK signal to refresh the stored charge in a certain
time to get an accurate result.
 The stored change may leak as the circuits of the dynamic CMOS are more
sensitive to knowledge and other factors.
Advantages of Dynamic CMOS
 Dynamic CMOS circuits can achieve higher speeds compared to static CMOS due
to the reduced number of transistors.
 Dynamic CMOS circuits often require less area on the silicon chip, allowing for
higher density and more compact designs.
 Dynamic CMOS can be more power-efficient in high-speed applications,
particularly when the circuit operates at high frequencies.
Disadvantages of Dynamic CMOS
 Dynamic CMOS circuits can consume more power during the switching phase.
 Dynamic circuits can be more complex to design.
 It requires precise timing and careful management of charge storage.
 Dynamic CMOS circuits are more susceptible to noise, which can lead to data
corruption.
Applications of Dynamic CMOS
 High-speed processors
 DRAM (Dynamic Random-Access Memory)
 High-density logic circuits
 Advanced digital systems requiring fast processing
Block Diagram Of Dynamic CMOS
Here is the bloc diagram of the dynamic CMOS as mentioned below.

Difference Between Static and Dynamic CMOS

Dynamic
Feature Static CMOS CMOS

Lower average
Power Low static power consumption. power
Consumption consumption.
 Dynamic
Feature Static CMOS CMOS

Speed Moderate speed. High speed.

More complex
design with
More transistors per gate. timing and
charge
Complexity management.

Transistor
Higher. Lower.
Count

Noise Lower noise

High noise immunity due to stable logic levels.
Immunity immunity.

Relies on
Charge Does not rely on charge storage. capacitor
Storage charge storage.

Clock Clock-
Not clock-dependent.
Dependency dependent.

Primarily
Power Static power dissipation is minimal. dynamic power
Dissipation dissipation.

Higher leakage
current due to
Very low leakage current.
Leakage charge storage
Current in capacitors.

More complex
design with
Easier to design and implement. timing and
Design refresh
Complexity requirements.

Use in
Used in SRAM. Used in DRAM.
Memory
 Dynamic
Feature Static CMOS CMOS

High-speed
logic circuits,
high-
General-purpose logic performance
gates, microprocessors, microcontrollers, digital processors,
logic circuits making. DRAM,
pipelined
architecture
Applications making.

Requires
Refresh No refresh required. periodic
Requirement refresh.

Power Less tolerant to

Supply Tolerant to power supply variations. power supply
Variation variations.

Q 14. Explain the behavior of pass transistor in dynamic CMOS logic implementation (AKTU 20-21)

Ans:

In pass-transistor circuits, inputs are applied to the source/drain diffusion terminals.
These circuits build switches using either nMOS pass transistors or parallel pairs of nMOS and
pMOS transistors called as transmission gates.
Q15 Estimate the equation for the charge storage and charge leakage at the soft node capacitance
CX?
Ans:
Q.16. Explain the term voltage bootstrapping in CMOS logic with suitable example (AKTU 22-23)
Ans.

Q. 17. What are the noise considerations in dynamic design ?

Ans: Noise considerations in dynamic design are :
i. Charge leakage :
1. The operation of the dynamic logic depends on the principles of dynamically storing a charge on the
output node (capacitor).
2. Due to leakage currents, this charge gradually leaks away, resulting eventually in malfunctioning ofthe
gate.
Q18. Explain the domino CMOS logic. Also discuss the cascaded domino CMOS logic structures.
(AKTU 18-19, 22-23)
Ans:
Q. 19: Describe the basic principle of operation of NP domino logic. )AKTU 18-19, 19-20,
22-23)
Ans:
The HI-skew inverting static gates are replaced with predischarged dynamic gates using
pMOS logic.
A footed dynamic p-logic NAND gate is shown in Figure (b). When ф is 0, the first and third
stages precharge high while the second stage predischarges low.
When ф rises, all the stages evaluate. Domino connections are possible, as shown in Figure 
(c).
The design style is called NP Domino or NORA Domino (NO RAce).


 NORA has two major drawbacks.
(i) The logical effort of footed p-logic gates is worse than that of HI-
(ii) skew gates.NORA is extremely susceptible to noise.

In an ordinary dynamic gate, the input has a low noise margin (about Vt ), but is strongly
driven by a static CMOS gate.
The floating dynamic output is more prone to noise from coupling and charge sharing, but
drives another static CMOS gate with a larger noise margin.
In NORA, however, the sensitive dynamic inputs are driven by noise prone dynamic outputs.
Besides drawback and the extra clock phase requirement, there is little reason to use NORA. 
Zipper domino is a closely related technique, that leaves the precharge transistors slightly ON
during evaluation by using precharge clocks. This swing between 0 and VDD – |Vtp| for the
pMOS precharge and Vtn and VDD for the nMOS precharge.

Q19. Explain single-phase clock. What are the problems in single-phase clock ? (AKTU 22-23)
Ans:
Q20. Explain in detail about pipelining structure needed for a logic operation? (AKTU 22-
23)
Ans:
 Unit 4

Short Questions Answer (2 Marks)

Q1. How many types of semiconductor memory ?

Ans. There are two types of semiconductor memory

 i. RAM (Random Access Memory)

 ii. ROM (Read Only Memory).
Q2. What is ROM ?

Ans. ROMs are non-volatile memories, which means that the recorded data is not lost
even when the power is turned off, and no refresh operation is necessary.

Q3. What do you understand by dynamic RAM cell ?

Ans. The DRAM cell is made up of a capacitor that stores binary information ‘1’ (high
voltage) or ‘0’ (low voltage) and a transistor that allows the capacitor to be accessed.
DRAM is commonly utilised for main memory because of its low cost and great density.

Q4. Define SRAM cell.

Ans. When the SRAM cell is made up of a latch, the cell data is retained as long as the
power is turned on, and no refresh operation is required, as with DRAM cells. SRAM is
primarily employed in cache memory in a variety of applications.

Q5. Distinguish between SRAM and DRAM.

Ans.

S.
DRAM SRAM
No.

The DRAM cell consists of a capacitor to SRAM cell consists of a latch to store
1.
store binary information. the binary information.
 DRAM is high density and low cost SRAM is mainly used for the cache
2.
memory. memory applications.

Q6. Enlist the advantages of using address multiplexing scheme in DRAM cell.

Ans. Advantage of using address multiplexing scheme in DRAM cell are:

 1. It reduces the chip package size by reducing pin count.

 2. Reduction of packaging cost.
Q7. What do you understand by flash memory ?

Ans. The flash memory cell is made up of a single transistor with a floating gate, the
threshold voltage of which can be changed repeatedly by applying an electrical field to
its gate.

Q8. How the limitations of a ROM based realization is overcome in a PLA-based

realization ?

Ans. The encoder section of a ROM is solely programmable, and using ROMs to realise
boolean operations is often wasteful because there is no cross-connect for a major
chunk. This waste can be avoided by employing a Programmable Logic Array (PLA),
which takes up substantially less chip space.

Q9. What do you mean by latch-up ? What is the latch-up problem ?

Ans. A. Latch-up: Latch-up is described as the formation of a low-impedance link

between the power supply rails and the ground rails in CMOS chips as a result of the
connectivity of parasitic pnp-npn bipolar transistors.

B. Latch-up problem: These BJTs generate an SCR with positive feedback and
effectively short circuit the power rail to ground, resulting in high current flow and
perhaps irreversible device damage.

Q10. How the latch-up problem can be overcome ?

Ans. 1. Reduce the gains of BJT by lowering the minority carrier lifetime through gold
doping of the substrate.
2. Use minimum area p-wells, so that the p-well photocurrent can be minimized during
transient pulses.

Q11. Why leakage power dissipation has become an important issue in deep
submicron technology ?

Ans. Leakage and subthreshold currents are the most significant sources of leakage
power dissipation in deep submicron technology. As a result, leaky power dissipation
has emerged as a critical issue in deep submicron technology.

Q12. Why we need a low power VLSI circuits in today’s scenario ?

OR

What are needs for low power VLSI chips ?

Ans. Because we need

 i. Extended battery life.

 ii. Low cost.
 iii. High reliability.
Q13. What are the factors that reduces the power dissipation ?

Ans.

 1. Reduction of power supply voltage VDD.

 2. Reduction of the voltage swing at all nodes.
 3. Reduction of the load capacitance.
 4. Reduction of switching probability.
Q14. Comment on overview of power consumption in CMOS logic circuits.

Ans. The average power Consumption in conventional CMOS digital circuits can be
expressed as the sum of three main components, namely :

 i. The dynamic (Switching) power consumption

 ii. The short-circuit power consumption and
 iii. The leakage power consumption
 Q15. Why short-circuit power dissipation occurs ?

Ans. Short-circuit power dissipation happens when both pMOS and nMOS transistors in
the circuit conduct concurrently during the switching time. They form a direct current
path between the power supply and ground at this moment.

Q16. What is the effect on power consumption if the parasitic capacitance is

reduced ?

Ans. The goal of reduction of parasitic capacitance is low power consumption.

Q17. Write the levels of design for which switching capacitance can be reduced.

Ans.1. System level design.

2. Circuit level design.

3. Physical level design

Q 18. What is semiconductor memory ? Also explain its types. (AKTU 2022-23)
Ans: Semiconductor memory is a type of semiconductor device tasked with storing data. There are two electronic data storage mediums that
we can utilize, magnetic or optical.
Magnetic storage:
 Stores data in magnetic form.
 Affected by magnetic fields.
 Has high storage capacity.
 Doesn't use a laser to read/write data.
 Magnetic storage devices are; Hard disk , Floppy disk, Magnetic tape etc.
Optical storage:
 Stores data optically, uses laser to read/write.
 Not affected by magnetic fields.
 Has less storage than a hard disk.
 Data accessing is high, compared to a floppy disc.
 Optical storage devices are; CD-ROM,CD-R, CD-RW, DVD etc.
There is also volatile memory. This is memory that loses its data once power is cut off, while non-volatile memory retains data even without
power.

Semiconductor Memory Types

Q19. Explain the working of three-transistor DRAM cell with concept of leakage currents
and refresh operation. What are the features required to select a proper RAM ? (AKTU
2019-20)

Ans: Working of three-transistor DRAM cell:

1. The various configuration and stepwise historical evolution ofthe DRAM
cells is shown in Fig. 4.2.1.
2. In Fig. 4.2.1(a), during write operation, a word line is enabled and
complementary data are written from a pair ofbit lines. Charge is stored
at parasitic and gate capacitance ofa node.
3. In read operation, the voltage ofa bit line is discharged to ground through
transistor where the gate is charged with the high voltage
Q. 20. What is SRAM ? Explain CMOS SRAM cell design strategy? (AKTU 20-21)
Ans:
Q21: What is SRAM ? Explain CMOS SRAM cell design strategy. (2020-21)
Ans:
Q22. What do you mean by ROM ? Also explain NAND based ROM array design style (AKTU
2018-19)
Ans:
Q23 What are the sources of power dissipation in CMOS circuits ? Explain dynamic and static
power consumption. (AKTU 17-18,18-19,19-20)
Ans:
Q 26. Explain the variable threshold CMOS circuits. (AKTU 2016-17,18-19)
ANs:
Q26. Discuss the low power MTCMOS VLSI design techniques. (AKTU 2018-19)
Ans:
Q. 27: Discuss the various design techniques involved in low power CMOS VLSI circuits. (AKTU
2020-21)
Ans:
Unit 5

Short Question Answer (2 Marks)

Q1. Write the types of defects in designing of digital circuits.

Ans. The types of defects in designing of digital circuits are :

 1. Physical defects.
 2. Electrical defects.
 3. Logical defects.
Q2. Define the terms:

Defects, Errors and Faults.

Ans. Defect: A defect in an electronic system is an inadvertent divergence between the

hardware that has been implemented and the planned design.

Fault: A representation of a “defect” at the abstracted function level is called a fault.

Error: A wrong output signal produced by a defective system is called an error.

Q3. What are the difficulties for the test engineer to test the VLSI circuits?

Ans. 1. The complexity of VLSI systems.

2. With minor exceptions, there is no way that the circuit can be modified during test to
make it work.

Q4. What is the major difficulty in sequential circuit testing ?

Ans. The major difficulty in sequential circuit testing is to determine the internal state of
the circuit.

Q5. Explain the terms controllability and observability.

Ans. A. Controllability: A circuit’s controllability is a measure of how easily (or how

difficultly) the controller can establish a specified signal value at each node by setting
values at the circuit input terminals.
B. Observability: The observability is a measure of the ease (or difficulty) with which
each logic node in the circuit may be determined by managing its primary input and
monitoring its primary output.

Q6. What is use of BST (Boundary Scan Test) ?

Ans. This technique uses scan route and self testing to tackle challenges related with
testing VLSI circuits on boards.

Q7. What are the advantages of BST test ?

Ans. Advantages of BST are as follows :

 1. No need for complex factors.

 2. The test engineer’s work is simplified.
 3. Fault coverage is increased.
Q8. Write the objectives of Built-In-Self-Test.

Ans. The objectives of Built-In-Self-Test are :

 1. To reduce test pattern generation cost.

 2. To reduce the volume of test data.
 3. To reduce test time.
Q9. Write the expression of dynamic power dissipation for MOS circuit.

Ans. The dynamic power dissipation may be represented as :

Pdynamic = α CVDD2f

Q10. Differentiate between static power and dynamic power.

Ans.

S.
Static power Dynamic power
No.
 Static power is the circuit The power used to charge or discharge the intrinsic
1.
leakage power. capacitor of a transistor is referred to as dynamic power.

Static power exists even if Dynamic power only exists when signals toggle either
2.
there are no activities. from low-to-high or high-to-low.

Q11. Write the modules which are essential circuit modules for BIST.

Ans.

1. Pseudo random pattern generator (PRPG).

2. Output response analyzer (ORA).

Q12. What are the fabrication defects which can be detected by IDDQ test only ?

Ans.

 1. Gate oxide short.

 2. p-n diode leakage.
 3. Transmission-gate defects.
 4. Channel punch-through.
Q13. Write the design guidelines for IDDQ testability.

Ans.

 1. Full CMOS is preferred.

 2. No active pull-ups or pull-downs.
 3. No internal drive conflicts.
 4. No floating nodes in the circuits.
Q14. Write the physical defects (faults) that can occur in CMOS.

Ans.
1. Defects in Si substrates.

2. Photolithographic defects.

3. Oxide defects.

Q15. What are the electrical faults that can be translated into logical faults ?

Ans.

1. Logical stuck-at-0 or stuck-at-1.

2. Slower transition (delay fault).

3. AND-bridging, OR-bridging.

Q16. What is meant by stuck-at-1 (s-a-1) fault and stuck-at-0 (s-a-0) faults.

Ans.

1. Faults are fixed (0 or 1) value to a net which is an input or an output of a logic gate or
a flip-flop in the circuit.

2. If the net is stuck to 0, it is called stuck-at-0 (s-a-0) fault.

3. And if the net is stuck to 1, it is called stuck-at-1 (s-a-1) fault.

Q17: Enlist the different kinds of physical defect (faults) that can occur on a CMOS circuits.

Ans:
Q18. Explain functional modeling.
Q19. Differentiate between behavioral and structural modeling.

Ans:

Aspect Structural Diagrams Behavioral Diagrams

Show the static structure of Illustrate the dynamic behavior of

Purpose the system the system

Focus on the components, Focus on the interactions

classes, and their between components and
Focus relationships classes

Classes, objects, interfaces,

Activities, states, messages,
components, and their
events, and their interactions
Elements relationships

Use class diagrams, object Use activity diagrams, state

diagrams, component machine diagrams, sequence
Representation diagrams, etc. diagrams, etc.

Time-independent, as they Time-dependent, as they

depict the structure at a describe how the system
Time specific moment behaves over time

Class diagrams for modeling Sequence diagrams for depicting

Example Use the structure of a software the interaction between objects
Cases system in a specific scenario

Q20: Write a short note on VLSI testing. (AKTU 2019-20)

Ans:
Q21: What is need of VLSI testing ? Discuss about functional and manufacturing tests.

Ans:
Q. 22 Explain the Ad-Hoc testable design techniques. (AKTU 2017-18)
Ans:
Q 23: Explain Fault types and models. (Aktu 2017-18)

Ans:
Q24: Explain the concept of observability, controllability and predictability. (AKTU 17-18, 20-21)

Ans:
Q25: Explain the scan based techniques. (AKTU 2018-19, 19-20, 20-21)
Ans:
Q 26: What are the different scan based techniques. Explain built in self-test technique. (AKTU
2017-18, 18-19, 22-23)
ANs: