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Verilog Compiler Directive

The document describes several Verilog compiler directives including `noaccelerate, `accelerate, `autoexpand_vectornets, `celldefine, `endcelldefine, and `default_decay_time. The `noaccelerate and `accelerate directives control application of optimization algorithms. The `autoexpand_vectornets directive allows vector expansion. The `celldefine and `endcelldefine directives tag instances as cells. The `default_decay_time directive specifies decay time for triregs without a specified time.

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493 views

Verilog Compiler Directive

The document describes several Verilog compiler directives including `noaccelerate, `accelerate, `autoexpand_vectornets, `celldefine, `endcelldefine, and `default_decay_time. The `noaccelerate and `accelerate directives control application of optimization algorithms. The `autoexpand_vectornets directive allows vector expansion. The `celldefine and `endcelldefine directives tag instances as cells. The `default_decay_time directive specifies decay time for triregs without a specified time.

Uploaded by

dharmendraonline
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Verilog Compiler Directives and their description

Comiler Compiler
Description
Directive

The `noaccelerate compiler directive causes Verilog-XL to


stop applying the XL algorithm to the modules following the
compiler directive.

The `accelerate compiler directive causes Verilog-XL to


`accelerate
start re-applying the XL algorithm after a `noaccelerate
`noaccelerate
compiler directive has been issued.

You can only specify these compiler directives outside of


module definitions. You can have as many of these compiler
directives in the source description as you want.

The `autoexpand_vectornets compiler directive lets the


`autoexpand_vectornets compiler expand vectors as needed to form the proper
connections between the elements of the source description.

The `celldefine and `endcelldefine compiler directives tag


module instances as cell instances. More than one pair of
`celldefine and `endcelldefine compiler directives can appear
in a single source description.

Certain PLI access routines use cells for applications such as


delay calculation. Verilog-XL does not mark macro modules
`celldefine (which it expands inline) as cell instances. Refer to the PLI
`endcelldefine 1.0 Reference and User Guide and the VPI Reference and
User Guide for more information about access routines that
recognize cells and the use of cells in delay calculation.

Note: You do not need to apply these compiler directives to


cells extracted from libraries, because Verilog-XL
automatically tags modules as cells unless you invoke it with
the command-line plus option +nolibcell.

The `default_decay_time compiler directive lets you specify


the decay time for triregs whose declarations do not include
a decay time specification. This directive applies to all of the
triregs in all of the modules that follow it in the source
description.

The `default_decay_time compiler directive must include an


argument that specifies the charge decay time. You can enter
this argument as a constant integer, as a real number, or as
the character string infinite. The character string infinite
specifies no charge decay in the triregs that follow the
`default_decay_time directive.
`default_decay_time
The following example shows a use of the
`default_decay_time compiler directive with a numerical
argument. All triregs without a decay time specification in
the modules that follow this `default_decay_time compiler
directive have a charge decay time of 100 time units.

`default_decay_time 100
The following example shows a use of the

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