Unit-2 DSD

Verilog HDL (Hardware Description Language) is a language used

to describe the behavior and structure of digital systems
Verilog allows the design and verification of digital circuits before
hardware implementation. It is essential in modern digital design to
model and test complex systems such as processors, memory
devices, and communication circuits.

Program Structure-:
Modules -: They are building block . A. module defined a portion of
hardware which consists of complex system, full adder , gates
Ports -: Modules Interact with external environment via ports input
and output.
Statements-: The logic or function of module is defined using
various constructs such as assign (for continuous assignments) ,
always (for sequential logic ) and procedural blocks (assign , initial).

Top-Level Module: The highest level in the hierarchy, which can

instantiate other sub-modules.
Sub-Modules: These are modules instantiated inside other modules
to build the overall system.
Module Instantiation: A module can be reused multiple times,
reducing redundancy in the design. Instantiating a module involves
specifying the module's name and the connections to its ports (wires
or registers)

module top;
wire a, b, sum;

// Instantiating the full_adder module

full_adder fa1 (.A(a), .B(b), .Sum(sum));
endmodule

○ Wire: Represents a physical connection, used for

combinational logic.
 ○ Reg: Holds a value until updated, used in sequential
circuits (e.g., flip-flops).
● Operators: Verilog supports arithmetic, logical, relational, and
bitwise operations.
● Procedural Blocks:
○ always: A procedural block that triggers on events (edges
of a clock or signal changes), used in behavioral
descriptions.
○ initial: Executes only once, often used for testbenches.
● Control Statements: if, else, case, for, and while provide flow
control in designs.

Modules: The fundamental unit in Verilog is the module. A module

can represent an entire system or a simple gate. It is a block of code
that contains logic and has inputs and outputs defined through ports.

Gate-level modeling is a way of representing digital circuits using

gates like AND, OR, NOT, XOR, etc. In this style, the designer
describes how logic gates are connected and how they interact.

Dataflow modeling describes the flow of data through a circuit using

continuous assignments (assign) to represent the behavior of the
system. This modeling is closer to the way hardware behaves and
uses logical operators and conditions to define the output in terms of
inputs.

Behavioral modeling in Verilog focuses on describing the high-level

functionality of a system without worrying about its internal structure
or the specific gates used. It uses procedural blocks (always or initial)
to describe how the system behaves over time.

Modeling Style Description When to Use

Gate-Level Describes circuits Use for low-level
using basic logic detailed designs.
gates (AND, OR,
etc.).
Dataflow Describes circuits Use when you need
by the flow of data a simple,
using continuous combinational logic
assignments. design.
Behavioral Describes Use for high-level
functionality design or when
without specifying focusing on
the internal functionality.
structure.

Tasks and Functions

Verilog Tasks -: Tasks are usable blocks that performs a specific

series of operations . They can have multiple inputs , outputs . Can
have multiple inputs and outputs and contain delays and more flexible
than functions

● Reusable
● Timing Controls
● Multiple Outputs

task_name: Name of the task.

input/output/inout: Specifies the direction of signals.
begin...end: Encloses the statements within the task.
Explanation:
● find_max is a task that takes two inputs (num1 and num2) and
provides the maximum value in max.
● This task is called within an always block, allowing it to be
triggered whenever a or b changes.

Verilog Funtions -: Just like tasks but more restrictive like only
return a singnle output and can only execute combinational
logic , not contiain timing delays

Single Return Value: Functions return a single value, making them

ideal for calculations or simple logic.
No Timing Control: Functions cannot include timing controls (e.g., #
delays, @ events).
Must Complete in One Simulation Time Unit: Functions execute
instantaneously within a single simulation time unit.
Use in Expressions: Since functions return a value, they can be
directly used in expressions.
Differences Between Tasks and Functions
Feature Task Function
Return Type No direct return Single return value
value
Multiple Outputs Yes No
Timing Controls Allowed (#, @, wait) Not allowed
Execution Executes when Executes within a
invoked single time unit
 value
Multiple Outputs Yes No
Timing Controls Allowed (#, @, wait) Not allowed
Execution Executes when Executes within a
invoked single time unit
Use in Expressions No Yes

When to Use Tasks vs. Functions

● Use a Task when:
○ You need multiple outputs.
○ Timing control is required (e.g., delays).
○ Sequential execution is necessary for the functionality.
● Use a Function when:
○ The logic is combinational.
○ You need a single output that can be used in expressions.
○ You want the operation to complete in a single simulation
time unit.

Compiler Directives-:
n Verilog, compiler directives are special commands that control
various aspects of the compilation process. They are useful for
setting up conditions, managing parameters, and altering compilation
behaviors to make code more flexible, configurable, and efficient

These directives are typically prefixed with a backtick ( ) and are not
executed as part of the simulation

1. define** and **undef

● `define: Used to define a macro or constant.
● `undef: Used to remove a previously defined macro.
2. `include
The `include directive is used to include external files into the
current file. This is helpful for sharing common code or definitions
across multiple files.

3. `timescale
The `timescale directive specifies the time unit and time precision
for simulation. It is often used at the beginning of a file and affects all
modules within that file.
4. default_nettype
The `default_nettype directive controls the default data type for
undeclared signals in the module. This is often used to prevent
implicit declarations.

5. ifdef**, **ifndef, else**, **elsif, and `endif

These directives allow conditional compilation. You can use them to
include or exclude parts of the code depending on the definition of
certain macros.
● `ifdef: Includes code if a macro is defined.
● `ifndef: Includes code if a macro is not defined.
● else** and **elsif: Alternative conditions within `ifdef blocks.
● `endif: Ends the conditional block.
6. celldefine** and **endcelldefine

he celldefine** and **endcelldefine directives are used to mark

sections of code as cells in a design library, which may affect how
they are handled in terms of optimization and analysis during
synthesis

7. `resetall
The `resetall directive resets all previously set compiler directives to
their default states. It’s useful at the end of a file to avoid unintended
propagation of directives.

8. `line
The `line directive is used for debugging. It helps in controlling the
line number and file name that are displayed in compilation
messages, making it easier to trace back errors.

9. `pragma
`pragma is a directive used to add hints to the compiler, often related
to optimization. Pragmas are typically tool-specific, meaning they
might not be supported by all Verilog compilers.

`pragma protect // Protects the intellectual property in this file (tool-

dependent)

Summary Table of Verilog Compiler Directives

 Directive Description
define / undef Defines or removes macros
`include Includes external files
`timescale Sets the time unit and time
precision
`default_nettype Controls the default net type
ifdef / ifndef / else / elsif / Conditional compilation
`endif
celldefine / endcelldefine Marks cell boundaries
`resetall Resets all compiler directives
to default
`line Sets line number and file name
for error messages
`pragma Adds tool-specific
optimizations or instructions

System tasks and functions

In Verilog, system tasks and functions are predefined routines that
facilitate various non-synthesizable operations like displaying
information, handling file I/O, and controlling simulation behavior.

These tasks and functions, identified by a $ prefix, provide essential

tools for debugging, monitoring, and controlling Verilog simulations.

Categories of System Tasks and Functions

. Display and Monitoring Tasks

. Simulation Control Tasks
. File I/O Tasks
. Mathematical Functions
. Time-Related Functions

Display and Monitoring Tasks

These tasks are useful for displaying and tracking signals, variables,
or messages during simulation.
Common Display and Monitoring Tasks
● $display: Displays values and messages to the simulation
console.
● $monitor: Continuously monitors and displays values
whenever any specified variable changes.
● $strobe: Similar to $display, but displays only the final value
of signals in a time step.
● $write: Displays values without a newline, useful for
formatted output within the same line.
● $monitoron and $monitoroff: Enables and disables
$monitor during simulation.

2. Simulation Control Tasks

These tasks control simulation behavior, such as stopping, finishing,
or displaying a breakpoint.
Common Simulation Control Tasks
● $stop: Pauses the simulation and allows you to inspect the
current state.
● $finish: Ends the simulation entirely.
● $exit: Similar to $finish, but may exit with an exit code in
some simulators.
● $restart: Restarts the simulation (available in some
 ●
simulators).

3. File I/O Tasks

File I/O tasks allow reading from and writing to files, useful for test
benches and complex simulations where data is stored in or retrieved
from files.
Common File I/O Tasks
● $fopen: Opens a file for reading or writing.
● $fclose: Closes an open file.
● $fdisplay, $fwrite, $fstrobe: File-based equivalents of
$display, $write, and $strobe.
● $fmonitor: Writes monitored values to a file whenever
variables change.
● $fscanf: Reads formatted data from a file.
● $readmemb and $readmemh: Loads binary (memb) or
hexadecimal (memh) data from a file into memory.
4. Mathematical Functions
Verilog provides a set of mathematical functions that perform various
arithmetic operations.
Common Mathematical Functions
● $abs: Returns the absolute value of a number.
● $pow: Raises a number to a power.
● $sqrt: Calculates the square root.
● $clog2: Returns the ceiling of the base-2 logarithm, useful for
calculating address width for memory.
5. Time-Related Functions
These functions provide information about simulation time, which is
helpful for debugging and performance analysis.
Common Time-Related Functions
● $time: Returns the current simulation time.
● $realtime: Returns the simulation time in real format (for
decimal precision).
● $stime: Returns the simulation time as a short integer.