J Electr Eng Technol Vol. 9, No.

1: 127-135, 2014
http://dx.doi.org/10.5370/JEET.2014.9.1.127

127
Advanced Cascade Multilevel Converter with Reduction
in Number of Components


Ali Ajami

, Mohammad Reza Jannati Oskuee*, Ataollah Mokhberdoran*

and Mahdi Toupchi Khosroshahi*

Abstract In this paper a novel converter structure based on cascade converter family is presented.
The suggested multilevel advanced cascade converter has benefits such as reduction in number of
switches and power losses. Comparison depict that proposed topology has the least number of IGBTs
among all multilevel cascade type converters which have been introduced recently. This characteristic
causes low cost and small installation area for suggested converter. The number of on state switches in
current path is less than conventional topologies and so the output voltage drop and power losses are
decreased. Symmetric and asymmetric modes are analyzed and compared with conventional multilevel
cascade converter. Simulation and experimental results are presented to illustrate validity, good
performance and effectiveness of the proposed configuration. The suggested converter can be applied
in medium/high voltage and PV applications.

Keywords: Multilevel converters, Reduced number of components, Cascaded multilevel converter,
Symmetric and asymmetric topology



1. Introduction


Multilevel voltage-source converters provide a cost
effective solution in the low and medium-voltage energy
management market [1]. The term multilevel was
introduced with the three level converters [2]. A multilevel
converter is a power electronic system that produces a
desired output voltage via several levels of dc voltages as
inputs. With increasing the number of dc voltage sources,
the converter output voltage waveform yields nearly
sinusoidal waveform while using a fundamental frequency-
switching scheme. As the number of levels increases,
these advantages will be enhanced. This characteristic
results in high-power-quality waveforms with lower
distortion and a low blocking voltage for switching devices.
However, it can impose more cost due to increase the
circuit complexity and number of components and so the
efficiency and reliability of multilevel converter is
decreased. These are the main drawbacks of multilevel
converters. Three main types of commercial topologies of
multilevel voltage-source converters are: neutral point
clamped (NPC) or diode clamped [2], cascaded H-bridge
(CHB) [3], and flying capacitors (FCs) [4].
Among these converter topologies, the higher output
voltage and power rating (13.8 kV, 30 MVA) are related to
cascaded multilevel converter and its modular topology
causes the higher reliability. The major disadvantages
associated with the multilevel configurations are their
circuit complexity, requiring the high number of power
switches and the great number of auxiliary dc voltages
which provided either by independent supplies or, more
commonly, by a bulky array of capacitive voltage splitters.
In this case, balancing the dc voltages is another factor that
makes modulator circuit more complex [5]. A lot of efforts
in literatures have been done to reduce the number of
power switches and dc sources in several new topologies of
multilevel cascade converters. The first introduced
topology was the series H-bridge design [6], but several
configurations have been obtained for this topology as well
[7-8]. Several combinational designs have also been
developed by cascading the fundamental topologies [9-10].
These designs can improve power quality for a given
number of semiconductor devices than the fundamental
topologies alone due to a multiplying effect of the number
of levels. In [11-12] new configurations have also been
proposed in which the number of separate dc sources have
been diminished for high-voltage, high-power applications.
A new cascaded multilevel converter called Zigzag
converter is presented in [13]. Multiple outputs in this
novel converter are produced only by one dc source. The
dc voltage of each cascaded cell can be balanced without
special control, and independent of load type. In this paper
a novel symmetric and asymmetric multilevel modular
cascade converter is proposed. Number of switches and on-
state IGBTs is reduced in suggested advanced-cascade
converter. The proposed configuration is discussed in both
symmetric and asymmetric form. Then comparison is done
between suggested multilevel converter and conventional
one that presents advantages of this topology. Eventually
Corresponding Author: Dept. of Electrical Engineering, Azarbaijan
Shahid Madani University, Iran. (ajami@azaruniv.edu)
* Dept. of Electrical Engineering, Azarbaijan Shahid Madani Uni-
versity, Iran. ({m.r.jannati, amokhber, mt.khosroshahi}@ azaruniv. edu)
Received: May 27, 2013; Accepted: June 25, 2013
ISSN(Print) 1975-0102
ISSN(Online) 2093-7423
Advanced Cascade Multilevel Converter with Reduction in Number of Components

128
simulation results and a prototype implementation of
proposed multilevel converter are presented to show
affectivity of new topology.


2. Cascade Multilevel Converter

A series connection of multiple single-phase converters
creates cascaded multilevel converter. Each converter
consists of a dc voltage source and four power switches
that can produce three levels of voltage on its terminals.
Three voltage steps refer to positive and negative values
and zero level in each basic converter. Desired staircase
voltage waveform is generated by composing appropriate
dc voltage sources. This construction has capability to
acquire medium output voltage levels utilizing only standard
low-voltage components. This decreases the switching
losses and voltage stress on power electronic devices, also
the output voltage has small voltage steps, which results in
high power quality, low harmonic components and better
electromagnetic compatibility. A high modularity capability
is main property of these converters because each converter
can be seen as a module with similar circuit topology,
control structure, and modulation. The cascaded H-bridge
(CHB) topologies are suitable solution for high voltage
applications due to the modularity and the simplicity of
control. But, in these topologies, a great number of
separated DC voltage sources are required to supply each
conversion cell. Fig. 1 (a) depicts a cascaded H-bridge
structure with n DC voltages sources which can produce
2n+1 output voltage levels in symmetric mode. In
symmetric position for n dc voltage sources we have
V
1
=V
2
==V
n
=V
dc
.

3. Proposed Topology

3.1 Fundamental unit of suggested converter

As seen from Fig. 2 basic unit consist of two dc voltage
sources and four semiconductor unidirectional switches or
IGBTs. When number of dc sources is equal in conventional
and proposed converter, it is found out that number of
IGBTs here is half of that one in H-Bridge. Therefore each
dc source devotes two IGBTs to itself.
In asymmetric CHB converter more output voltage
levels are generated compared to the symmetric mode by
same number of dc voltage sources.
Each basic unit is able to generate all voltage levels, zero,
V and 2V. It is noteworthy that each basic module with two
DC voltage sources and 4 switches beside a surrounding H-
bridge produces five levels (positive and negative levels
and regarding zero level) so the proposed topology with
more than three DC voltage sources (two dc sources inside
first module and a single voltage source) can generate more
output levels with less switches because H-bridge is
common for all the modules. Switching states are given in
Table 1 for proposed symmetric basic unit. To avoid short
circuit across dc voltage sources in the basic unit S
11
and
S
13
should operate in complementary mode with S
12
and
S
14
respectively.
Fundamental asymmetric unit of recommended converter
is achieved with partial rearrangement in symmetric
topology which is presented in Fig. 3. These changes entail
adding an IGBT S
11
at left side of symmetric structure and
exchanging of central IGBT with one bidirectional switch
as seen in Fig. 3. In this basic module S
13
is added to avoid
turning on diode of S
14
when S
11
is on. This prevents short

(a) (b)
Fig. 1. Multilevel cascade H-Bridge converter: (a) Symmetric
converter; (b) Asymmetric converter

Fig. 2. Basic cell of proposed topology for symmetric mode

Table 1. Switching states of basic symmetric proposed
topology
S. No
Switching state
V
o

S
11
S
12
S
13
S
14

1 1 0 1 0 +2V
2 0 1 1 0 +V
3 0 1 0 1 0
Ali Ajami, Mohammad Reza Jannati Oskuee, Ataollah Mokhberdoran and Mahdi Toupchi Khosroshahi

129
circuit across dc voltage sources V
11
and V
21
in the Fig. 3.
Switching states have been obtained in Table 2 for
asymmetric unit shown in Fig. 3. If dc voltage sources are
selected as binary mode, the basic unit will be able to
generate four positive levels considering zero level. It is
assumed V
1
=1V and V
2
= 2V in this table.
As seen from Table 2 to avoid short circuit across DC
voltage sources in the basic unit S
11
, S
12
and S
15
should
operate in complementary mode with S
13
, S
14
and S
16

respectively. Furthermore S
11
and S
12
should not be turned
on simultaneously. For example if S
12
and S
13
are turned on,
S
14
should not turn on; otherwise V
11
will be shorted circuit.
S
13
and S
14
operate like a bidirectional switch.

3.2 Suggested configuration

Novel suggested configuration for multilevel cascade
converter called advanced cascade (AC) converter in
symmetric form is shown in Fig. 4. In this method, all of
the dc voltage sources in each unit are identical.

v
j
= v; j = 1, 2, n (1)

Where V is amplitude of each dc voltage sources and n
is number of dc power supplies. It is noteworthy that n
should be odd. In the symmetric case a single DC voltage
source is used in the top of all modules to produce more
output level without need of two excessive IGBTs. This
figure represents connection of n-1 fundamental units and
an innovative H-bridge encompassed bulk of novel cascade
topology. In this structure, role of H-bridge is to reverse the
positive output voltage levels in second half cycle of
voltage waveform.
Although several dc sources are required in this
configuration, in some applications renewable energy
sources could be used, such as photovoltaic panels or fuel
cells, or with energy storage devices, such as capacitors or
batteries. If ac voltage is already available, multiple dc
power supplies can be produced via the isolated
transformers and rectifiers. The overall output voltage of
the proposed cascaded multilevel converter is the sum of
output voltages of the m basic units, as follows:

I
0
= _(:
o1
+:
o2
++:
om
) (2)

Where for ith basic unit

v
oI
= _
2v if S
I1
= 1 anu S
I3
= 1
v if S
I2
= 1 anu S
I3
= 1
u if S
I4
= 1
(3)

For achieving more output voltage steps with the same
Fig. 3. Basic proposed topology for asymmetric mode

Table 2. Switching states of basic asymmetric proposed
topology
S. No
Switching state
V
o

S
11
S
12
S
13
S
15
S
16

1 0 1 1 0 1 0 +3V
0 0 1 1 1 0 +2V
3 1 0 0 1 1 0 +V
4 1 0 0 1 0 1 0
5 0 1 1 0 0 1 0

Fig. 4. Proposed symmetric multilevel advanced cascade
converter

Advanced Cascade Multilevel Converter with Reduction in Number of Components

130
number of dc voltages sources that used in symmetric
multilevel converter, asymmetric form is introduced. Fig. 5
shows the proposed asymmetric multilevel converter. In
asymmetric multilevel converter with n dc power supplies,
values of dc voltage sources are defined as bellow:

v
k
= p
k-1
(4)

Where k=1,2n, and p is integer number that represents
asymmetric factor and V is the smallest dc voltage source
in the top of all modules (single DC voltage source). As the
matter of the fact DC voltage sources which are used in Fig.
5 are selected by (4) in a sequence.
Here some partial changes have been implied to
asymmetric recommended topology. As well as adding two
IGBTs in each basic unit which is mentioned before, two
IGBTs are joined to alone dc voltage source. To increase
the number of output levels in proposed asymmetric
topology, one DC source with two IGBTs are added. Two
IGBTs is added to the single DC voltage source in the top
of all modules (V) to create paths for selecting or
eliminating this DC source in order to generate desired
step in output voltage. Also in the i-th module (as seen in
Fig. 5) Si1 is added to create path for contributing the V2i-
1 lonely in the output voltage waveform. Adding this IGBT
necessitate adding Si3 beside Si4 to prevent short
circuiting the DC sources in this module.
By combinations of switching states of each unit, the
various output voltage levels can be obtained. If suitable
values for the dc voltage sources are chosen, then the
output voltage of the converter can be produced between
-( v
oI
n-1
I=1
+v) and +( v
oI
+v
n-1
I=1
) , where v
oI
is
determined as bellow:

v
oI(max)
= v
2I-1
+v
2I
(5)


4. Comparison Study

4.1 Number and rating of devices

The purpose of this section is comparison of imperative
quantities between suggested multilevel converter and
traditional multilevel converter with the same dc power
supplies in the both magnitudes and number. Table 3 and 4
show comparison results between proposed advanced
multilevel cascade converter and conventional multilevel
cascade converter. It should be noticed in Tables 3 and 4
number of output levels includes positive and negative as
well as zero levels. Number of dc voltage sources is equal
to n and each unit is consisted of two dc voltage source. It
is noteworthy that n should be odd.
In the asymmetric form of basic unit shown in Fig. 3 the
PIV is calculated as follows:

PIv
1
= 2v
1
+4v
2
(6)

In same way for asymmetric form of ith basic unit PIV

Fig. 5. Proposed asymmetric multilevel advanced cascade
converter

Table 3. Comparison of proposed advanced cascade
multilevel converter in symmetric and asymmetric
modes
Proposed Symmetric Asymmetric
No. of DC sources n n
No. of switches 2n+2 3n+3
No. of output levels 2n+1 2 - _
1 -p
n
1 -p
] +1
Maximum voltage n vdc (
1-p
n
1-p
) - vdc
PIV (
1S
2
n-
S
2
) - v
dc

(2v
2I-1
+ 4v
2I
)
m
I=1
No. of On-state
switches
n-1 (
S
2
n -
1
2
)
Ali Ajami, Mohammad Reza Jannati Oskuee, Ataollah Mokhberdoran and Mahdi Toupchi Khosroshahi

131
would be equal to:

PIv
I
= 2v
2I-1
+4v
2I
(7)

Therefore total PIV of asymmetric converter shown in
Fig. 5 can be obtained as follows:

Tottal PIv = PIv
1
+. PIv
I
+PIv
m
(8)

Where, m is number of basic units.
It is noteworthy that n should be odd. Table 4 shows
traditional multilevel cascade circuit information in both
symmetric and asymmetric modes. It should be pointed out
that in the comparison of proposed and conventional
topology the number of DC voltage sources should be
considered as equal. So for the single DC voltage source
(V) used in the asymmetric proposed topology with two
IGBTs, it is assumed an H-bridge is used in the
conventional one includes a DC source.
Comparison between two tables illustrates number of
IGBTs and on-state switches are almost half of that one in
conventional configuration. Number of output voltage
levels of multilevel cascade converter in symmetric and
asymmetric mode is exactly same to that of suggested
converter. This comparison approves advantages of the
suggested configuration in this paper. As a matter of fact
with less number of IGBTs, same output voltage steps
could be generated in introduced topology compared to H-
Bridge cascade multilevel converter.
Fig. 6 shows the number of IGBTs versus the number of
voltage levels in proposed symmetric topology. As the
figure shows, for any specific value of level, the proposed
topology uses lower number of IGBTs in comparison with
CHB. The figure clearly shows that the proposed topology
uses less number of IGBTs.

4.2 Power losses calculation

Generally power electronic converters have two kinds of
losses. The conduction losses are produced by equivalent
resistance and the on-state voltage drop of the
semiconductor devices. Non-ideal operation of switches
creates the switching losses. Calculation of the losses of
the proposed multilevel converter is discussed below.

A. Conduction losses

In order to calculate the conduction losses, firstly
conduction losses of a typical power transistor and diode is
calculated then they are extended to the multilevel
converter. The instantaneous conduction losses of a
transistor (p c, T (t)) and diode (p c, D (t)) can be expressed
as follows:


,
( ) [ ( )] ( )
C T T T R
t t i t
V i P

= + (9)

,
( ) [ ( )] ( )
C D D D
P t V R i t i t = +
(10)

Where, VT and VD are the on-state voltage of the
transistor and diode, respectively. RT and RD are the
equivalent resistance of the transistor and diode,
respectively and is a constant related to the characteristic
of the transistor. Therefore, using (9) and (10), the average
conduction power loss of the proposed sub-multilevel
converter can be calculated as follows [14]:


0
( ) ( ) 1
( ) ( )
( ) ( ) ( ) ( )
T D
C
T D
x t V y t V
t i t d t
P
x t R t y t R i t
i

+ +
=

+


(11)

where, x(t) and y(t) are number of transistors and diodes
in the current path in any instant of time respectively.

B. Switching losses

The switching losses are calculated for a typical switch
and then the results are developed for the proposed
multilevel converter. The total switching power losses
consist of two components:
1. IGBT switching power loss
2. Anti-parallel diodes power losses
The following equations can be written:


, , ,
( )
sw T on T off T sw
P E E f = +
(12)

, , , ,
( )
sw Anti D on Anti D off Anti D sw on Anti D sw
P E E f E f

= +


Where,
Table 4. Comparison of conventional multilevel cascade
converter in symmetric and asymmetric modes
Traditional cascade Symmetric A Symmetric
No. of DC sources n N
No. of switches 4n 4n
No. of output levels 2n+1 2 - _
1 -p
n
1 -p
] +1
Maximum voltage n vdc (
1-p
n
1-p
) - vdc
PIV 4n - v
dc
4 - (
1-p
n
1-p
) - vdc
No. of On-state switches 2n 2n

Fig. 6. Number of IGBTs versus number of levels for the
symmetric topology
0 10 20 30 40 50 60 70
0
20
40
60
80
100
120
Number of levels
N
u
m
b
e
r

o
f

I
G
B
T
s

4n/2n+1
2n+2/2n+1
Proposed
CHB
Advanced Cascade Multilevel Converter with Reduction in Number of Components

132
, sw T
P
is switching power losses of IGBT,
, on T
E
is turn on
energy losses in IGBT
, off T
E
is Turn off energy losses in IGBT and
sw
f is
switching frequency.

The index Anti D indicates the parameter related to
the anti-parallel diodes. The switching losses depend on the
number of switching transitions. Therefore, it depends on
the modulation method. Finally total switching power
losses of a fundamental block can be calculated as below:


, ,
1
i i
i
sw sw T sw Anti D
P P P

= +

(14)

Where i are depended on switching pattern that define
the number of turned on IGBTs.
Using (11) and (14), the total losses of the fundamental
multilevel converter will be as follows:


loss sw C
P P P = + (15)

Comparison of the power losses for the 7-level
symmetric proposed and conventional structures is
depicted in Fig. 7. Calculation of losses is analyzed based
on SPWM modulation approach. In this case the proposed
configuration consist of a module includes two DC voltage
sources and a single DC source is utilized. Here
conventional structures consist of three H-bridges. Both
cascaded and proposed converters are simulated using
BUP406 IGBTs with the given data in [15] and 10v DC
voltage sources values and load parameters of 30 ohm and
20 mH. As seen in this figure power loss of proposed
topology is less than conventional one.


5. Simulation and Experimental Results

5.1 Simulation results

Fig. 8 shows the 11-level hybrid Advanced cascade (AC)
converter in symmetric form which has two basic unit so
n=5 and number of IGBTs according to Table 1 are 2n+2
where yield 12 IGBTs. Switching states of 11-level
proposed converter have been illustrated in Table 5 to make
operational principle of AC multilevel converter much
more comprehensible. The switch S is ON when its state is
1 and is OFF when its state is 0.
Figs. 9 and Fig 10 illustrate simulation results. It should
be noticed that in symmetric and asymmetric proposed
topologies two modules and one module as well as a single
DC sources are implemented respectively. In presented
simulation and experimental results the DC voltage sources
are considered 100V. Therefore output voltage waveforms
consist of 100 V steps in the simulation and experimental
results. Dc voltage sources in asymmetric form for
proposed configuration are selected according to a
geometric progression with a factor of two. Fig. 9 (a) show
simulation results of output voltage and current for 11-level

Fig. 7. Comparison of the power losses for the proposed
and conventional structures
0.1 0.15 0.2 0.25 0.3 0.35
0
1
2
3
4
5
6
Modulation Index
L
o
s
s

(
w
)
cascade inverter
proposed inverter

Fig. 8. The 11-level symmetric hybrid Advanced cascade

Table 5. Switching states of 11-level proposed topology in
symmetric form
S. No
Switching state
Vo
S
11
S
21
S
13
S
23
H
1
H
2

1 1 1 1 1 1 0 +5V
1

2 1 1 1 0 1 0 +4V
1

3 1 1 0 0 1 0 +3V
1

4 1 0 0 0 1 0 +2V
1

5 0 0 0 0 1 0 +V
1

6 0 0 0 0 1 1 0
7 0 0 0 0 0 1 -V
1

8 1 0 0 0 0 1 -2V
1

9 1 1 0 0 0 1 -3V
1

10 1 1 1 0 0 1 -4V
1

11 1 1 1 1 0 1 -5V
1


Ali Ajami, Mohammad Reza Jannati Oskuee, Ataollah Mokhberdoran and Mahdi Toupchi Khosroshahi

133
proposed symmetric topology under RL load. Fig. 9 (b)
shows THD analysis and magnitudes of different harmonic
components in output voltage waveform for proposed
symmetric topology.
Fig. 10 (a) presents simulation result of 15-level
asymmetric configuration (output voltage and current). Fig.
10 (b) shows THD analysis and magnitudes of different
harmonic in output voltage waveform for proposed
asymmetric topology. For this case, THDs of the output
voltage based on simulations are 14.58% and 11.24% in
suggested symmetric and asymmetric forms respectively.
As it can be seen in these waveforms, the output current
has a low THD, meaning near sinusoidal waveform. To
produce a desired output with high power quality, the
number of voltage levels should be increased.

5.2 Experimental results

To evaluate the performance of the suggested multilevel
converter, shown in Fig. 8, a single-phase 11-level
prototype has been modeled and implemented. The Fig. 11
shows the implemented laboratory prototype photograph.
The IGBTs used in the prototype are BUP406 with internal
anti-parallel diodes and voltage and current ratings equal to
1200V and 20 A, respectively. The switching required
pulses are produced by the DsPIC30F4011 microcontroller.
The Hcpl316j is used as IGBT gate derives. In the
implemented proposed symmetric multilevel converter the
DC voltage sources are 100 V.
Figs. 12 and Fig. 13 illustrate experimental results.
Amplitude of the smallest DC voltage source for the
asymmetric proposed topology is 70 V in the experimental
test so the output voltage waveform is obtained with 70 V
steps. Figs. 12 (a) and (b) present experimental results of
output voltage waveforms for 11-level proposed symmetric
topology in no load and under RL load respectively.
Figs. 13 (a) and (b) depict experimental results of output
voltage waveforms for 15-level proposed asymmetric
topology in no load and under RL load respectively. Fig. 13
(c) shows the FFT analysis and magnitudes of different

(a) Output voltage and current

(b) THD and FFT analysis of output voltage
Fig. 9. Simulation results of 11-level proposed converter in
symmetric mode


(a) Output voltage and current


(b) THD and FFT analysis of output voltage
Fig. 10. Simulation results of 15-level proposed converter
in asymmetric mode
0 200 400 600 800 1000
0
2
4
Frequency (Hz)
Fundamental (50Hz) = 108.5 , THD= 14.58%
M
a
g

(
%

o
f

F
u
n
d
a
m
e
n
t
a
l
)
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07
-800
-600
-400
-200
0
200
400
600
800


Voltage
current
Fig. 11. The implemented laboratory prototype
Advanced Cascade Multilevel Converter with Reduction in Number of Components

134
harmonic components of output voltage. As seen in this
figure main harmonic is related to 50Hz which devotes the
greatest magnitude to itself.
As seen in this figure the simulation and experimental
results are match as saliently. Partial difference between the
magnitudes of the simulation and experimental results is
because of the voltage drops on switches in the prototype.


6. Conclusion

In this paper, a new converter topology has been
proposed which has many superior features over
conventional topologies. In the proposed topology less
number of power switches is required compared to
conventional converter. Furthermore suggested topology
needs lower number of isolated dc voltage sources in
comparison to conventional topologies. The number of on
state switches in current path is less than conventional
topologies. Therefore, the voltage drop in output voltage,
cost, and volume of proposed converter are low too. In the
comparison part these advantages have been shown clearly.
The experimental results of the developed prototype for an
eleven-level converter of the proposed topology are
demonstrated in this paper.
(a) Output voltage in no load case

(b) Output voltage and current under load condition
Fig. 12. Experimental results of 11-level proposed symmetric
configuration

(a) Output voltage in no load case

(b) Output voltage and current under load condition

(c) FFT analysis for output voltage in asymmetric proposed
topology
Fig. 13. Experimental results of 15-level asymmetric
configuration
Ali Ajami, Mohammad Reza Jannati Oskuee, Ataollah Mokhberdoran and Mahdi Toupchi Khosroshahi

135
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Ali Ajami He received his B.Sc. and M.
Sc. degrees from the Electrical and Com-
puter Engineering Faculty of Tabriz
University, Iran, in Electronic Engin-
eering and Power Engineering in 1996
and 1999, respectively, and his Ph.D.
degree in 2005 from the Electrical and
Computer Engineering Faculty of Tabriz
University, Iran, in Power Engineering. Currently, he is
associate Prof. of electrical engineering department of
Azarbaijan Shahid Madani University. His main research
interests are dynamic and steady state modeling and
analysis of FACTS devices, harmonics and power quality
compensation systems, microprocessors, DSP and
computer based control systems.

Mohammad Reza Jannati Oskuee
He was born in Tabriz, Iran, in 1988.
He received his B.Sc. degree (2011), in
electrical power engineering from Uni-
versity of Tabriz, Tabriz, Iran. Currently
he is M.Sc. student of Power Engin-
eering at Azarbaija n Shahid Madani
University, Tabriz, Iran. His major re-
search interests include smart grid, distribution system plan-
ing and operation, renewable energy, power electronics,
application of evolutionary algorithms and intelligence
computing in power systems, dynamics and FACTS devices.

Ataollah Mokhberdoran He was born
in Tabriz, Iran in 1983 and received his
B.Sc. and M.Sc. degrees from the
Electrical Engineering Faculty of Iran
University of Science and Technology
and Azarbaijan Shahid Madani Uni-
versity, Iran, in Electrical Power
Engineering in 2006 and 2010, respect-
ively. Currently, he works as R&D manager of ASAS
Company in Tabriz. In recent years, he performed numerous
industrial research and development projects in power
engineering fields. His research interests include multilevel
inverters, power converters, renewable energies, FACTs,
DSP based power electronic devices and smart grids.

Mahdi Toupchi Khosroshahi He was
born in Tabriz, Iran, in 1984. He re-
ceived his B.Sc. and M. Sc. degrees
from the electrical engineering Faculty
of Azarbaijan Shahid Madani Universi-
ty, Tabriz, Iran, in Power Engineering
in 2008 and 2013, respectively. His
main research interests include control
and operation of smart micro-grid, distribution system,
renewable energy, power electronics, FACTS devices,
application of evolutionary algorithms and intelligence
computing in power systems and Medicine
.