IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

11, NOVEMBER 2011 3109

A New Topology of Cascaded Multilevel Converters

With Reduced Number of Components for
High-Voltage Applications
Javad Ebrahimi, Student Member, IEEE, Ebrahim Babaei, Member, IEEE,
and Goverg B. Gharehpetian, Senior Member, IEEE

Abstract—In this paper, a new topology of a cascaded multilevel variety of control strategies have been developed [6]–[9]. There
converter is proposed. The proposed topology is based on a cas- are three different basic multilevel converter topologies: neu-
caded connection of single-phase submultilevel converter units and tral point clamped (NPC) or diode clamped [10], flying capac-
full-bridge converters. Compared to the conventional multilevel
converter, the number of dc voltage sources, switches, installation itor (FC) or capacitor clamped [11], and cascaded H-bridge
area, and converter cost is significantly reduced as the number (CHB) [12].
of voltage steps increases. In order to calculate the magnitudes The main drawback of the NPC topology is unequal voltage
of the required dc voltage sources, three methods are proposed. sharing between the series connected capacitors, which leads
Then, the structure of the proposed topology is optimized in order to dc-link capacitor unbalancing and requires a great number
to utilize a minimum number of switches and dc voltage sources,
and produce a high number of output voltage steps. The operation of clamping diodes for a high number of voltage levels [6].
and performance of the proposed multilevel converter is verified Also, the maximum voltage across the switches is closest to the
by simulation results and compared with experimental results of a switching node. Therefore, the three-level NPC converter has
single-phase 49-level converter, too. been commercialized in industry as a standard topology. The
Index Terms—Full-bridge topology and high-voltage appli- FC multilevel converter, and its derivative, the stacked multilevel
cation, multilevel converter, power conversion, submultilevel (SM) converter [13] and [14], use flying capacitors as clamp-
converter. ing devices. These topologies have several attractive properties
compared to NPC converters, including the advantage of trans-
formerless operation and have redundant phase leg states that
I. INTRODUCTION allow the switching stresses to be equally distributed among
ULTILEVEL converters have been introduced as static semiconductor switches [15] and [16]. But, these converters
M high-power converters for medium- to high-voltage ap-
plications such as large electric drives, dynamic voltage restor-
require an excessive number of storage capacitors for a high
number of voltage steps. A double FC multicell converter has
ers, reactive power compensations, and FACTS devices [1]–[5]. been presented in [17]. This topology has been implemented by
The multilevel converters synthesize a desired stepped output adding two low-frequency switches to the conventional config-
voltage waveform by the proper arrangement of the power semi- uration of the FC multilevel converter. The main advantages of
conductor devices from several lower dc voltage sources. The the presented converter, in comparison with the FC multilevel
main advantage of multilevel converters is the use of mature and SM converters, are the doubling of the rms value of the
medium power semiconductor devices, which operate at re- output voltage and the number of output voltage steps and the
duced voltages. As a result, the switching losses and voltage canceling of the midpoint of the dc source. But two additional
stress on power electronic devices are reduced. Also, the output switches must operate at the peak of the output voltage. This
voltage has small voltage steps, which results in good power restricts high-voltage applications of this converter.
quality, low-harmonic components, and better electromagnetic The CHB topologies are a good solution for high-voltage ap-
compatibility. Multilevel converters have obtained more and plications due to the modularity and the simplicity of control.
more attention in recent years and new topologies with a wide But, in these topologies, a large number of separated voltage
sources are required to supply each conversion cell. To reduce
the number of separate dc voltage sources for high-voltage ap-
plications, new configurations have also been presented; how-
Manuscript received December 9, 2010; revised March 5, 2011; accepted ever, a capacitor-voltage balancing algorithm is required [18]
March 28, 2011. Date of current version November 18, 2011. This work was
supported by the Iran Renewable Energy Organization (SUNA). Recommended and [19].
for publication by Associate Editor B. Wu. Multilevel converters have some particular disadvantages.
J. Ebrahimi and G. B. Gharehpetian are with the Electrical Engineering De- They need a large number of power semiconductor switches,
partment, Amirkabir University of Technology, Tehran 15914, Iran (e-mail:
j_ebrahimi@aut.ac.ir; grptian@aut.ac.ir). which increase the cost and control complexity and tend to re-
E. Babaei is with the Faculty of Electrical and Computer Engineering, Uni- duce the overall reliability and efficiency. Although low-voltage-
versity of Tabriz, Tabriz 51664, Iran (e-babaei@tabrizu.ac.ir). rated switches can be utilized in a multilevel converter, each
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. switch requires a related gate driver and protection circuit. This
Digital Object Identifier 10.1109/TPEL.2011.2148177 may cause the overall system to be more expensive and complex.

0885-8993/$26.00 © 2011 IEEE

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3110 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

The researchers have strived in [20] to introduce a new topol-

ogy for multilevel converters with a reduced number of com-
ponents compared to conventional multilevel converters. This
topology consists of series connected submultilevel converter
blocks. In order to create the output voltage with a constant
number of steps, there are different structures with different
number of components. Therefore, the converter structure can be
optimized for various objectives. This increases the design flex-
ibility. But, the converter needs a large numbers of bidirectional
switches and the blocking voltage of bidirectional switches is
also high.
To overcome aforementioned disadvantages, a new topology
with reduced number of switches and dc voltage sources has
been presented in [21]. Also, the structures based on similar
concepts have been presented in [22]. In these topologies, the
dc source is formed by connecting a number of half-bridge
submodules. The main drawback of these topologies is the uti-
lization of unidirectional switches, which operate at high output
voltage in single-phase applications. Also, the design flexibility
is lost in these topologies.
Fig. 1. (a) Proposed submultilevel topology and (b) typical output waveforms
As mentioned, the presented topologies in [20] and [21] uti- of v o .
lize switches, which operate at the peak of the output voltage.
Therefore, a bulky and costly interface transformer needs to be TABLE I
used for high-voltage applications. VALUES OF v o FOR DIFFERENT STATES OF THE SWITCHES
This paper proposes a new modular and simple topology for
cascaded multilevel converters that produces a large number of
steps with a low number of power switches and components.
Three different procedures for calculating required magnitudes
of dc voltage sources are proposed. In addition, the structure of
the proposed topology is optimized for various aims. A com-
parison analysis with two recently presented topologies is also
provided. Finally, a design example of the proposed multilevel
converter is included.

II. PROPOSED TOPOLOGY

Fig. 1 shows the proposed topology for a submultilevel con-
verter, which consists of the basic unit and a full-bridge con-
verter. The basic unit consists of n dc voltage sources. Each
dc voltage source is connected to the output by two switches
and can produce a zero or positive polarity voltage. As shown
in Fig. 1, each switch is composed of an insulated gate bipolar
transistor (IGBT) with an antiparallel diode. Both switches, Si
and S̄i (for i = 1, 2, . . . , n), are complementary controlled on
the entire operation cycle. The basic unit produces a staircase
voltage waveform with positive polarity. The output voltage of
the basic unit can be equal to each dc voltage source or binary,
ternary, . . . , or n’nary combinations of the dc voltage sources.
Therefore, the maximum number of output voltage steps for vo voltage drops of the switches have been neglected. As can be
is equal to 2n − 1. The output side of the basic unit is con- seen, 2n +1 − 1 different values can be obtained for vo . It can be
nected to a single-phase full-bridge converter, which alternates mentioned that there are different switching states to generate
the input voltage polarity and provides a positive or negative the zero-voltage level at the output voltage. In Table I, one state
staircase waveform at the output. The full-bridge switches, T1 , is presented.
T̄1 , T2 , and T̄2 , are also complementary controlled. The typical The proposed multilevel converter topology is constituted
output waveforms of vo and vo are shown in Fig. 1(b). Table I by a cascade connection of submultilevel converters as shown
gives the values of voltages vo and vo for different states of the in Fig. 2. The structure of the first, second, . . . and kth basic
switches S1 , S2 , . . . , Sn , T1 , and T2 . For simplicity, the on-state unit have 2n1 , 2n2 , . . . , and 2nk switches, respectively. The

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EBRAHIMI et al.: NEW TOPOLOGY OF CASCADED MULTILEVEL CONVERTERS 3111

are presented. To produce a specific number of output steps,

the number of dc voltage sources is decreased from the first- to
the third proposed method. But, the variety of magnitudes of dc
voltage sources is increased. This is one of the important prob-
lems for asymmetric structures of multilevel converters. It is
noticeable that for all proposed methods, any number of output
voltage steps (even and odd) can be produced.

A. First Proposed Method

In this method, all the dc voltage sources in each unit are
equal. The first dc voltage source V11 is considered as the base
value for the per-unit system as follows:
Vbase = V11 = Vdc . (2)
Then, the normalized values of the dc voltage sources for pro-
Fig. 2. Proposed multilevel converter topology. ducing all steps in the output must be chosen using the following
procedure:
full-bridge converters provide positive or negative stepped volt- For unit 1:
age waveforms between the output terminals. The overall output V1i = V11 = Vdc , i = 2, . . . , n1 . (3)
voltage of the proposed cascaded multilevel converter is the sum
of output voltages of the submultilevel converters as follows: For unit 2:

n1
vo = vo1 + vo2 + · · · + vok . (1) V2i = V21 = V11 + 2 V1j = (2n1 + 1)Vdc , i = 2, . . . , n2 .
The different output voltage levels can be determined by com- j =1
(4)
binations of switching states of each unit. If proper values for
For unit 3:
the dc voltage sources are selected, then  the output
 i voltage of
the converter can be obtained between (− ki=1 nj =1 Vij ) and 
n1 
n2
k  n i V3i = V31 = V11 + 2 V1j + 2 V2j
(+ i=1 j =1 Vij ). If the number of dc voltage sources in j =1 j =1
basic units is considered equal to 1, then there is no need for
switches in basic units. In this state, the dc voltage source is = (2n1 + 1)(2n2 + 1)Vdc , i = 2, . . . , n3 . (5)
directly connected to the full-bridge converter. In other words, In general, for the mth unit:
this topology is equivalent to the CHB converter.
Although the latter topology requires multiple dc sources, 
m −1 
nj

but these may be suitable for the cases, which have possible Vm i = Vm 1 = V11 + 2 Vj l
combination of photovoltaic panels, fuel cells, or energy stor- j =1 l=1

age devices, such as capacitors or batteries. When ac voltage 

m −1
is available, multiple dc sources can be generated using iso- = (2nj + 1)Vdc , i = 2, . . . , nm . (6)
lated transformers and rectifiers [20]. It is important to mention j =1
that this topology requires less dc voltage sources considering
The maximum output voltage Vo m ax is obtained as follows:
variety and number compared to topologies presented in [20]
and [21]. This is a great advantage in practice, as it will be shown 
k 
ni 
k

in the following sections. Vo m ax = Vij = (ni × Vi1 ). (7)

i=1 j =1 i=1

III. DETERMINATION OF THE MAGNITUDES The number of output voltage steps can be determined by the
OF THE DC VOLTAGE SOURCES following equation:
To provide a large number of output steps without increas- 
k
ing the number of inverters, asymmetric structures can be used. Nstep,1 = (2ni + 1)
In [23] and [24], dc voltage sources in conventional cascaded i=1
multilevel inverters have been proposed to be chosen according
= (2n1 + 1) × (2n2 + 1) × · · · × (2nk + 1). (8)
to a geometric progression with a factor of 2 or 3. In fact, a
proper choice of voltage asymmetry among cells can produce
a different combination of voltage levels and eliminate redun- B. Second Proposed Method
dancies. For the proposed topology, in order to have unequal In the second method, the normalized values of dc voltage
values for vo and produce linear steps, three different methods sources in each unit of the proposed topology are proposed to
for the determination of magnitudes of the dc voltage sources be chosen according to the following procedure:

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3112 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

For unit 1: the number of submultilevel converters and components can be

chosen in order to obtain an optimal structure for each special
V11 = Vdc (9)
objective. This leads to the reduction in the cost, weight, and
V1i = 2V11 = 2Vdc , i = 2, . . . , n1 . (10) installation area of the converter. In this section, these optimal
structures are investigated.
For unit 2:

n1
V21 = V11 + 2 V1i = (4n1 − 1)Vdc (11) A. Optimal Structure for Maximum Number of Voltage Steps
i=1 With Constant Number of Switches
V2i = 2V21 = 2(4n1 − 1)Vdc , i = 2, . . . , n2 . (12) The desirable objective in a multilevel converter is to obtain
the maximum number of steps for minimum number of switches.
In general, for the mth unit: If the number of switches Nswitch is constant in the proposed

m −1 
ni 
m −1 topology, then, the maximum number of output voltage step
Vm 1 = V11 + 2 Vij = (4ni − 1)Vdc (13) should be determined.
i=1 j =1 i=1 Suppose that the proposed topology consists of a series of

m −1 k submultilevel converters and each of these has ni dc voltage
Vm i = 2 Vm 1 = 2 (4nj − 1)Vdc , i = 2, . . . , nm . (14) sources (i = 1, 2, . . . , k), then, we have
j =1
Nswitch = 2(n1 + n2 + · · · + nk ) + 4k. (21)
The maximum output voltage is obtained as follows:
To determine the dc voltage sources for three proposed methods,

k 
ni 
k
Vo m ax = Vij = [(2 ni − 1) × Vi1 ]. (15) the numbers of voltage steps are given by (8), (16), and (20).
i=1 j =1 i=1 Considering these equations and (21), the product of the num-
bers (whose summation is constant) will be maximized, when
The number of generated steps in the output voltage is ex-
the following equation is valid:
pressed by the following equation:

k n1 = n2 = · · · = nk = n. (22)
Nstep,2 = (4ni − 1). (16)
i=1 From (21) and (22), it is clear that we have

C. Third Proposed Method Nswitch

k= . (23)
2n + 4
The third method for the determination of magnitudes of dc
voltage sources is in binary fashion in each unit, which results The value of n must be determined. Considering (8), (16),
in an exponential increase in the number of overall output steps. (20), and (22), the maximum number of voltage steps with three
For the mth unit, the dc voltage sources are determined ac- methods can be, respectively, calculated as follows:
cording to the following equation:
Nstep,1 = (2n + 1)k

m −1 
ni 
m −1
Vm 1 = V11 + 2 Vij = (2n i +1 − 1)Vdc (17) Nstep,2 = (4n − 1)k
i=1 j =1 i=1
Nstep,3 = (2n +1 − 1)k . (24)
i−1
Vm i = 2 Vm 1 , i = 2, . . . , nm . (18)
Considering (23) and (24), it is clear that we have
The peak value of the output voltage is obtained as follows:

k 
ni 
k Nstep,1 = [(2n + 1)1/(2n +4) ]N s w i t c h
Vo m ax = Vij = [(2n i − 1) × Vi1 ]. (19) Nstep,2 = [(4n − 1)1/(2n +4) ]N s w i t c h
i=1 j =1 i=1

The number of output voltage steps can be determined by the Nstep,3 = [(2n +1 − 1)1/(2n +4) ]N s w i t c h . (25)
following equation:
Fig. 3 shows the variation of (2n + 1)1/(2n +4) , (4n −

k 1)1/(2n +4) , and (2n +1 − 1)1/(2n +4) versus n. It is evident that
Nstep,3 = (2n i +1 − 1) (20) the maximum number of voltage steps for the first and second
i=1 methods is obtained for n = 2. This means that a structure con-
sisting of two dc voltage sources (i.e., four switches) in each
IV. OPTIMAL STRUCTURES
basic unit can provide maximum step voltages for vo with a
In the proposed topology, there are different submultilevels minimum numbers of switches. For the third method, the max-
arrangements for a specified number of dc voltage sources to ob- imum is theoretically obtained for n = ∞. This means that a
tain different number of steps at the output voltage and utilizing structure consisting of one basic unit with available switches is
a different number of switches. It is worthwhile to notice that desirable for a constant number of switches.

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EBRAHIMI et al.: NEW TOPOLOGY OF CASCADED MULTILEVEL CONVERTERS 3113

Fig. 3. Variation of (2n + 1)1 / (2 n + 4 ) , (4n − 1)1 / (2 n + 4 ) , and (2 n + 1 −

Fig. 5. Variation of (2n + 4)/ ln(2n + 1), (2n + 4)/ ln(4n − 1), and
1)1 / (2 n + 4 ) versus n. (2n + 4)/ ln(2n + 1 − 1) versus n.

voltage source provides a maximum number of voltage steps

for vo with a minimum number of dc sources. It is necessary
to note that the proposed topology is basically a conventional
cascaded multilevel converter.

C. Optimal Structure for Minimum Number of Switches With

Constant Number of Voltage Steps
Suppose that Nstep is the number of voltage steps considered
Fig. 4. Variation of (2n + 1)1 / n , (4n − 1)1 / n , and (2 n + 1 − 1)1 / n versus for voltage vo . In this case, the topology, which can produce
n. Nstep steps with the minimum number of switches, should be
determined.
It is clear that the number of components should be integer. With respect to Section IV-A, it is evident that the maximum
Therefore, if the result is not an integer number, then it should number of voltage steps is obtained for equal number of switches
be automatically rounded off to the nearest integer number. in the basic units. Thus, if the number of switches in each unit is
assumed to be equal ton, then considering (21), (22), and (24),
B. Optimal Structure for Maximum Number of Voltage Steps the total numbers of switches Nswitch with the three methods,
With Constant Number of dc Voltage Sources can be, respectively, obtained as follows:
The next objective is expressed as follows. Suppose that the (2n + 4)
Nswitch, 1 = (2n + 4)k = ln(Nstep ) ×
number of dc voltage sources is constant and equal to Nsource . ln(2n + 1)
Find a topology, which provides the maximum number of volt- (2n + 4)
age steps. Nswitch, 2 = (2n + 4)k = ln(Nstep ) ×
ln(4n − 1)
Suppose that the proposed topology consists of a series of k
submultilevel converters. Each of these consists of ni dc voltage (2n + 4)
Nswitch, 3 = (2n + 4)k = ln(Nstep ) × . (29)
sources (for i = 1, 2, . . . , k). Thus ln(2n +1 − 1)

k Fig. 5 shows the variation of (2n+4)/ln(2n+1), (2n + 4)/
Nsource = ni = n1 + n2 + · · · + nk . (26) ln(4n − 1), and (2n + 4)/ln(2n +1 − 1) versus n. It is clear that
i=1 the numbers of switches for a constant Nstep will be minimized
Considering (21), the number of dc voltage sources can be at the minimum point of these figures. Therefore, n = 2 results
written as follows: in the minimum number of switches, to realize Nstep values
for the first and the second methods. For the third method, the
Nsource = n × k. (27) optimal value is theoretically obtained for n = ∞.
Using (24), the maximum number of voltage steps will be
determined as follows: V. COMPARISON OF THE PROPOSED TOPOLOGY
WITH OTHER TOPOLOGIES
Nstep,1 = [(2n + 1)1/n ]N s o u r c e
In this section, the proposed topology is compared with two
Nstep,2 = [(4n − 1)1/n ]N s o u r c e other topologies recommended in [20] and [21]. The first com-
parison index is the number of IGBTs. It is important to note
Nstep,3 = [(2n +1 − 1)1/n ]N s o u r c e . (28)
that the presented topology in [20] has been used bidirectional
Fig. 4 shows the variation of (2n + 1)1/n , (4n − 1)1/n , and switches that are composed of two IGBTs. But in the proposed
(2n +1
− 1)1/n versus n. It is clear that the maximum number topology of this paper and [21], the switches are composed of
of voltage steps for first, second, and third methods are obtained one IGBT. Therefore, to compare the different topologies, the
for n = 1. Thus, a structure consisting of units with one dc numbers of IGBTs (instead of switches) are used in this paper.

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3114 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 7. Blocking voltages on switches to realize N ste p -step voltage in pro-

posed topology and those presented in [20] and [21].

(30) can be considered as a criterion for comparison of different

topologies considering the maximum voltage on switches [20].
A lower value indicates that a smaller voltage is applied to the
terminal of switches, which is considered as an advantage. With
respect to Fig. 2, the following equations can be obtained:

n
Vswitch,u ,j = 2 Vj i , j = 1, . . . , k. (31)
i=1

Therefore, the peak voltage of switches of the basic unit can

be written as follows:

k 
n
Vswitch,U = 2 Vj i = Vdc × (Nstep − 1). (32)
j =1 i=1

The peak voltage of switches in the jth full-bridge converter

can be calculated as follows:
Fig. 6. Number of IGBTs to realizeN ste p -steps voltage by proposed topology 
n

using: (a) first; (b) second; and (c) third methods in comparison with topologies Vswitch,b,j = 2 × Vj i , j = 1, . . . , k. (33)
presented in [20] and [21]. i=1

Therefore, the peak voltage of switches of full-bridge con-

It is noticeable that the number of IGBTs and the antiparal- verters can be obtained as follows:
lel diodes are the same. Fig. 6 compares the number of IGBTs 
k
NIGBT versus the number of output voltage steps Nstep for three Vswitch,B = Vswitch,b,j = Vdc × (Nstep − 1). (34)
methods of determination of dc voltage sources in the topology j =1
recommended in this paper and topologies presented in [20] Considering (32) and (34), (30) can be rewritten as follows:
and [21]. It is obvious that the proposed topology needs fewer
IGBTs to realize Nstep steps for vo . Vswitch = 2Vdc × (Nstep − 1), Nstep ≥ 2. (35)
The second comparison index is the blocking voltages on
Fig. 7 compares the normalized blocking voltages on switches
switches. The voltage and current ratings of switches in a multi-
to realize Nstep -step voltage by the proposed topology and those
level converter play an important role in the cost and realization
presented in [20] and [21]. It is clear that the blocking voltage on
of the multilevel converter. In all topologies, currents of all
switches in the proposed topology is less than that recommended
switches are equal to the rated current of the load. This is, how-
in [20] for realizing Nstep -step voltage for vo . It should be
ever, not the case for the voltage. Suppose that the peak voltage
noted that the proposed topology utilize multiple cascaded full-
of switches Vswitch is represented by the following equation:
bridges in the output side of the converter while the presented
Vswitch = Vswitch,U + Vswitch,B topology in [20] and [21] utilize one full-bridge in the output
side. According to (34), the overall peak voltage of the full-

k 
k
bridge converters in the proposed topology is equal to those
= Vswitch,u ,j + Vswitch,b,j (30)
presented in [20] and [21]. But, in topologies presented in [20]
j =1 j =1
and [21], this voltage is related to only one full-bridge converter.
where Vswitch ,U and Vswitch, B are the peak voltage of units This leads to restriction on the high-voltage applications.
and full-bridges switches, respectively. Also, Vswitch, u , j and The last comparison index is the losses of switches. In the
Vswitch, b, j represent the peak voltage of switches in the jth proposed topology, for half cycle, the antiparallel diodes and
basic unit and jth full-bridge converter, respectively. Therefore, IGBTs of ON-switches are conduct for ϕ radian and (π − ϕ)

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EBRAHIMI et al.: NEW TOPOLOGY OF CASCADED MULTILEVEL CONVERTERS 3115

Fig. 8. Normalized switching losses of the proposed topology and that pre-
sented in [21] versus N ste p -step voltage.

radian, respectively. ϕ is the power factor angle. The total con-

duction losses of the switches are calculated as follows:
 2
2 Rd Im
Pcond = k(n + 2) Vd Im (1 − cos ϕ) + (2ϕ − sin(2ϕ))
π 4
 π 
β +1 β +1
+VT Im (1 + cos ϕ) + RT Im sin (ωt) dωt
ϕ

(36)
where Im is the peak value of the output current. VT and Vd are
the threshold voltages of IGBTs and diodes, respectively. RT
and Rd are the equivalent resistances of voltage drop across the Fig. 9. Optimal multilevel structure with minimum number of used switches
based on (a) proposed topology, (b) topology presented in [20] and (c) topology
IGBTs and diodes, respectively. β is a constant and depends on presented in [21].
the used IGBTs. At a particular temperature, the semiconductor
specifications from the manufacturer can be used to approximate presented in Fig. 9(a). As can be seen in this figure, the number
semiconductor losses. For specified switches, the conduction of IGBTs and dc voltage sources are 16 and 4, respectively.
losses depend on the load current and power factor. In this design, the converter is able to generate 49 steps in the
The total switching losses in the proposed topology can be output voltage.
obtained as follows: The structure of the optimal multilevel converter with the min-
 Vdc I imum number of used switches designed based on the topology
Psw = (k + n)(2n + 1)k −1 f (tON + tOFF ) (37) presented in [20] is shown in Fig. 9(b). This topology requires
3
bidirectional switches with the capability of blocking voltage
where tON and tOFF are the rise and the fall times of the
and conducting current in both directions. The bidirectional
switches. Fig. 8 shows the normalized switching losses versus
switch arrangement, which consists of two common emitter IG-
the number of output voltage steps for proposed topology. For
BTs and two antiparallel diodes has been used for this topology.
calculation of losses, it is assuming the IGBTs and the diodes
It is noticeable that in the full-bridge circuit, similar to other
in both topologies are the same. This comparison shows that
two topologies, unidirectional switches are used. In this struc-
the proposed topology has less switching losses than [21]. The
ture, the number of IGBTs and dc voltage sources are 22 and 6,
switching losses of topology presented in [20] depend on the
respectively, and the number of voltage steps is 53.
utilized snubber circuit in switches. Therefore, this topology is
If this design is accomplished based on the topology presented
not in this comparison.
in [21], 28 switches with 12 dc voltage sources should be used,
as been shown in Fig. 9(c). In this converter, the number of
VI. DESIGN OF MULTILEVEL CONVERTER BASED ON
voltage steps is 47.
PROPOSED TOPOLOGY The blocking voltage on all of switches in Fig. 9(a), (b), and
This section outlines the design procedure of a multilevel con- (c) are 960, 1674.4, and 956.8 V, respectively. It is worth to note
verter based on the proposed topology and those recommended that the sum of the blocking voltages on full-bridges switches
in [20] and [21]. The converter is a single-phase multilevel con- for all topologies is almost the same and equal to 480 V. But, in
verter with a minimum of 45 voltage steps and a peak value of the proposed topology, the blocking voltage on switches in each
240 V. In this design, the magnitudes of dc voltage sources are full-bridge converter is near to the maximum output voltage of
determined by the second proposed method. It should be noted adjoining units. On the other hand, the blocking voltage in [20]
that on-state voltage drops of switches have been neglected. The and [21] is near to the maximum output voltage of the converter.
optimal multilevel structure for the minimum number of used This problem restricts the multilevel converter for high-voltage
switches based on the proposed topology (see Sections II–III) is applications.

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3116 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

Fig. 12. THD of the output voltage waveform versus N ste p step.
Fig. 10. Photo of prototype.
TABLE II
ON SWITCHES LOOK-UP TABLE

Fig. 11. Control block diagram. where Vo,n is the rms of the n order component of the output
voltage. Vo,rm s and Vo,1 being the rms values of the output
voltage and the fundamental of the output voltage, respectively.
VII. SIMULATION AND MEASUREMENT RESULTS The values of Vo,rm s and Vo,1 are calculated using the following
equation, respectively:
To study the performance of the proposed multilevel con-
 ⎛ ⎞2
verter, shown in Fig. 9(a), a single-phase 49-level prototype √ 
 ∞ Nstep
has been modeled and built. The PSCAD/EMTDC software 2 2Vdc   ⎝  cos(nαi ) ⎠
Vo,rm s =  (39)
has been used for simulations. Each switch is an antiparallel π n
n =1 i=1
connection of an IGBT and a diode. The IGBTs used for the
prototype are BUP306D with internal antiparallel diodes with √
2 2Vdc 
Nstep
voltage and current ratings equal to 1200 V and 20 A, respec- Vo,1 = cos(αi ) (40)
tively. The 89C52 microcontroller by ATMEL Company has π i=1
been used to generate the switching pattern. The required dc
voltage sources have been provided by cascaded connections of where the parameters α1 , α2 . . . αN s t e p are switching angles and
dc power supplies. Fig. 10 shows a photo of the prototype. given by the following equation:
There are several modulation techniques for multilevel con- 
i − 0.5
verters [25]–[28]. In this paper, the fundamental frequency- αi = arcsin i = 1, 2, . . . , Nstep .
Nstep
switching technique has been used. Fig. 11 shows the control
block diagram of the converter. The main objective of the con- Fig. 12 shows the relation between the voltage step and the
trol system is the synthesis of the output voltage with minimum THD.
error with respect to the reference voltage. It is important to note Table II shows the ON switches look-up table for different
that the calculation of the optimal switching angles for selective voltage levels (steps). This converter is able to generate all even
harmonics elimination or minimization of total harmonic dis- and odd voltage steps (from −24 to 24 pu for 10-V base). As an
tortion (THD) is not the objective of this paper. The THD of the example, the following voltage waveform should be generated:
sinusoidal stepped waveform is defined as follows: ⎧

  ⎨100 cos(100πt) + 80 cos(300πt), 0 ≤ t < 20 ms
⎪
∞ 2 vo (t) = 120 + 60 cos(100πt), 20 ≤ t < 40 ms
n =3,5,... Vo,n Vo,rm s ⎪
THD = = −1 (38) ⎩
Vo,1 Vo,1 −160 sin(100πt), 40 ≤ t < 60 ms.

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EBRAHIMI et al.: NEW TOPOLOGY OF CASCADED MULTILEVEL CONVERTERS 3117

Fig. 13. Output voltage waveforms: (a) simulation and (b) measurement
(Time/div = 10 ms).

Fig. 13 shows the simulated and measured output voltage wave-

forms. As can be seen, the proposed converter can generate
desired voltage waveforms.
In order to investigate waveforms of output voltages produced
by different basic units and submultilevel converters and the
output current, the converter has been designed and adjusted
to generate a 50 Hz, 29-level sinusoidal waveform. The test
has been performed on an R–L load (with R = 107 Ω and L =
55 mH). Considering the high number of voltage levels and due
to limitations of available dc voltage sources in the laboratory,
the amplitude of prototype dc voltage source of lower unit is
small. Therefore, conduction losses of IGBTs are near to the
amplitude of dc voltage sources. To avoid large distortions,
voltages of the experimental prototype are measured on no-load
condition.
Fig. 14 shows simulation and measurement results. The re-
sults have a good agreement with each other. There is a small
difference between the amplitudes of the simulation and ex-
perimental results due to the voltage drops on switches of the
prototype. As shown in Fig. 14, the output voltage of each ba-
sic unit has always zero or a positive value. The ac outputs of
full-bridge converter have been connected in series such that
the synthesized voltage waveform is the sum of outputs of full-
bridge converters. Considering the output voltage and current
waveforms, it is obvious that there is a phase difference between
the output voltage and current waveform, which is due to the
inductive characteristic of the load. As can be seen in these
waveforms, the output current has a low THD, meaning near
sinusoidal waveform. Since the load of the converter is almost a
low pass filter (R–L), the output current contains less high order
harmonics than the output voltage. For this case, THDs of the
output voltage and current based on simulations are 1.742% and Fig. 14. Simulation (left figure) and measurement (right figure) results
(Time/div = 5 ms) and (Voltage/div = 10 V): (a) output voltage of the first
0.417%, respectively. To generate a desired output with high basic unit; (b) output voltage of the second basic unit; (c) output voltage of
power quality, the number of voltage steps should be increased the first submultilevel converter; (d) output voltage of the second submultilevel
or other switching technique should be applied to the converter. converter; and (e) top and bottom: converter output voltage and current.

comparison among the proposed converter and other topologies

VIII. CONCLUSION has been provided. It is shown that the proposed topology, not
A new configuration for multilevel converter has been pro- only has lower number of switches and components, compared
posed, which is based on the cascaded connection of submul- to other topologies, but also the full-bridge converters operate at
tilevel converters. The suggested structure extends the design a lower voltage. This extends the applications of the proposed
flexibility and possibilities to optimize it for various objectives. converter for high voltages.
The proposed topology has been optimized in this paper for uti- The operation and performance of the proposed topology has
lizing a minimum number of switches and voltage sources. A been simulated and experimentally verified on a single-phase

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3118 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 11, NOVEMBER 2011

49-level converter prototype. It is shown that the simulations [23] M. Manjrekar and T. A. Lipo, “A hybrid multilevel inverter topology for
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Electron. Conf., 2010, Jun. 2010. Exchange Service) from 1993 to 1996.

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