SEMICONDUCTOR TECHNICAL DATA

 




HighPerformance SiliconGate CMOS
The MC574HC4046A is similar in function to the MC14046 Metal gate
CMOS device. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC4046A phaselocked loop contains three phase comparators, a
voltagecontrolled oscillator (VCO) and unity gain opamp DEM OUT. The
comparators have two common signal inputs, COMP IN, and SIG IN. Input
SIG IN and COMP IN can be used directly coupled to large voltage signals, or
indirectly coupled (with a series capacitor to small voltage signals). The
selfbias circuit adjusts small voltage signals in the linear region of the
amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error
signal PC1 OUT and maintains 90 degrees phase shift at the center
frequency between SIG IN and COMP IN signals (both at 50% duty cycle).
Phase comparator 2 (with leadingedge sensing logic) provides digital error
signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift
between SIG IN and COMP IN signals (duty cycle is immaterial). The linear
VCO produces an output signal VCO OUT whose frequency is determined by
the voltage of input VCO IN signal and the capacitor and resistors connected
to pins C1A, C1B, R1 and R2. The unity gain opamp output DEM OUT with
an external resistor is used where the VCO IN signal is needed but no loading
can be tolerated. The inhibit input, when high, disables the VCO and all
opamps to minimize standby power consumption.
Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding,
data synchronization and conditioning, voltagetofrequency conversion
and motor speed control.

16
1

Symbol

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCOIN
DEMOUT
R1
R2
PC2OUT
SIGIN
PC3OUT
VCC

D SUFFIX
SOIC PACKAGE
CASE 751B05

16
1

ORDERING INFORMATION
MC74HCXXXXAN
MC74HCXXXXAD

PCPout

16

VCC

PC1out

15

PC3out

COMPin

14

SIGin

VCOout

13

PC2out

INH

12

R2

C1A

11

R1

C1B

10

DEMout

GND

VCOin

Name and Function

Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Inhibit Input
Capacitor C1 Connection A
Capacitor C1 Connection B
Ground (0 V) VSS
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage

10/95

Motorola, Inc. 1995

31

Plastic
SOIC

PIN ASSIGNMENT

Output Drive Capability: 10 LSTTL Loads

Low Power Consumption Characteristic of CMOS Devices
Operating Speeds Similar to LSTTL
Wide Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0 A Maximum (except SIGIN and COMPIN)
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Low Quiescent Current: 80 A Maximum (VCO disabled)
High Noise Immunity Characteristic of CMOS Devices
Diode Protection on all Inputs
Chip Complexity: 279 FETs or 70 Equivalent Gates
Pin No.

N SUFFIX
PLASTIC PACKAGE
CASE 64808

REV 6

This datasheet has been downloaded from http://www.digchip.com at this page

MC74HC4046A

MAXIMUM RATINGS*
Symbol
VCC

Parameter

DC Supply Voltage (Referenced to GND)

Value

Unit

0.5 to + 7.0

V
V

Vin

DC Input Voltage (Referenced to GND)

1.5 to VCC + 1.5

Vout

DC Output Voltage (Referenced to GND)

0.5 to VCC + 0.5

DC Input Current, per Pin

20

mA

Iout

DC Output Current, per Pin

25

mA

ICC

DC Supply Current, VCC and GND Pins

50

mA

PD

Power Dissipation in Still Air

750
500

mW

Tstg

Storage Temperature

65 to + 150

_C

Iin

TL

Plastic DIP
SOIC Package

This device contains protection

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.

_C

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP and SOIC Package

260

* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

VCC

Min

Max

Unit

3.0

6.0

DC Supply Voltage (Referenced to GND)

VCC

DC Supply Voltage (Referenced to GND) NONVCO

2.0

6.0

Vin, Vout

DC Input Voltage, Output Voltage (Referenced to GND)

VCC

55

+ 125

_C

0
0
0

1000
500
400

ns

TA

Operating Temperature, All Package Types

tr, tf

Input Rise and Fall Time

(Pin 5)

VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V

[Phase Comparator Section]

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
Volts

55 to
25_C

85C

125C

Unit

VIH

Minimum HighLevel Input

Voltage DC Coupled
SIGIN, COMPIN

Vout = 0.1 V or VCC 0.1 V

|Iout| 20 A

2.0
4.5
6.0

1.5
3.15
4.2

1.5
3.15
4.2

1.5
3.15
4.2

VIL

Maximum LowLevel Input

Voltage DC Coupled
SIGIN, COMPIN

Vout = 0.1 V or VCC 0.1 V

|Iout| 20 A

2.0
4.5
6.0

0.5
1.35
1.8

0.5
1.35
1.8

0.5
1.35
1.8

Minimum HighLevel
Output Voltage
PCPOUT, PCnOUT

Vin = VIH or VIL

|Iout| 20 A

2.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

Vin = VIH or VIL

|Iout| 4.0 mA
|Iout| 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

VOH

(continued)

MOTOROLA

32

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS continued (Voltages Referenced to GND)
Guaranteed Limit
Symbol
VOL

VCC
Volts

55 to
25_C

85C

125C

Unit

Vout = 0.1 V or VCC 0.1 V

|Iout| 20 A

2.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL

|Iout| 4.0 mA
|Iout| 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Parameter

Test Conditions

Maximum LowLevel
Output Voltage QaQh
PCPOUT, PCnOUT

Maximum Input Leakage Current

SIGIN, COMPIN

Vin = VCC or GND

2.0
3.0
4.5
6.0

3.0
7.0
18.0
30.0

4.0
9.0
23.0
38.0

5.0
11.0
27.0
45.0

IOZ

Maximum ThreeState
Leakage Current
PC2OUT

Output in HighImpedance State

Vin = VIH or VIL
Vout = VCC or GND

6.0

0.5

5.0

10

ICC

Maximum Quiescent Supply

Current (per Package)
(VCO disabled)
Pins 3, 5 and 14 at VCC
Pin 9 at GND; Input Leakage at
Pins 3 and 14 to be excluded

Vin = VCC or GND

|Iout| = 0 A

6.0

4.0

40

160

Iin

NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).

[Phase Comparator Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol

Parameter

Guaranteed Limit

VCC
Volts

55 to 25_C

85C

125C

Unit

tPLH,
tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT

(Figure 1)

2.0
4.5
6.0

175
35
30

220
44
37

265
53
45

ns

tPLH,
tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT

(Figure 1)

2.0
4.5
6.0

340
68
58

425
85
72

510
102
87

ns

tPLH,
tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT

(Figure 1)

2.0
4.5
6.0

270
54
46

340
68
58

405
81
69

ns

tPLZ,
tPHZ

Maximum Propagation Delay, SIGIN/COMPIN Output

Disable Time to PC2OUT (Figures 2 and 3)

2.0
4.5
6.0

200
40
34

250
50
43

300
60
51

ns

tPZH,
tPZL

Maximum Propagation Delay, SIGIN/COMPIN Output

Enable Time to PC2OUT (Figures 2 and 3)

2.0
4.5
6.0

230
46
39

290
58
49

345
69
59

ns

tTLH,
tTHL

Maximum Output Transition Time

(Figure 1)

2.0
4.5
6.0

75
15
13

95
19
16

110
22
19

ns

HighSpeed CMOS Logic Data

DL129 Rev 6

33

MOTOROLA

MC74HC4046A
[VCO Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol

Parameter

Test Conditions

VCC
Volts

55 to
25_C

85C

125C

Unit

VIH

Minimum HighLevel
Input Voltage
INH

Vout = 0.1 V or VCC 0.1 V

|Iout| 20 A

3.0
4.5
6.0

2.1
3.15
4.2

2.1
3.15
4.2

2.1
3.15
4.2

VIL

Maximum LowLevel
Input Voltage
INH

Vout = 0.1 V or VCC 0.1 V

|Iout| 20 A

3.0
4.5
6.0

0.90
1.35
1.8

0.9
1.35
1.8

0.9
1.35
1.8

VOH

Minimum HighLevel
Output Voltage
VCOOUT

Vin = VIH or VIL

|Iout| 20 A

3.0
4.5
6.0

1.9
4.4
5.9

1.9
4.4
5.9

1.9
4.4
5.9

Vin = VIH or VIL

|Iout| 4.0 mA
|Iout| 5.2 mA

4.5
6.0

3.98
5.48

3.84
5.34

3.7
5.2

Vout = 0.1 V or VCC 0.1 V

|Iout| 20 A

3.0
4.5
6.0

0.1
0.1
0.1

0.1
0.1
0.1

0.1
0.1
0.1

Vin = VIH or VIL

|Iout| 4.0 mA
|Iout| 5.2 mA

4.5
6.0

0.26
0.26

0.33
0.33

0.4
0.4

Vin = VCC or GND

6.0

0.1

1.0

1.0

VOL

Iin

Maximum LowLevel
Output Voltage
VCOOUT

Maximum Input
Leakage Current
INH, VCOIN

VVCOIN Operating Voltage Range at

VCOIN over the range
specified for R1; For linearity
see Fig. 15A, Parallel value of
R1 and R2 should be > 2.7 k
R1

INH = VIL

Resistor Range

R2

C1

Capacitor Range

MOTOROLA

34

Min

Max

Min

Max

Min

Max

3.0
4.5
6.0

0.1
0.1
0.1

1.0
2.5
4.0

0.1
0.1
0.1

1.0
2.5
4.0

0.1
0.1
0.1

1.0
2.5
4.0

3.0
4.5
6.0

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
4.5
6.0

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
3.0
3.0

300
300
300

3.0
4.5
6.0

40
40
40

No
Limit

pF

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
[VCO Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit

Symbol

VCC
Volts

Parameter

85C

55 to 25_C
Min

Max

Min

Max

125C
Min

Max

Unit

f/T

Frequency Stability with

Temperature Changes
(Figure 13A, B, C)

3.0
4.5
6.0

fo

VCO Center Frequency

(Duty Factor = 50%)
(Figure 14A, B, C, D)

3.0
4.5
6.0

fVCO

VCO Frequency Linearity

3.0
4.5
6.0

See Figures 15A, B, C

VCO

Duty Factor at VCOOUT

3.0
4.5
6.0

Typical 50%

%/K

3
11
13

MHz

[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit

Symbol
RS

VOFF

RD

Parameter

Test Conditions

VCC
Volts

55 to 25_C
Min

Max

50
50
50

300
300
300

85C
Min

Max

125C
Min

Max

Unit

Resistor Range

At RS > 300 k the

Leakage Current can
Influence VDEMOUT

3.0
4.5
6.0

Offset Voltage
VCOIN to VDEMOUT

Vi = VVCOIN = 1/2 VCC;

Values taken over RS
Range.

3.0
4.5
6.0

See Figure 12

mV

Dynamic Output
Resistance at DEMOUT

VDEMOUT = 1/2 VCC

3.0
4.5
6.0

Typical 25

HighSpeed CMOS Logic Data

DL129 Rev 6

35

MOTOROLA

MC74HC4046A
SWITCHING WAVEFORMS

SIGIN
INPUT

VCC

SIGIN, COMPIN
INPUTS

VCC
50%

50%

GND
VCC

GND
tPHL

COMPIN
INPUT

tPLH
90%
50%

PCPOUT, PC1OUT
PC3OUT
OUTPUTS

50%

PC2OUT
OUTPUT

10%

tTHL

tTLH

GND

tPHZ

tPZH

VOH

90%
50%

Figure 1.

HIGH
IMPEDANCE

Figure 2.

VCC
SIGIN
INPUT

TEST POINT

50%
GND
OUTPUT
VCC

COMPIN
INPUT

DEVICE
UNDER
TEST

50%

PC2OUT
OUTPUT

GND

tPLZ

tPZL

HIGH
IMPEDANCE

50%
10%

*INCLUDES ALL PROBE AND JIG CAPACITANCE

VOL

Figure 3.

MOTOROLA

CL*

Figure 4. Test Circuit

36

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
the capacitor. Once the voltage across the capacitor charges
up to Vref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side
of the capacitor. The output from the internal logic is then taken to VCO output (Pin 4).
The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input
accessible without degrading the loop performance, the VCO
input voltage is buffered through a unity gain Opamp to Demod Output. This Opamp can drive loads of 50K ohms or
more and provides no loading effects to the VCO input voltage (see Figure 12).
An inhibit input is provided to allow disabling of the VCO
and all Opamps (see Figure 5). This is useful if the internal
VCO is not being used. A logic high on inhibit disables the
VCO and all Opamps, minimizing standby power consumption.

DETAILED CIRCUIT DESCRIPTION

Voltage Controlled Oscillator/Demodulator Output
The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1
are selected to determine the center frequency of the VCO
(see typical performance curves Figure 14). R2 can be used
to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased.
If R2 is omitted the VCO range is from 0 Hz. The effect of R2
is shown in Figure 24, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for a
narrow lock range, large swings on the VCO input will cause
less frequency variation.
Internally, the resistors set a current in a current mirror, as
shown in Figure 5. The mirrored current drives one side of

VREF
12

+
_

I1
CURRENT
MIRROR
I1 + I2 = I3

R2

VCOIN

9
11

+
_

I2

VCOOUT

I3

R1

+
_

DEMODOUT 10

C1
(EXTERNAL)
7

INH

Vref
+

Figure 5. Logic Diagram for VCO

HighSpeed CMOS Logic Data

DL129 Rev 6

37

MOTOROLA

MC74HC4046A
The output of the VCO is a standard high speed CMOS
output with an equivalent LSTTL fan out of 10. The VCO
output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or
feed external prescalers (counters) to enable frequency synthesis.

COMPIN. The SIGIN and COMPIN have a special DC bias

network that enables AC coupling of input signals. If the signals are not AC coupled, standard 54HC/74HC input levels
are required. Both input structures are shown in Figure 6.
The outputs of these comparators are essentially standard
54HC/74HC outputs (comparator 2 is TRISTATEABLE). In
normal operation VCC and ground voltage levels are fed to
the loop filter. This differs from some phase detectors which
supply a current to the loop filter and should be considered in
the design. (The MC14046 also provides a voltage).

Phase Comparators
All three phase comparators have two inputs, SIGIN and
VCC

VCC

SIGIN
PC2OUT

14

13

VCC

COMPIN
3

PCPOUT
1
PC3OUT
15
PC1OUT
2

Figure 6. Logic Diagram for Phase Comparators

Phase Comparator 1

VCO input voltage must increase and the phase difference

between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the VCO input is at 0 V. This requires
the phase detector output to be grounded; hence, the two input signals must be in phase. When the input frequency is
fmax, the VCO input must be VCC and the phase detector inputs must be 180 degrees out of phase.

This comparator is a simple XOR gate similar to the

54/74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and output
waveforms are shown in Figure 7. The output of the phase
detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto
if initially out of lock is defined as the capture range. The capture range for phase detector 1 is dependent on the loop filter
design. The capture range can be as large as the lock range,
which is equal to the VCO frequency range.
To see how the detector operates, refer to Figure 7. When
two square wave signals are applied to this comparator, an
output waveform (whose duty cycle is dependent on the
phase difference between the two signals) results. As the
phase difference increases, the output duty cycle increases
and the voltage after the loop filter increases. In order to
achieve lock when the PLL input frequency increases, the

MOTOROLA

SIGIN
COMPIN
PC1OUT

VCC

VCOIN

GND

Figure 7. Typical Waveforms for PLL Using

Phase Comparator 1

38

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
The XOR is more susceptible to locking onto harmonics of
the SIGIN than the digital phase detector 2. For instance, a
signal 2 times the VCO frequency results in the same output
duty cycle as a signal equal to the VCO frequency. The difference is that the output frequency of the 2f example is twice
that of the other example. The loop filter and VCO range
should be designed to prevent locking on to harmonics.

Phase comparator 2 is more susceptible to noise, causing

the PLL to unlock. If a noise pulse is seen on the SIGIN, the
comparator treats it as another positive edge of the SIGIN
and will cause the output to go high until the VCO leading
edge is seen, potentially for an entire SIGIN period. This
would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed
for only the short duration of the noise spike and would cause
less upset.

Phase Comparator 2
This detector is a digital memory network. It consists of
four flipflops and some gating logic, a three state output and
a phase pulse output as shown in Figure 6. This comparator
acts only on the positive edges of the input signals and is independent of duty cycle.
Phase comparator 2 operates in such a way as to force the
PLL into lock with 0 phase difference between the VCO output and the signal input positive waveform edges. Figure 8
shows some typical loop waveforms. First assume that SIGIN
is leading the COMPIN. This means that the VCOs frequency must be increased to bring its leading edge into proper
phase alignment. Thus the phase detector 2 output is set
high. This will cause the loop filter to charge up the VCO input, increasing the VCO frequency. Once the leading edge of
the COMP IN is detected, the output goes TRISTATE holding the VCO input at the loop filter voltage. If the VCO still
lags the SIGIN then the phase detector will again charge up
the VCO input for the time between the leading edges of both
waveforms.
If the VCO leads the SIGIN then when the leading edge of
the VCO is seen; the output of the phase comparator goes
low. This discharges the loop filter until the leading edge of
the SIGIN is detected at which time the output disables itself
again. This has the effect of slowing down the VCO to again
make the rising edges of both waveforms coincidental.
When the PLL is out of lock, the VCO will be running either
slower or faster than the SIGIN. If it is running slower the
phase detector will see more SIGIN rising edges and so the
output of the phase comparator will be high a majority of the
time, raising the VCOs frequency. Conversely, if the VCO is
running faster than the SIGIN, the output of the detector will
be low most of the time and the VCOs output frequency will
be decreased.
As one can see, when the PLL is locked, the output of
phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is
TRISTATED, the PCP output is high. This output can be
used to determine when the PLL is in the locked condition.
This detector has several interesting characteristics. Over
the entire VCO frequency range there is no phase difference
between the COMPIN and the SIGIN. The lock range of the
PLL is the same as the capture range. Minimal power was
consumed in the loop filter since in lock the detector output is
a high impedance. When no SIGIN is present, the detector
will see only VCO leading edges, so the comparator output
will stay low, forcing the VCO to fmin.

HighSpeed CMOS Logic Data

DL129 Rev 6

Phase Comparator 3
This is a positive edgetriggered sequential phase detector using an RS flipflop as shown in Figure 6. When the PLL
is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIG IN and COMP IN
are not important. It has some similar characteristics to the
edge sensitive comparator. To see how this detector works,
assume input pulses are applied to the SIG IN and COMP IN s
as shown in Figure 9. When the SIGIN leads the COMPIN,
the flop is set. This will charge the loop filter and cause the
VCO to speed up, bringing the comparator into phase with
the SIG IN. The phase angle between SIGIN and COMP IN varies from 0 to 360 and is 180 at fo. The voltage swing for
PC3 is greater than for PC2 but consequently has more ripple
in the signal to the VCO. When no SIG IN is present the VCO
will be forced to fmax as opposed to fmin when PC2 is used.
The operating characteristics of all three phase comparators should be compared to the requirements of the system
design and the appropriate one should be used.

SIGIN
COMPIN
PC2OUT

VCC
HIGH IMPEDANCE OFFSTATE

GND

VCOIN
PCPOUT

Figure 8. Typical Waveforms for PLL Using

Phase Comparator 2

SIGIN
COMPIN
PC3OUT
VCOIN

VCC
GND

Figure 9. Typical Waveform for PLL Using

Phase Comparator 3

39

MOTOROLA

MC74HC4046A

VCC=6.0 V

800
VCC=3.0 V

4.0

VCC=4.5 V

I I ( A)

R I = (k )

VCC=3.0 V
400
VCC=4.5 V

VCC=6.0 V

0
1/2 VCC1.0 V

1/2 VCC

1/2 VCC+1.0 V

4.0
1/2VCC 500 mV

VI (V)

Figure 10. Input Resistance at SIGIN, COMPIN with

VI = 1.0 V at SelfBias Point

1/2 VCC
VI (V)

1/2 VCC + 500 mV

Figure 11. Input Current at SIGIN, COMPIN with

VI = 500 mV at SelfBias Point

DEMOD OUT
15
6.0

VDEM
OUT

VCC=6.0 V RS=300 k
VCC=6.0 V RS=50 k
VCC=4.5 V RS=300 k
VCC=4.5 V RS=50 k

FREQUENCY STABILITY (%)

R1=3.0 k

5.0

R1=300 k
R1=100 k

R1=300 k

5.0

R1=3.0 k
15
100

3.0
VCOIN (V)

R1=100 k
5.0
0
5.0
VCC = 4.5 V
C1 = 100 pF; R2 = ; VVCOIN = 1/2 VCC

10
15
100

50

0
50
100
AMBIENT TEMPERATURE (C)

150

150

R1=3.0 k
R1=300 k
R1=100 k

8.0
6.0
4.0
2.0
0
2.0
4.0
6.0
8.0
10
100

VCC = 6.0 V
C1 = 100 pF; R2 = ; VVCOIN=1/2 VCC
50

50

100

150

AMBIENT TEMPERATURE (C)

Figure 13B. Frequency Stability versus Ambient

Temperature: VCC = 4.5 V

MOTOROLA

0
50
100
AMBIENT TEMPERATURE (C)

10
FREQUENCY STABILITY (%)

R1=300 k

10

VCC = 3.0 V
C1 = 100 pF; R2 = ; VVCOIN=1/3 VCC

Figure 13A. Frequency Stability versus Ambient

Temperature: VCC = 3.0 V

R1=3.0 k

15

50

6.0

Figure 12. Offset Voltage at Demodulator Output as

a Function of VCOIN and RS

FREQUENCY STABILITY (%)

R1=100 k

10

VCC=3.0 V RS=300 k
VCC=3.0 V RS=50 k
0

10

Figure 13C. Frequency Stability versus Ambient

Temperature: VCC = 6.0 V

310

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
23

70

21

60

19

VCC = 3.0 V

f VCO (KHz)

f VCO(MHz)

50
VCC = 4.5 V

17
15
13

R1 = 3.0 k
C1 = 39 pF

9
7.0

0.5

1.0

1.5

40
30
20

VCC = 3.0 V

11

2.0

2.5

3.0

3.5

R1 = 3.0 k
C1 = 0.1 F

10
0

4.0

0.5

1.0

1.5

VVCOIN (V)

Figure 14A. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)

2.0
2.5
VVCOIN (V)

3.0

3.5

4.0

Figure 14B. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)
1.0

2.0

VCC = 6.0 V

0.9

VCC = 4.5 V

VCC = 4.5 V

0.8

VCC = 6.0 V

0.7
f VCO (KHz)

VCC = 3.0 V
f VCO(MHz)

VCC = 6.0 V

VCC = 4.5 V

VCC = 6.0 V

1.0

VCC = 3.0 V

0.6
0.5
0.4
0.3
0.2

R1 = 300 k
C1 = 39 pF
0
0

0.5

1.0

1.5

2.0
2.5
VVCOIN (V)

3.0

3.5

4.0

4.5

Figure 14C. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)
2.0

0.5

1.0

1.5

2.0
2.5
3.0
VVCOIN (V)

3.5

4.0

4.5

Figure 14D. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)

C1 = 1.0 F

1.0
f VCO (%)

VCC=
4.5 V
6.0 V

f2

3.0 V

f0
f0

4.5 V

f1

6.0 V

1.0

3.0 V
2.0

R1 = 300 k
C1 = 0.1 F

0.1

100

R2 = ; V = 0.5 V

C1 = 39 pF
101

102

MIN

103

R1 (k)

1/2 VCC

MAX

V = 0.5 V OVER THE VCC RANGE:

FOR VCO LINEARITY
f0 = (f1 + f2) / 2
LINEARITY = (f0 f0) / f0) x 100%

Figure 15A. Frequency Linearity versus

R1, C1 and VCC

HighSpeed CMOS Logic Data

DL129 Rev 6

Figure 15B. Definition of VCO Frequency Linearity

311

MOTOROLA

MC74HC4046A
106

106

CL = 50 pF; R2 = ; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;

CL = 50 pF; R1 = ; VVCOIN = 0 V; Tamb = 25C

VVCOIN = 1/3 VCC FOR VCC = 3.0 V; Tamb = 25C

105
VCC = 6.0 V, C1 = 40 pF
VCC = 6.0 V, C1 = 1.0 F

104

PR2 ( W)

PR1 ( W)

105
VCC = 6.0 V, C1 = 40 pF
VCC = 6.0 V, C1 = 1.0 F

104

VCC = 4.5 V, C1 = 40 pF
VCC = 4.5 V, C1 = 1.0 F

VCC = 4.5 V, C1 = 40 pF
VCC = 4.5 V, C1 = 1.0 F

VCC = 3.0 V, C1 = 40 pF
VCC = 3.0 V, C1 = 1.0 F

103
100

101

R1 (k)

102

VCC = 3.0 V, C1 = 1.0 F

103
100

103

101

Figure 16. Power Dissipation versus R1

102

103

R1 = R2 = ; Tamb = 25C

107
106
VCO

(Hz)

102
VCC=6.0 V

105

INH = GND; Tamb = 25C; R2 = ; VVCOIN = 1/3 VCC

VCC =
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V

R1=3.0 k

PDEM ( W)

R2 (k)

Figure 17. Power Dissipation versus R2

108

103

VCC = 3.0 V, C1 = 40 pF

VCC=4.5 V

101

104

VCC=3.0 V

R1=100 k

103

R1=300 k

100
101

102
RS (k)

102

103

101

off (Hz)

106
105

VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25C

6.0 V
4.5 V
3.0 V

104

105

106

VCC = 4.5 V; R2 =

107

2 fL (Hz)

107

104

108

R1 = ; VVCOIN = 1/2 VCC FOR VCC = 4.5 V AND 6.0 V;

VCC =
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V

103
C1 (pF)

Figure 19. VCO Center Frequency versus C1

Figure 18. DC Power Dissipation of

Demodulator versus RS

108

102

106
105

R2=3.0 k

104

103
R2=100 k

102
101

103

R2=300 k

101

102

103

104

105

102

106

107

C1 (pF)

105

104

103

102

101

R1C1

Figure 20. Frequency Offset versus C1

MOTOROLA

106

Figure 21. Typical Frequency Lock Range (2fL)

versus R1C1

312

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
20

14
R1=3.0 k

C1=39 pF
12

R1=10 k

10

R1=20 k

FREQ. (MHz)

FREQ. (MHz)

15

R1=30 k

10

R1=40 k

8.0
R1=3 k
R1=10 k
R1=20 k
R1=30 k
R1=40 k
R1=50 k
R1=100 k
R1=300 k

6.0
4.0

R1=50 k

5.0

2.0
R1=100 k

C1=39 pF

R1=300 k

2.0
1.0

101

102

103

104

105

100

101

102

R2 ( k)

103

104

105

106

R2 ( k)

Figure 22. R2 versus fmax

Figure 23. R2 versus fmin

20

2f L (MHz)

C1=39 pF

R1=10 k
R1=3.0 k
R1=20 k

10

R1=30 k
R1=40 k
R1=50 k

R1=100 k
R1=300 k

0
1.0

101

102

103

104

105

R2 ( k)

Figure 24. R2 versus Frequency Lock Range (2fL)

HighSpeed CMOS Logic Data

DL129 Rev 6

313

MOTOROLA

MC74HC4046A
APPLICATION INFORMATION
The following information is a guide for approximate values of R1, R2, and C1. Figures 19, 20, and 21 should be used as
references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC
ELECTRICAL CHARACTERISTICS tables.
Phase Comparator 1
R2 =

R2

0R

Phase Comparator 2
R2 =

R2

0R

Phase Comparator 3
R2 =

R2

0R

Given f0

Given f0 and fL

Given fmax and f0

Given f0 and fL

Given fmax and f0

Given f0 and fL

Use f0 with Figure

19 to determine
R1 and C1.

Calculate fmin
fmin = f0fL
Determine values
of C1 and R2 from
Figure 20.

Determine the
value of R1 and
C1 using Figure 19
and use Figure 21
to obtain 2fL and
then use this to
calculate fmin.

Calculate fmin
fmin = f0fL
Determine values
of C1 and R2 from
Figure 20.

Determine the
value of R1 and
C1 using Figure 19
and Figure 21 to
obtain 2fL and
then use this to
calculate fmin.

Calculate fmin:
fmin = f0fL
Determine values
of C1 and R2 from
Figure 20.

(see Figure 23 for

characteristics of
the VCO operation)

MOTOROLA

Determine R1C1
from Figure 21.

Determine R1C1
from Figure 21.

Determine R1C1
from Figure 21.

Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.

Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.

Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.

(see Figure 24 for

characteristics of the
VCO operation)

(see Figure 24 for

characteristics of the
VCO operation)

(see Figure 24 for

characteristics of the
VCO operation)

314

HighSpeed CMOS Logic Data

DL129 Rev 6

MC74HC4046A
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ISSUE R

16

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.

DIM
A
B
C
D
F
G
H
J
K
L
M
S

S
T

SEATING
PLANE

H
D 16 PL
0.25 (0.010)

G
T A

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J

16

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

P 8 PL
0.25 (0.010)

R X 45
C

T
SEATING

PLANE

M
D 16 PL
0.25 (0.010)

INCHES
MILLIMETERS
MIN
MAX
MIN
MAX
0.740 0.770 18.80 19.55
6.35
0.250 0.270
6.85
3.69
0.145 0.175
4.44
0.39
0.015 0.021
0.53
1.02
0.040 0.070
1.77
0.100 BSC
2.54 BSC
0.050 BSC
1.27 BSC
0.21
0.008 0.015
0.38
2.80
0.110 0.130
3.30
7.50
0.295 0.305
7.74
0
0
10
10
0.020 0.040
0.51
1.01

DIM
A
B
C
D
F
G
J
K
M
P
R

MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7
0
6.20
5.80
0.50
0.25

INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
7
0.229 0.244
0.010 0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different
applications. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does
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HighSpeed CMOS Logic Data

DL129 Rev 6

CODELINE

315

*MC74HC4046A/D*

MC74HC4046A/D
MOTOROLA