SEMICONDUCTOR TECHNICAL DATA

 
! "!
"!"! !  ! Do Not Use for New Designs
High–Performance Silicon–Gate CMOS THIS DEVICE WILL BE SUPERCEDED
BY MC54/74HC164A IN THE
The MC54/74HC164 is identical in pinout to the LS164. The device inputs SECOND QUARTER OF 1996
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The MC54/74HC164 is an 8–bit, serial–input to parallel–output shift
register. Two serial data inputs, A1 and A2, are provided so that one input J SUFFIX
may be used as a data enable. Data is entered on each rising edge of the CERAMIC PACKAGE
14 CASE 632–08
clock. The active–low asynchronous Reset overrides the Clock and Serial
Data inputs. 1

• Output Drive Capability: 10 LSTTL Loads

• Outputs Directly Interface to CMOS, NMOS, and TTL N SUFFIX
• Operating Voltage Range: 2 to 6 V PLASTIC PACKAGE
14
• Low Input Current: 1 µA CASE 646–06
• High Noise Immunity Characteristic of CMOS Devices 1

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A D SUFFIX
• Chip Complexity: 244 FETs or 61 Equivalent Gates 14 SOIC PACKAGE
1 CASE 751A–03

ORDERING INFORMATION
LOGIC DIAGRAM MC54HCXXXJ Ceramic
MC74HCXXXN Plastic
1 MC74HCXXXD SOIC
SERIAL A1 3
DATA DATA QA
2 4
INPUTS A2 QB
5 PIN ASSIGNMENT
QC
6 PARALLEL
QD A1 1 14 VCC
10 DATA
QE OUTPUTS A2 2 13 QH
11
QF QA 3 12 QG
12 QB 4 11 QF
QG
8
CLOCK 13 QC 5 10 QE
QH
QD 6 9 RESET
GND 7 8 CLOCK
9
RESET PIN 14 = VCC
PIN 7 = GND

FUNCTION TABLE
Inputs Outputs
Reset Clock A1 A2 QA QB … QH
L X X X L L … L
H X X No Change
H H D D QAn … QGn
H D H D QAn … QGn

D = data input
QAn – QGn = data shifted from the preceding
stage on a rising edge at the clock input.

10/95

 Motorola, Inc. 1995 3–1 REV 7

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MC54/74HC164
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Value Unit This device contains protection

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V circuitry to guard against damage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
due to high static voltages or electric
Vin DC Input Voltage (Referenced to GND) – 1.5 to VCC + 1.5 V fields. However, precautions must

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout DC Output Voltage (Referenced to GND) – 0.5 to VCC + 0.5 V
be taken to avoid applications of any

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
voltage higher than maximum rated
Iin DC Input Current, per Pin ± 20 mA voltages to this high–impedance cir-

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
cuit. For proper operation, Vin and
Iout DC Output Current, per Pin ± 25 mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vout should be constrained to the
ICC DC Supply Current, VCC and GND Pins ± 50 mA v
range GND (Vin or Vout) VCC. v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Unused inputs must always be
PD Power Dissipation in Still Air, Plastic or Ceramic DIP† 750 mW

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tied to an appropriate logic voltage
SOIC Package† 500 level (e.g., either GND or VCC).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _C
Tstg Storage Temperature – 65 to + 150 Unused outputs must be left open.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TL Lead Temperature, 1 mm from Case for 10 Seconds _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Plastic DIP or SOIC Package) 260
(Ceramic DIP) 300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
Ceramic DIP: – 10 mW/_C from 100_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SOIC Package: – 7 mW/_C from 65_ to 125_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TA Operating Temperature, All Package Types – 55 + 125 _C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Input Rise and Fall Time VCC = 2.0 V 0 1000 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
(Figure 1) VCC = 4.5 V 0 500
VCC = 6.0 V 0 400

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter Test Conditions V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIH Minimum High–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 1.5 1.5 1.5 V
v
Voltage |Iout| 20 µA 4.5 3.15 3.15 3.15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 4.2 4.2 4.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL Maximum Low–Level Input Vout = 0.1 V or VCC – 0.1 V 2.0 0.3 0.3 0.3 V
v
Voltage |Iout| 20 µA 4.5 0.9 0.9 0.9

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 1.2 1.2 1.2

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOH Minimum High–Level Output Vin = VIH or VIL 2.0 1.9 1.9 1.9 V
v
Voltage |Iout| 20 µA 4.5 4.4 4.4 4.4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 5.9 5.9 5.9
v
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VIH or VIL |Iout| 4.0 mA 4.5 3.98 3.84 3.70
|Iout| 5.2 mA 6.0 5.48 5.34 5.20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VOL Maximum Low–Level Output
v
Vin = VIH or VIL 2.0 0.1 0.1 0.1 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Voltage |Iout| 20 µA 4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v
Vin = VIH or VIL |Iout| 4.0 mA 4.5 0.26 0.33 0.40

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
|Iout| 5.2 mA 6.0 0.26 0.33 0.40
± 0.1 ± 1.0 ± 1.0 µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Iin Maximum Input Leakage Current Vin = VCC or GND 6.0
µA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ICC Maximum Quiescent Supply Vin = VCC or GND 6.0 8 80 160
Current (per Package) Iout = 0 µA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MOTOROLA 3–2 High–Speed CMOS Logic Data

DL129 — Rev 6
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MC54/74HC164

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
v ÎÎÎÎ
v ÎÎÎ
VCC – 55 to

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V 25_C 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
fmax Maximum Clock Frequency (50% Duty Cycle) 2.0 6.0 4.8 4.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figures 1 and 4) 4.5 30 24 20
6.0 35 28 24

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, Maximum Propagation Delay, Clock to Q 2.0 175 220 265 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL (Figures 1 and 4) 4.5 35 44 53

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 30 37 45

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPHL Maximum Propagation Delay, Reset to Q 2.0 205 255 310 ns
(Figures 2 and 4) 4.5 41 51 62

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 35 43 53

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, Maximum Output Transition Time, Any Output 2.0 75 95 110 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTHL (Figures 1 and 4) 4.5 15 19 22
6.0 13 16 19

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Cin
NOTES:
Maximum Input Capacitance — 10 10 10

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
pF

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Package)* 140 pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Guaranteed Limit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VCC – 55 to
v v 25_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Symbol Parameter V 85_C 125_C Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tsu Minimum Setup Time, A1 or A2 to Clock 2.0 50 65 75 ns
(Figure 3) 4.5 10 13 15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 9 11 13

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
th Minimum Hold Time, Clock to A1 or A2 2.0 5 5 5 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 3) 4.5 5 5 5
6.0 5 5 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
trec Minimum Recovery Time, Reset Inactive to Clock 2.0 5 5 5 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 2) 4.5 5 5 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 5 5 5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Clock 2.0 80 100 120 ns
(Figure 1) 4.5 16 20 24

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
6.0 14 17 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tw Minimum Pulse Width, Reset 2.0 80 100 120 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 2) 4.5 16 20 24
6.0 14 17 20

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tr, tf Maximum Input Rise and Fall Times 2.0 1000 1000 1000 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Figure 1) 4.5 500 500 500
6.0 400 400 400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

High–Speed CMOS Logic Data 3–3 MOTOROLA

DL129 — Rev 6
MC54/74HC164

PIN DESCRIPTIONS

INPUTS register is completely static, allowing clock rates down to DC

in a continuous or intermittent mode.
A1, A2 (Pins 1, 2)
OUTPUTS
Serial Data Inputs. Data at these inputs determine the data
to be entered into the first stage of the shift register. For a QA – QH (Pins 3, 4, 5, 6, 10, 11, 12, 13)
high level to be entered into the shift register, both A1 and A2 Parallel Shift Register Outputs. The shifted data is pres-
inputs must be high, thereby allowing one input to be used as ented at these outputs in true, or noninverted, form.
a data–enable input. When only one serial input is used, the
other must be connected to VCC. CONTROL INPUT

Reset (Pin 9)
Clock (Pin 8)
Active–Low, Asynchronous Reset Input. A low voltage ap-
Shift Register Clock. A positive–going transition on this pin plied to this input resets all internal flip–flops and sets Out-
shifts the data at each stage to the next stage. The shift puts QA – QH to the low level state.

SWITCHING WAVEFORMS

tr tf tw
VCC VCC
90% RESET 50%
CLOCK 50%
10% GND GND
tw tPHL
1/fmax
Q 50%
tPLH tPHL
90% trec
Q 50% VCC
10%
CLOCK 50%
tTLH tTHL GND

Figure 1. Figure 2.

TEST POINT

VALID OUTPUT
VCC DEVICE
A1 OR A2 50% UNDER
GND TEST CL*
tsu th
VCC
CLOCK 50%
GND
* Includes all probe and jig capacitance

Figure 3. Figure 4. Test Circuit

MOTOROLA 3–4 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC164

EXPANDED LOGIC DIAGRAM

8
CLOCK

1
A1
2 D Q D Q D Q D Q D Q D Q D Q D Q
A2
R R R R R R R R
9
RESET

3 4 5 6 10 11 12 13

QA QB QC QD QE QF QG QH

TIMING DIAGRAM

CLOCK
A1
A2

RESET
QA

QB

QC

QD

QE

QF

QG

QH

High–Speed CMOS Logic Data 3–5 MOTOROLA

DL129 — Rev 6
MC54/74HC164

OUTLINE DIMENSIONS

J SUFFIX
CERAMIC DIP PACKAGE
-A- CASE 632–08
ISSUE Y NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
14 8 Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
-B- 3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
1 7 4. DIMESNION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
-T-
SEATING K D 0.015 0.020 0.39 0.50
PLANE F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
F G N M J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
D 14 PL J 14 PL L 0.300 BSC 7.62 BSC
M 0° 15° 0° 15°
0.25 (0.010) M T A S 0.25 (0.010) M T B S
N 0.020 0.040 0.51 1.01

N SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06 NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
ISSUE L POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
L 0.300 BSC 7.62 BSC
SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03 NOTES:
–A– ISSUE F 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
14 8 MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
–B– P 7 PL PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G MILLIMETERS INCHES
R X 45° F
DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
SEATING K M J F 0.40 1.25 0.016 0.049
PLANE
D 14 PL G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S
K 0.10 0.25 0.004 0.009
M 0° 7° 0° 7°
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

MOTOROLA 3–6 High–Speed CMOS Logic Data

DL129 — Rev 6
 MC54/74HC164

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*MC54/74HC164/D*
◊ CODELINE MC54/74HC164/D
High–Speed CMOS Logic Data 3–7 MOTOROLA
DL129 — Rev 6
This datasheet has been download from:

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Datasheets for electronics components.