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    Watch Timer

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    wtn2013
    The watchdog timer on the 80C166 microcontroller provides a mechanism to recover from software or hardware failures. If the software fails to regularly service the watchdog timer before it overflows, an internal reset will be triggered. The watchdog timer has two registers - one read-only register that contains the current count, and a control register used to initialize and configure the watchdog timer. The watchdog timer can be clocked at either the CPU clock divided by 2 or 128, and its timeout period can be programmed by setting the reload value and clock prescaler. Regularly servicing the watchdog timer with a specific instruction prevents it from overflowing and triggering a reset.

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    Watch Timer

    Uploaded by

    wtn2013
    89 views4 pages
    The watchdog timer on the 80C166 microcontroller provides a mechanism to recover from software or hardware failures. If the software fails to regularly service the watchdog timer before it overflows, an internal reset will be triggered. The watchdog timer has two registers - one read-only register that contains the current count, and a control register used to initialize and configure the watchdog timer. The watchdog timer can be clocked at either the CPU clock divided by 2 or 128, and its timeout period can be programmed by setting the reload value and clock prescaler. Regularly servicing the watchdog timer with a specific instruction prevents it from overflowing and triggering a reset.

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    The watchdog timer on the 80C166 microcontroller provides a mechanism to recover from software or hardware failures. If the software fails to regularly service the watchdog timer before it overflows, an internal reset will be triggered. The watchdog timer has two registers - one read-only register that contains the current count, and a control register used to initialize and configure the watchdog timer. The watchdog timer can be clocked at either the CPU clock divided by 2 or 128, and its timeout period can be programmed by setting the reload value and clock prescaler. Regularly servicing the watchdog timer with a specific instruction prevents it from overflowing and triggering a reset.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    89 views4 pages

    Watch Timer

    Uploaded by

    wtn2013
    The watchdog timer on the 80C166 microcontroller provides a mechanism to recover from software or hardware failures. If the software fails to regularly service the watchdog timer before it overflows, an internal reset will be triggered. The watchdog timer has two registers - one read-only register that contains the current count, and a control register used to initialize and configure the watchdog timer. The watchdog timer can be clocked at either the CPU clock divided by 2 or 128, and its timeout period can be programmed by setting the reload value and clock prescaler. Regularly servicing the watchdog timer with a specific instruction prevents it from overflowing and triggering a reset.

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    The Watchdog Timer (WDT) / 80C166

    12

    The Watchdog Timer (WDT)

    To allow recovery from software or hardware failure, the 80C166 provides a Watchdog Timer. If the
    software fails to service this timer before an overflow occurs, an internal reset sequence will be
    initiated. This internal reset will also pull the RSTOUT pin low, which also resets the peripheral
    hardware, which might be the cause for the malfunction. When the watchdog timer is enabled and
    the software has been designed to service it regularly before it overflows, the watchdog timer will
    supervise the program execution, as it only will overflow if the program does not progress properly.
    The watchdog timer will also time out, if a software error was due to hardware related failures. This
    prevents the controller from malfunctioning for longer than a user-specified time.
    The watchdog timer provides two registers: a read-only timer register that contains the current
    count, and a control register for initialization.

    Reset Indication Pin

    RSTOUT

    Data Registers

    Control Registers

    WDT

    WDTCON

    Figure 12-1
    SFRs and Port Pins associated with the Watchdog Timer
    The watchdog timer is a 16-bit up counter which can be clocked with the CPU clock (fCPU) either
    divided by 2 or divided by 128. This 16-bit timer is realized as two concatenated 8-bit timers (see
    figure below). The upper 8 bits of the watchdog timer can be preset to a user-programmable value
    via a watchdog service access in order to vary the watchdog expire time. The lower 8 bits are reset
    on each service access.

    Figure 12-2
    Watchdog Timer Block Diagram

    Semiconductor Group

    12-1

    The Watchdog Timer (WDT) / 80C166

    Operation of the Watchdog Timer


    The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT,
    which is a non-bitaddressable read-only register. The operation of the Watchdog Timer is controlled
    by its bitaddressable Watchdog Timer Control Register WDTCON. This register specifies the reload
    value for the high byte of the timer, selects the input clock prescaling factor and provides a flag that
    indicates a watchdog timer overflow.
    WDTCON (FFAEH / D7H)
    15

    14

    13

    12

    SFR
    11

    10

    Reset Value: 000XH


    7

    WDTREL

    rw

    Bit

    Function

    WDTIN

    Watchdog Timer Input Frequency Selection


    0: Input frequency is fCPU / 2
    1: Input frequency is fCPU / 128

    WDTR

    Watchdog Timer Reset Indication Flag


    Set by the watchdog timer on an overflow.
    Cleared by a hardware reset or by the SRVWDT instruction.

    WDTREL

    Watchdog Timer Reload Value (for the high byte)

    WDT WDT
    R
    IN
    r

    rw

    Note: The reset value will be 0002H, if the reset was triggered by the watchdog timer (overflow). It
    will be 0000H otherwise.
    After any software reset, external hardware reset (see note), or watchdog timer reset, the watchdog
    timer is enabled and starts counting up from 0000H with the frequency fCPU/2. The input frequency
    may be switched to fCPU/128 by setting bit WDTIN. The watchdog timer can be disabled via the
    instruction DISWDT (Disable Watchdog Timer). Instruction DISWDT is a protected 32-bit instruction
    which will ONLY be executed during the time between a reset and execution of either the EINIT
    (End of Initialization) or the SRVWDT (Service Watchdog Timer) instruction. Either one of these
    instructions disables the execution of DISWDT.
    When the watchdog timer is not disabled via instruction DISWDT, it will continue counting up, even
    during Idle Mode. If it is not serviced via the instruction SRVWDT by the time the count reaches
    FFFFH the watchdog timer will overflow and cause an internal reset. This reset will pull the external
    reset indication pin RSTOUT low. It differs from a software or external hardware reset in that bit
    WDTR (Watchdog Timer Reset Indication Flag) of register WDTCON will be set. A hardware reset
    or the SRVWDT instruction will clear this bit. Bit WDTR can be examined by software in order to
    determine the cause of the reset.
    A watchdog reset will also complete a running external bus cycle before starting the internal reset
    sequence if this bus cycle does not use READY or samples READY active (low) after the
    programmed waitstates. Otherwise the external bus cycle will be aborted.
    Note: After a hardware reset that activates the Bootstrap Loader the watchdog timer will be
    disabled.
    Semiconductor Group

    12-2

    The Watchdog Timer (WDT) / 80C166

    To prevent the watchdog timer from overflowing, it must be serviced periodically by the user
    software. The watchdog timer is serviced with the instruction SRVWDT, which is a protected 32-bit
    instruction. Servicing the watchdog timer clears the low byte and reloads the high byte of the
    watchdog time register WDT with the preset value in bit field WDTREL, which is the high byte of
    register WDTCON. Servicing the watchdog timer will also reset bit WDTR. After being serviced the
    watchdog timer continues counting up from the value (<WDTREL> * 28). Instruction SRVWDT has
    been encoded in such a way that the chance of unintentionally servicing the watchdog timer (eg. by
    fetching and executing a bit pattern from a wrong location) is minimized. When instruction SRVWDT
    does not match the format for protected instructions, the Protection Fault Trap will be entered,
    rather than the instruction be executed.

    The time period for an overflow of the watchdog timer is programmable in two ways:
    the input frequency to the watchdog timer can be selected via bit WDTIN in register WDTCON
    to be either fCPU/2 or fCPU/128.
    the reload value WDTREL for the high byte of WDT can be programmed in register WDTCON.
    The period PWDT between servicing the watchdog timer and the next overflow can therefore be
    determined by the following formula:
    PWDT =

    2(1 + <WDTIN>*6) * (216 - <WDTREL> * 28)


    fCPU

    The table below marks the possible ranges for the watchdog time which can be achieved using a
    CPU clock of 20 MHz. Some numbers are rounded to 3 significant digits.

    Reload value
    in WDTREL

    Prescaler for fCPU


    2 (WDTIN = 0)

    128 (WDTIN = 1)

    FFH

    25.6 s

    1.6 ms

    00H

    6.55 ms

    419 ms

    Note: For safety reasons, the user is advised to rewrite WDTCON each time before the watchdog
    timer is serviced.

    Semiconductor Group

    12-3

    The Watchdog Timer (WDT) / 80C166

    Semiconductor Group

    12-4

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