UNIT-III

TIMERS, MIXED SIGNAL SYSTEMS

SYLLABUS

Timers:
Watchdog Timer, RTC, Timer-A, Measurement in capture mode, PWM
Generation.

Mixed-Signal Systems:
Comparator-A, ADC10 SAADC- Architecture, Operation-
Single conversion, Temperature sensor on ADC10, DTC in ADC10; ADC12-
Comparison with ADC10.

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 Timers
• Most modern microcontrollers provide - range of timers.
• MSP430 is no exception.
• A timer is a specialized type of clock which is used to measure time intervals.
• All devices contain two types of timer and some have five.
• Each type of timer module works in essentially the same way in all devices.
• Timer- A is identical in almost all MSP430s.
• For instance, except that a few have a different number of capture/compare channels.
1. Watch dog timer
2. Basic timer 1
3. Real-Time Clock
4. Timer-A
5. Timer-B

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Watchdog timer:
- present in all devices.
- Main function to protect the system against malfunctions.
- Protection is not needed then it can be used as an interval timer.
Basic timer1:
- Present in the MSP430x4xx family only.
- It provides the clock for the LCD and acts as an interval timer.
Real-time clock:
- Present in most recent MSP430x4xx devices.
- In which the basic timer has been extended to provide a real-time clock.
Timer_A:
- Present in all devices.
- Has 3 channels , more versatile than the simpler timers.
- Handle external i/p and o/p directly to measure f, time-stamp inputs, and drive
outputs at precisely specified times, either once or periodically.
- Handle Internal connections to other modules so that it can measure the
duration of a signal from the comparator, for instance.
-It can also generate interrupts
Timer_B:
- Present in larger devices of all families.
- It is similar to Timer_A with some extensions.
- More suitable for driving outputs such as pulse-width modulation.
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 WATCHDOG TIMER

The primary function of the WDT+ module is to perform a controlled system restart
after a software problem occurs. If the selected time interval expires, a system reset is
generated. If the watchdog function is not needed in an application, the module can be
configured as an interval timer and can generate interrupts at selected time intervals.
Features
• Four software-selectable time intervals
• Watchdog mode
• Interval mode
• Access to WDT+ control register is password protected
• Control of RST/NMI pin function
• Selectable clock source
• Can be stopped to conserve power
• Clock fail-safe feature

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 Watch dog timer
• The main purpose of the watchdog timer is to protect the system against failure of the software,
such as the program becoming trapped in an unintended, infinite loop.
• The watchdog counts up and resets the MSP430 when it reaches its limit.
• The code must therefore keep clearing the counter before the limit is reached to prevent a reset.
• The operation of the watchdog is controlled by the 16-bit register WDTCTL.
• It is guarded against accidental writes by requiring the password
WDTPW = 0x5A in the upper byte.
• A reset will occur if a value with an incorrect password is written to WDTCTL. This can be done
deliberately if you need to reset the chip from software. Reading WDTCTL returns 0x69 in the upper
byte, so reading WDTCTL and writing the value back violates the password and causes a reset.

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 WATCHDOG TIMER CONTROL REGISTER

• The watchdog counter is a 16-bit register WDTCNT, which is not visible to the user.
• Lower byte of WDTCTL contains the bits that control the operation of the watchdog timer.
Upper byte describes the Passwords for read and write operation.
• The RST/NMI pin is also configured using this register which is described in the “Non-maskable
Interrupts”.
• Most bits are reset to 0 after a power-on reset (POR) but are unaffected by a power-up clear (PUC).

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WDTPW : Watchdog timer password . Always read as 069H. Always written as 05AH.
WDTHOLD: watchdog timer hold bit.
WDTHOLD = 0 -> Watchdog timer not stopped
WDTHOLD = 1 -> Watchdog timer stopped
WDTNMIES: Watchdog timer non-maskable edge select.
WDTNMIES = 0 -> NMI in raising edge
WDTNMIES = 0 -> NMI in falling edge
 WDTNMI: Watchdog timer non-maskable interrupt.
WDTNMI = 0 -> Reset function
WDTNMI = 0 -> NMI function
 WDTTMSEL : Watchdog timer mode select. Watchdog timer can be operated in two different modes
Interval mode and Watchdog mode depending on the input bit .
WDTTMSEL = 0 -> Watchdog mode
WDTTMSEL = 1 -> Interval Mode

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• WDTCNTCL bit : Watchdog timer counter clear, labeled r0(w) this means that the bit always reads as 0 but a 1 can
be written to stimulate some action, clearing the counter in this case.
WDTCNTCL = 0 -> No Action Taken,
WDTCNTCL = 1 -> Counter value Cleared to 0000H
The task is often called petting, feeding, or kicking the dog.

• WDTSSEL: Watchdog timer source select bit: Chooses clock depending on the given input bit. By default it is
SMCLK
WDTSSEL = 0 -> SMCLK
WDTSSEL = 1 -> ACLK
• The reset output can be selected from bits 6, 9, 13, or 15 of the counter.
• The period is 26 = 64, 29= 512, 213 = 8192, 215 = 32,768 (default: around 32ms.) times the period of the clock. This
is controlled by the WDTISx bits in WDTCTL.
WDTISx : 0 0 = 215 (Watchdog timer clock source / 32768)
0 1 = 213 (Watchdog timer clock source / 8192)
1 0 = 29 (Watchdog timer clock source /512)
1 1 = 26 (Watchdog timer clock source / 64)
• The intervals are roughly 2, 16, 250, and 1000ms if the watchdog runs from ACLK at 32KHz.
• The watchdog timer sets the WDTIFG flag in the special function register IFG1. This is cleared by a power-on
reset but its value is preserved during a PUC. (This happens in overflow condition)

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Failsafe Clock Source for Watchdog Timer+
Newer devices, including the MSP430F2xx family and recent members of the MSP430x4xx, have
the enhanced watchdog timer+ (WDT+) which includes fail-safe logic to preserve the watchdog’s
clock.
This includes fail-safe logic to preserve the watchdog’s clock.
Suppose that the watchdog is configured to use ACLK and the program enters low-power mode 4 to
wait for an external interrupt.
The old watchdog (WDT) stops during LPM4 and resumes counting when the device is awakened.
In contrast, WDT+ does not let the device enter LPM4 because that would disable its clock.
Therefore it is not possible to use LPM4 with WDT+ active; the watchdog must first be stopped by
setting WDTHOLD.
Similarly, it is not possible to use LPM3 if WDT+ is active and gets its clock from SMCLK.
If its clock fails, WDT+ switches from ACLK or SMCLK to MCLK and takes this from the DCO if
an external crystal fails.
The watchdog interval may change dramatically but there must be serious problems elsewhere if
this happens

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 WATCHDOG AS AN INTERVAL TIMER

• The watchdog can be used as an interval timer if its protective function is not desired.
• Set the WDTTMSEL bit in WDTCTL for interval timer mode.
• The periods are the same as before and again WDTIFG is set when the timer reaches its
limit, but no reset occurs.
• The counter rolls over and restarts from 0.
• An interrupt is requested if the WDTIE bit in the special function register IE1 is set.
• This interrupt is maskable and as usual takes effect only if GIE is also set.
• The watchdog timer has its own interrupt vector, which is fairly high in priority but not
at the top.
• It is not the same as the reset vector, which is taken if the counter times out in
watchdog mode.
• The WDTIFG flag is automatically cleared when the interrupt is serviced. It can be
polled if interrupts are not used.
• Many applications need a periodic “tick,” for which the watchdog timer could be used
in interval mode.
• The disadvantage is the limited selection of periods, but 1s is convenient for a clock.
Some of the previous examples that used Timer_A could be rewritten for the watchdog
instead and its use is illustrated in the standard sets of code examples from TI.

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 WDT as interval mode
#include "MSP430G2553.h"

#include "intrinsics.h“

volatile uint16_t delay1,delay2;

void main(void)

WDTCTL = WDT_MDLY_0_5; // WDT as interval timer (period 0,5 ms)

IE1 |= WDTIE; // Enable WDT interrupt

P1DIR |= BIT0+BIT6; // Set P1.0 & P1.6 as output

P1OUT |= BIT0+BIT6; // P1.0 & P1.6 are ON at start

delay1 = 5000; // LED1 toggle period = 509 ms

delay2 = 10000; // LED1 toggle period = 1717 ms

__low_power_mode_1(); // Enable interrupt and enter LPM1 mode

}
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#pragma vector=WDT_VECTOR //Contd.,
Watchdog Interval Timer interrupt service

__interrupt void watchdog_timer(void)

if(--delay1==0)

{ // Countdown of intervals

P1OUT ^= BIT0; // Toggle LED1 (P1.0) state

delay1 = 5000; // Reload delay counter 1.

if(--delay2==0)

P1OUT ^= BIT6; // Toggle LED2 (P1.6) state

delay2 = 10000; // reload delay counter 2.

} 13
 Real-Time Clock (RTC)
A Real-Time Clock (RTC) module has been added to recent devices in the MSP430xFxx
family.
It counts seconds, minutes, hours, days, months, and years. Alternatively it can be used as
a straight forward counter.
Real time clock control register (RTCCTL) is shown below.

This register is initialized after a power-on reset, and the RTCHOLD bit is set so that the
clock does not run by default.
The current time and date are held in a set of registers that contain the following bytes:
• Second (RTCSEC).
• Minute (RTCMIN).
• Hour(RTCHOUR), which runs from 0–23 (24-hour format).
• Day of week (RTCDOW), which runs from 0–6.
• Day of month (RTCDAY).
• Month (RTCMON).
• Year (RTCYEARL), assuming BCD format.
• Century(RTCYEARH), assuming BCD format.
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The registers are arranged in pairs that can also be accessed as words.
For example, RTCYEAR = RTCYEARH : RTCYEARL and
RTCTIM0 = RTCMIN:RTCSEC.
The registers that hold the date and time are initialized when calendar mode is
selected but the user will obviously need to store the current values if “real” time is to be
real.
RTCDOW is effectively an independent 0–6 counter, incremented daily. The user must
initialize this appropriately and decide which day is the start of the week
There is no provision for a 12-hour clock with an AM/PM flag.
The Real-Time Clock has an interrupt flag RTCFG and corresponding enable bit RTCIE in
RTCCTL.
The flag is set every minute, every hour, daily at midnight, or daily at noon depending
on the RTCTEVx bits.

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 RTC Operation

Calendar Mode:
 Calendar mode is selected when RTCMODEx = 11.
 Switching from counter to calendar mode clears the seconds, minutes,
hours, day-of-week, years counts and sets day-of-month and months
counts to 1.
 When RTCBCD = 1, BCD format is selected for the calendar
registers.
Counter mode:
 Counter mode is selected when RTCMODEx < 11.
 In this mode, a 32-bit counter is provided that is directly accessible by
software.
 Switching from calendar mode to counter mode resets the count
value.

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It is maskable and can be used in two ways:

• Interrupts are generated by the Real-Time Clock module if RTCIE is set. Both
the BTIFG and RTCFG flags are set at an interrupt and cleared automatically
when it is serviced. The interval is determined by RTCTEVx.

• Interrupts come from Basic Timer1 as described earlier if RTCIE is clear. The
interval is determined by BTIPx. The Real-Time Clock sets its RTCFG flag
according to RTCTEVx but this does not request an interrupt. A program can poll
the flag to check whether an interval of time has elapsed and must clear RTCFG in
software.

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 TIMER-A
o
Timer block :
- 16 bit timer/counter
- 4 operating modes are present.
- 7 output modes are present
- has 3 capture/compare register channels(advanced MSP430 has 7)
- has extensive interrupt capabilities
- Selectable and configurable clock source.
- PWM capability.
- Capture/compare channels:
Capture : Each channel can Capture an input, which means recording the
“time” (the value in TAR) at which the input changes in TACCRn.
Compare: The current value of TAR with the value stored in TACCRn update
an output when they match.
o
Request an interrupt
o
Sampling mode : special mode used for serial communication.
o
Timer-A is modular and the number of CC-channels varies between devices.
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Timer_A showing the timer block and capture/compare channel 1.
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The timer has four modes of operation, selected with the MCx bits:
Stop (MC = 0): The timer is halted. All registers, including TAR, retain their values
so that the timer can be restarted later where it left off.
Up (1): The counter counts from 0 up to the value in TACCR0, the
capture/compare register for channel 0. It returns to 0 on the next clock transition.
The period is (TACCR0+1) counts. For example, if TACCR0 = 4, the sequence of
counts is 0, 1, 2,3, 4, 0, 1.

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Continuous (2): The counter runs freely through its full range from 0x0000 to
0xFFFF,at which point it overflows and rolls over back to 0. The period is 2 16 = 65,536
counts.
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Up/Down (3): The counter counts from 0 up to TACCR0, then down again to 0 and
repeats. The period is 2×TACCR0 counts. For example, if TACCR0 = 3, the sequence of
counts is 0, 1, 2, 3, 2, 1, 0, 1. 25
Resolution and period of Timer_A in the Continuous mode with
different clocks and input dividers.

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 Capture/Compare Channels
• Timer-A has 3 channels in most MSP430s.
• Channel 0 is lost to many applications because its register TACCR0 is needed to set
the limit of counting in up & up/down modes.
• Each channel is controlled by a register TACCTLn.

• Capture mode:
- Records the time – the value in TAR- at which event occurs on the input.
- The input usually CCIX8, can be either external or internal from another
peripheral or software, depending on board connections
• Compare mode:
- compare it specifies the time at which the output should next be changed and
an interrupt requested.
- This mode is selected with CAP bit.
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- This is cleared by default so that the channel is in compare mode.
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 Capture mode Hardware
• According to capture mode bit CMx – event can be Falling edge, raising edge, or both.
• Input to be captured will be selected by CCISx in TACCTLn.
 Two of these will be CCInA nad CCInB (comes from outside timer module).
- CCInA is connected to external pin TAn.
- CCInB is connected internally to another modules.
EXAMPLE : Internal connections of F20X1
CCI0B - Connected to ACLK
- Allows frequency of SMCLK to be compared with ACLK.
- Enables frequency- locked loop to be completed in s/w to synchronize two
clocks.
CCI1B – Comes from CAOUT (O/P of comparator)
- Allows precise timing of a measurement without overhead & delay that would
arise if s/w were needed to trigger a capture when CAOUT changed.
 The other two inputs that can be selected are constants, GND and VCC. Main purpose is
to allow captures from s/w.
• State of selected input can always be read in CCI bit of TACCTLn.
• Capture hardware therefore includes a synchronizer, which is enabled by setting the SCS bit.
This bit is should be set for safety.
• When capture occurs, the current value of TAR is copied into TACCRn and the channel flag
TACCRn CCIFG is set.
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• COV capture overflow bit is set if another capture occurs before TACCRn has been read.
 Compare mode hardware
• Purpose of compare mode is to produce an output and interrupt at the time stored in
TACCRn.
• Several actions are triggered when TAR counts to the value in TACCRn:
 Internal signal EQUn - set
 This in turn raises CCIFGn flag and requests an interrupt if enabled.
 Output signal OUTn is changed according to the mode set by OUTMODx bits in
TACCTLn.
 I/p signal to the capture hardware, CCI, is latched into SCCI bit.
The output modes are listed below:
mode Actions at TACCRx Most useful in counter mode
0 OUT BIT Output is controlled by OUT bit
1 SET Continuous
2 TOGGLE/RESET Up/Down
3 SET/RESET Up
4 TOGGLE Doubled period
5 RESET Continuous
6 TOGGLE/SET Up/down
7 RESET/SET up 30
 Out Modes
• Output (Mode-0) : O/p is directly controlled by OUT bit in TACCTLn; TAR has no
influence.
• Toggle (Mode-4) :
- Provides a simple way of switching a load on and off for equal times (50% DC).
- Can be used with channel 0 in up & up/down modes.
- Disadvantage : Load is toggled only once per cycle of timer and freq is halved.
• SET (Mode-1) & Reset (Mode-5) : Typically used for single changes in the O/P, usually in
continuous mode.
• Reset/Set (Mode-7) & Set/Reset (Mode-3) :
- Typically used for periodic, edge aligned PWM in up mode of the counter.
- First action takes place when TAR matches TACCRn.
- Second action occurs when TAR returns to 0, one count after the match to TACCR0
• Toggle/Reset (Mode-2) & Toggle/set (Mode-6) :
- Typically used for centre - aligned PWM in up/down mode.
- 1st action takes place when TAR matches TACCRn
- 2nd action occurs when TAR matches TACCR0.
- Second action is needed only once to fix sign of the waveform
Note: TACCTLn register are cleared by a POR , not affected by PUC.
Default channel state is compare mode.
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Interrupts from Timer-A

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Measurement in the capture mode

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 Comparator_A

Figure : Simplified block diagram of Comparator_A+, showing some of the bits that control its
operation.
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 Comparator_A Internal view

Figure : Simplified block diagram of Comparator_A+, showing some of the bits that control
its operation.
Comparator_A+ Registers
CACTL1 (Control Register-1)
CACTL2 (Control Register-2)
CAPD (Port Disable Register)
 ADC
Features of ADC:
 Accuracy:

 Resolution/Precision:

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 Architecture of the ADC10

Figure . Simplified block diagram of the ADC10.

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Core
 ADC10 is a 10-bit, switched-capacitor, SAR core. The ADC10ON bit
enables the core and a flag ADC10BUSY is set while sampling and
conversion is in progress.

 This can be taken from MCLK, SMCLK, ACLK, or the module’s

internal oscillator ADC10OSC, selected with the ADC10SSELx bits.

The ADC10 can use MCLK. The internal oscillator runs nominally at
5MHz. The frequency of the clock can be divided by 2,3,...,7,8 by
configuring the ADC10DIVx bits. The output of the divider feeds both the
SAR core and sample-and-hold blocks.

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Sample-and-Hold Unit:
The time is chosen with the ADC10SHTx bits, which allow 4, 8, 16, or 64 cycles of
ADC10CLK.

Input Selection:
 A multiplexer selects the input from eight external pins A0–A7
and four internal connections. Two of the internal connections are for optional, external
reference voltages, which share the pins for A3 and A4 in many devices.
 The other two internal connections are A10 to a temperature
sensor and A11 to Vmid = ½ (VCC +VSS), which is provided to monitor the supply
voltage.

Conversion Trigger
 A conversion can be triggered by ENC bit is set and setting the ADC10SC.
There are direct connections on-chip to the output units of channels 0–2 of Timer_A.
These are the same signals OUTn that can be brought out to the pins for PWM.

Interrupts
The interrupt flag ADC10IFG is raised when the result is written to ADC10MEM except
when the DTC (Data Transfer Controller) is used, when it is set after a block has been
completed.

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 Timing and Current Consumption of the ADC10

Conversions take 13 cycles of ADC10CLK. The final cycle is used to copy

the result into ADC10MEM and adjust its format if necessary. 12 cycles are
needed for the.

• 0.25mA for the internal reference alone, without the buffer.

• 0.6mA for the SAR core.
• 0.5mA for the buffer at reduced speed (ADC10SR = 1 and fADC10CLK
below 1.5MHz), in which case 4.5s should be allowed for it to settle.
• 1.1mA for the buffer at full speed (ADC10SR = 0), in which case 2s is
sufficient for settling.

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Basic Operation of the ADC10
1. Configure the ADC10, including the ADC10ON bit to enable the
module. The ENC bit must be clear during this operation because
most bits in ADC10CTL0 and ADC10CTL1 can be changed only when
ENC = 0.
2. Set the ENC bit to enable a conversion. This cannot be done while
the module is being configured in the previous step.
3. Trigger the conversion, either by setting the ADC10SC bit or by an
edge from Timer_A.
Single Conversion with the ADC10 Triggered by Software

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 ADC12
The principal distinctions between the ADC12 and ADC10:
The output has 12 bits rather than 10 the input capacitance is higher at 40pF.
 Sampling time should be extended to 9‫ז‬.
 The internal voltage reference requires an external storage capacitor. The

capacitor is not required if you use VSS and VCC as references.

 The sampling time can be controlled in two ways. The first, called pulse mode
and SAMPCON input from the signal that triggers the
conversion. This is called the extended sample mode.
 Analog inputs are enabled with PnSEL rather than a separate analog enable
register.

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Memory 0 is used for the conversion must set it up with
theADC12MCTL0 register. This contains the reference voltages and
input channel used for the conversion.
 ADC12IE contains bits to enable interrupts from the 16 memories.

Process :

1. The process for each reading starts with an interrupt from Basic
Timer1. The voltage reference is turned on in the ISR and the
watchdog timer is configured to give a further interrupt after 16ms.

2. The reference voltage should be stable by the time of the interrupt

from the watchdog timer so the ADC12 is turned on and a new
reading is enabled and triggered.

3. The final interrupt occurs when the conversion is complete. The

ADC12 is disabled and turned off, as is the voltage reference. This
interrupt vector is shared by all flags within ADC12 so its origin is
checked by using the vector register ADC12IV. 57
The temperature is calculated from the converted value in much the
same way as for the ADC10. Its scaling factor is 4200 rather than 420 so
that the result is in tenths of a degree rather than integral degrees and
the division is by 4096 to reflect the greater resolution of the ADC12. A
32-bit variable is needed to store the intermediate values but the final
result should fit in 16 bits.

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Several application
1. A Simple Glass Breakage Detector Using the MSP430. This uses the
ADC10 and op-amps integrated into the F2274 to digitize the sound
picked up by a microphone.
2. Implementing a Smoke Detector with the MSP430F2012. An infrared
LED and photodiode are used to detect the presence of smoke. The
signal is too small to be converted directly so an external op-amp is
required.
3. Oversampling the ADC12 for Higher Resolution (slaa323). This shows
how an average can be taken over a block of measurements to
improve the resolution of an ADC.
4. Li-Ion Battery Charger Solution Using the MSP430 (slaa287). An
ADC10 is used to monitor the voltage across the battery, the
charging current, and the temperature of the battery, sensed by a
thermistor.
5. Solid State Voice Recorder Using Flash MSP430 (slaa123). The sound
is digitized by an ADC12 triggered by Timer_B to avoid jitter in the
sampling clock. 59
 Analog-to-Digital Conversion: Sigma–Delta
high precision and low speed.
The sigma–delta ADCs in the MSP430 work at around 1ksps rather
than 100ksps for the SAR ADCs.
Architecture of a Sigma–Delta ADC
The analog input goes into a difference amplifier, which subtracts (hence

“delta”) the current value of the output to leave the error.

 This error is integrated (much the same as summation, hence “sigma”).
 The output of the integrator is converted from analog to digital in an
ADC at fm. This is performed by a 1-bit ADC, which is just a comparator.
 This digital signal is fed back and converted back to analog in a DAC so
that it can be subtracted from the input, thus forming a feedback loop. The
1-bit DAC is no more than a switch. 60
The second part of the ADC handles purely digital signals.
• The digital signal is processed by a low-pass filter. This is needed
because the stream of samples from the modulator can represent
frequencies up to ½ fm but the slower, final output can represent
frequencies only up to ½ fs. Thus we must remove frequencies above
½ fs to avoid aliasing at the final sampling rate.

• The filtered digital signal is then decimated to reduce the rate of

samples from fm to fs. The term decimated ought to mean “divided by
10” but is used for any factor in practice.

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