Microphone Preamplifier with

Variable Compression and Noise Gating

SSM2166

Data Sheet

and to eliminate popping. In the 1:1 compression setting, the

SSM2166 can be programmed with a fixed gain of up to 20 dB;
this gain is in addition to the variable gain in other compression
settings. The input buffer can also be configured for front-end
gains of 0 dB to 20 dB. A downward expander (noise gate) prevents
amplification of noise or hum. This results in optimized signal
levels prior to digitization, thereby eliminating the need for
additional gain or attenuation in the digital domain that may
add noise or impair accuracy of speech recognition algorithms.
The compression ratio and time constants are set externally. A
high degree of flexibility is provided by the VCA gain, rotation
point, and noise gate adjustment pins.

FEATURES
Complete microphone conditioner in a 14-lead SOIC package
Single 5 V operation
Adjustable noise gate threshold
Compression ratio set by external resistor
Automatic limiting featureprevents ADC overload
Adjustable release time
Low noise and distortion
Power-down feature
20 kHz bandwidth (1 dB)

APPLICATIONS
Microphone preamplifiers/processors
Computer sound cards
Public address/paging systems
Communication headsets
Telephone conferencing
Guitar sustain effects generators
Computerized voice recognition
Surveillance systems
Karaoke and DJ mixers

The SSM2166 is an ideal companion product for audio codecs

used in computer systems. The SSM2166 is available in a 14lead SOIC package and is guaranteed for operation over the
extended industrial temperature range of 40C to +85C.
10
COMP RATIO = 10:1

OUTPUT (dBu)

10

GENERAL DESCRIPTION
The SSM2166 integrates a complete and flexible solution for
conditioning microphone inputs in computer audio systems. It
is also excellent for improving vocal clarity in communications
and public address systems. A low noise, voltage-controlled
amplifier (VCA) provides a gain that is dynamically adjusted by
a control loop to maintain a set compression characteristic. The
compression ratio is set by a single resistor and can be varied
from 1:1 to over 15:1 relative to a user-defined rotation point;
signals above the rotation point are limited to prevent overload

COMP RATIO = 2:1

20
COMP RATIO = 1:1
30
40

60
70

60

50

40
30
INPUT (dBu)

20

10

00357-002

50

Figure 1. Compression and Gating Characteristics with 10 dB of Fixed Gain (The

Gain Adjust Pin Can Be Used to Vary This Fixed Gain Amount)

FUNCTIONAL BLOCK DIAGRAM AND TYPICAL SPEECH APPLICATION

10F
+
BUF OUT

IN
AUDIO
+IN

0.1F

VCAIN

V+

VCAR

1k

BUFFER

GAIN
ADJUST

14

2.3k

1k

VCA

OUTPUT
13
9

R2
10k
+
1F

LEVEL
DETECTOR

11

POWER DOWN

GND

AVG CAP

17k
ROTATION
SET

10

+
22F

NOISE GATE
SET
500k

CONTROL

SSM2166
12

V+

10F (OPTIONAL)
+

COMP RATIO SET

25k

00357-001

R1
10k

Figure 2.
Rev. E

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 19962013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

SSM2166

Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1

Signal Path ......................................................................................8

Applications ....................................................................................... 1

Level Detector ................................................................................9

General Description ......................................................................... 1

Control Circuitry........................................................................ 10

Functional Block Diagram and Typical Speech Application ...... 1

Power-Down Feature ................................................................. 12

Revision History ............................................................................... 2

PCB Layout Considerations ...................................................... 12

Specifications..................................................................................... 3

Evaluation Board ............................................................................ 13

Absolute Maximum Ratings............................................................ 4

Evaluation Board Examples ...................................................... 14

Thermal Resistance ...................................................................... 4

Evaluation Board Setup Procedure .......................................... 15

ESD Caution .................................................................................. 4

Test Equipment Setup ................................................................ 15

Pin Configuration and Function Descriptions ............................. 5

Setup Summary .......................................................................... 16

Typical Performance Characteristics ............................................. 6

Outline Dimensions ....................................................................... 17

Theory of Operation ........................................................................ 8

Ordering Guide .......................................................................... 17

Applications Information ............................................................ 8

REVISION HISTORY
10/13Rev. D to Rev. E
Change to Compression Ratio Section ........................................ 10
Changes to Ordering Guide .......................................................... 17
7/08Rev. C to Rev. D
Changes to Figure 4 through Figure 9 ........................................... 6
Changes to Figure 11 and Figure 12 ............................................... 7
Changes to Figure 19 ...................................................................... 10
Changes to Figure 26 ...................................................................... 13
Added Top Branding Revision Reflecting Die Replacement
Table ................................................................................................. 17
5/08Rev. B to Rev. C
Updated Format .................................................................. Universal
Changes to Features Section and General Description
Section ................................................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Deleted TPC 3; Renumbered Sequentially .................................... 4
Changes to Table 4, Pin 8 Description Column ........................... 5
Changes to Figure 5, Figure 6, Figure 8, and Figure 9 ................. 6

Change to Figure 11 ..........................................................................7

Changes to Signal Path Section .......................................................9
Added Figure 19 ............................................................................. 10
Deleted Figure 14 and Figure 17 .................................................. 12
Deleted Other Versions Section ................................................... 13
Changes to Figure 26...................................................................... 13
Changes to Figure 27...................................................................... 14
Changes to Test Equipment Section ............................................ 15
Added Table 6 ................................................................................. 16
Added Table 7 ................................................................................. 16
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
3/03Rev. A to Rev. B
Deleted PDIP Package ....................................................... Universal
Change to General Description .......................................................1
Changes to Thermal Characteristics ...............................................2
Changes to Ordering Guide .............................................................2
Deleted 14-Lead PDIP, Outline Dimensions .............................. 15
Updated 14-Lead Narrow-Body SOIC, Outline Dimensions... 15

Rev. E | Page 2 of 20

Data Sheet

SSM2166

SPECIFICATIONS
V+ = 5 V, f = 1 kHz, RL = 100 k, RGATE = 600 k, RROT PT = 3 k, RCOMP = 0 , R1 = 0 , R2 = , TA = 25C, unless otherwise noted;
VIN = 300 mV rms.
Table 1.
Parameter
AUDIO SIGNAL PATH
Voltage Noise Density
Noise
Total Harmonic Distortion and
Noise
Input Impedance
Output Impedance
Load Drive

Symbol

Conditions

en

15:1 Compression
20 kHz bandwidth, VIN = GND
Second and third harmonics, VIN = 20 dBu,
22 kHz low-pass filter

THD + N

1
2

Max

Unit

0.5

nV/Hz
dBu 1
%

k
nF

180
75
Resistive
Capacitive

1% THD
1% THD

1
1

V rms
V rms

1% THD
1% THD
1:1 compression, VCA gain = 60 dB

1
1.4
30

V rms
V rms
MHz

60
60 to +19
1:1
15:1

dB
dB

mV

See Figure 19 for RCOMP/RROT PT, rotation

point = 100 mV rms
15:1 compression, rotation point = 10 dBu,
R2 = 1.5 k

Control Feedthrough

Typ
17
109
0.25

ZIN
ZOUT

Buffer
Input Voltage Range
Output Voltage Range
VCA
Input Voltage Range
Output Voltage Range
Gain Bandwidth Product
CONTROL SECTION
VCA Dynamic Gain Range
VCA Fixed Gain Range
Compression Ratio, Minimum
Compression Ratio, Maximum

POWER SUPPLY
Supply Voltage Range
Supply Current
Quiescent Output Voltage Level
Power Supply Rejection Ratio
POWER DOWN
Supply Current

Min

V+
ISY

4.5
7.5
2.2
50

PSRR
Pin 12 = V+ 2

0 dBu = 0.775 V rms.

Normal operation for Pin 12 is 0 V.

Rev. E | Page 3 of 20

10

5.5
10

V
mA
V
dB

100

SSM2166

Data Sheet

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

Table 2.
Parameter
Supply Voltage
Audio Input Voltage
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ)
Lead Temperature (Soldering, 60 sec)

Rating
10 V
Supply voltage
40C to +85C
65C to +150C
150C
300C

Table 3.
Package Type
14-Lead SOIC

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. E | Page 4 of 20

JA
120

JC
36

Unit
C/W

Data Sheet

SSM2166

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

14 V+

GND 1
GAIN ADJUST

13 OUTPUT

VCAIN 3

SSM2166

12 POWER DOWN

TOP VIEW
11 ROTATION SET
(Not to Scale)
10 COMP RATIO SET
BUF OUT 5
IN 6

NOISE GATE SET

AUDIO +IN 7

AVG CAP

00357-003

VCAR 4

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
1
2

Mnemonic
GND
GAIN ADJUST

3
4

VCAIN
VCAR

5
6

BUF OUT
IN

7
8

AUDIO +IN
AVG CAP

NOISE GATE SET

10

COMP RATIO SET

11

ROTATION SET

12

POWER DOWN

13
14

OUTPUT
V+

Description
Ground.
VCA Gain Adjust Pin. A resistor from this pin to ground sets the fixed gain of the VCA. To check the setting of
this pin, make sure the compression ratio set pin (Pin 10) is grounded for no compression. The gain can be
varied from 0 dB to 20 dB. For 20 dB, leave the pin open. For 0 dB of fixed gain, a typical resistor value is
approximately 1 k. For 10 dB of fixed gain, the resistor value is approximately 2 k to 3 k. For resistor values
<1 k, the VCA can attenuate or mute (see Figure 6).
VCA Input Pin. A typical connection is a 10 F capacitor from the buffer output pin (Pin 5) to this pin.
Inverting Input to the VCA. This input can be used as a nonground reference for the audio input signal (see the
Applications Information section).
Input Buffer Amplifier Output Pin. This pin must not be loaded by capacitance to ground.
Inverting Input to the Buffer. A 10 k feedback resistor, R1, from the buffer output (Pin 5) to this input pin and
a resistor, R2, from this pin through a 1 F capacitor to ground give gains of 6 dB to 20 dB for R2 = 10 k to 1.1 k.
Input Audio Signal. The input signal should be ac-coupled (0.1 F typical) into this pin.
Detector Averaging Capacitor. A capacitor, 1 F to 22 F, to ground from this pin is the averaging capacitor
for the detector circuit.
Noise Gate Threshold Set Point. A resistor to V+ sets the level below which input signals are downward
expanded. For a 0.7 mV threshold, the resistor value is approximately 380 k. Increasing the resistor value
reduces the threshold (see Figure 5).
Compression Ratio Set Pin. A resistor to ground from this pin sets the compression ratio, as shown in Figure 2.
Figure 19 gives resistor values for various rotation points.
Rotation Point Set Pin. This pin is set by adding a resistor to the positive supply. This resistor together with
the gain adjust pin determines the onset of limiting. A typical value for this resistor is 17 k for a 100 mV
rotation point. Increasing the resistor value reduces the level at which limiting occurs (see Figure 9).
Power-Down Pin. Connect this pin to ground for normal operation. Connect this pin to the positive supply
for power-down mode.
Output Signal.
Positive Supply, 5 V Nominal.

Rev. E | Page 5 of 20

SSM2166

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0

5
COMP RATIO = 15:1

20
1

THD + N (%)

COMP RATIO = 1:1

40
TA = 25C
V+ = 5V
VIN = 300mV rms @ 1kHz
RL = 100k
NOISE GATE SETTING 550V rms
ROTATION SET 300mV rms
GAIN ADJUST = 1.25k

60
70
80
80

70

60

50

40
30
INPUT (dBu)

20

10

RL = 100k

0.1

0.05
0.01

00357-004

50

RL = 10k

Figure 4. Output vs. Input Characteristics

10

TA = 25C
V+ = 5V
RL = 100k
COMPRESSION RATIO = 2:1
ROTATION SET 700mV rms
GAIN ADJUST = 1.56k

TA = 25C
V+ = 5V
VIN = 77.5mV rms @ 1kHz
COMPRESSION RATIO = 1:1
NOISE GATE SETTING 550V rms
ROTATION SET 1V rms
GAIN ADJUST = 156k
MEASUREMENT FILTER BW: 20Hz TO 20kHz

THD + N (%)

0.1

0.1
0

50 100 150 200 250 300 350 400 450 500 550 600 650
RGATE (k)

0.01
10

00357-005

NOISE GATE (mV rms)

Figure 7. THD + N (%) vs. Input (V rms)

100

10

0.1
INPUT VOLTAGE (V rms)

Figure 5. Noise Gate vs. RGATE (Pin 9 to V+)

100

1k
FREQUENCY (Hz)

10k

30k

00357-008

OUTPUT (dBu)

COMP RATIO = 2:1

30

TA = 25C
V+ = 5V
COMPRESSION RATIO = 1:1
NOISE GATE SETTING 550V rms
ROTATION SET 1V rms
GAIN ADJUST = 1.25k
VIN FREQUENCY = 1kHz

00357-007

COMP RATIO = 10:1

10 COMP RATIO = 5:1

Figure 8. THD + N (%) vs. Frequency (Hz)

20

18

12
10
TA = 25C
V+ = 5V
VIN = 77.5mV rms @ 1kHz
RL = 100k
NOISE GATE SETTING 550V rms
ROTATION SET 1V rms
COMPRESSION RATIO = 1:1

8
6
4
2
0
0

8 10 12 14 16 18 20 22 24 26 28 30
GAIN ADJUST RESISTOR (k)

0.1

0.01

00357-006

VCA GAIN (dB)

14

Figure 6. VCA Gain vs. RGAIN (Pin 2 to GND)

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90
RROT PT RESISTOR (k)

Figure 9. Rotation Point vs. RROT PT (Pin 11 to V+)

Rev. E | Page 6 of 20

00357-009

ROTATION POINT (V rms)

16

Data Sheet

SSM2166

5V
100

1s

20mV

100

90

TA = 25C
CAVG = 2.2F

0dB
=
GAIN
SYSTEM
RL = 10k
COMPRESSION RATIO = 1:1

10

10

0%

00357-010

0%

TA = 25C
COMPRESSION RATIO = 15:1

NOISE BW = 20kHz

10s

00357-013

90

Figure 13. Small Signal Transient Response

Figure 10. Wideband Peak-to-Peak Output Noise

80

200mV

G = 60dB
60

100

90

G = 40dB

G = 20dB
20

10

ROTATION SET 1V rms

RCOMP = 30k
NOISE GATE SETTING 550V rms
VIN = 1mV rms

20

40
1k

0%

10k
100k
FREQUENCY (Hz)

1M

Figure 11. VCA Gain Bandwidth Curves vs. Frequency

RCOMP = 0
RGAIN = 1.24k
RGATE = 500k
RROT PT = 1.74k

V+ = 5V 1V p-p

50

V+ = 5V 0.5V p-p

60
70

80
20

100

1k
FREQUENCY (Hz)

10k

30k

00357-012

PSRR (dB)

30
40

Figure 12. PSRR vs. Frequency

Rev. E | Page 7 of 20

10s

Figure 14. Large Signal Transient Response

10

20

TA = 25C
CAVG = 2.2F
SYSTEM
GAIN
= 0dB

RL = 10k
COMPRESSION RATIO = 1:1

00357-014

00357-011

VGA GAIN (dB)

40

SSM2166

Data Sheet

THEORY OF OPERATION
Figure 15 illustrates a typical transfer characteristic for the
SSM2166 where the output level in decibels is plotted as a
function of the input level in decibels. The dotted line indicates
the transfer characteristic for a unity-gain amplifier. For input
signals in the range of VDE (downward expansion) to VRP (rotation
point), an r dB change in the input level causes a 1 dB change in
the output level. Here, r is defined as the compression ratio. The
compression ratio can be varied from 1:1 (no compression) to
over 15:1 via a single resistor, RCOMP. Input signals above VRP
are compressed with a fixed compression ratio of approximately
15:1. This region of operation is the limiting region. Varying the
compression ratio has no effect on the limiting region. The breakpoint between the compression region and the limiting region is
referred to as the limiting threshold or the rotation point and is
user specified in the SSM2166. The term rotation point derives
from the observation that the straight line in the compression
region rotates about this point on the input/output characteristic as
the compression ratio is changed.
The gain of the system with an input signal level of VRP is fixed
by RGAIN, regardless of the compression ratio, and is the nominal
gain of the system. The nominal gain of the system can be
increased by the user via the on-board VCA by up to 20 dB.
Additionally, the input buffer of the SSM2166 can be configured
to provide fixed gains of 0 dB to 20 dB with R1 and R2.
Input signals below VDE are downward expanded; that is, a
1 dB change in the input signal level causes approximately a
3 dB change in the output level. As a result, the gain of the
system is small for very small input signal levels, even though it
may be quite large for small input signals above VDE. The downward expansion threshold, VDE, is set externally by the user via
RGATE at Pin 9 (NOISE GATE SET). The SSM2166 provides an
active high, CMOS-compatible digital input whereby a powerdown feature reduces the device supply current to less than 100 A.

DOWNWARD
EXPANSION
THRESHOLD
(NOISE GATE)

LIMITING
REGION

COMPRESSION
REGION
1

VCA GAIN

DOWNWARD
EXPANSION
REGION
1
1

VDE

VRP
INPUT (dB)

00357-015

OUTPUT (dB)

LIMITING
THRESHOLD
(ROTATION POINT)

APPLICATIONS INFORMATION
The SSM2166 is a complete microphone signal conditioning
system on a single integrated circuit. Designed primarily for voiceband applications, this integrated circuit provides amplification,
rms detection, limiting, variable compression, and downward
expansion. An integral voltage-controlled amplifier (VCA)
provides up to 60 dB of gain in the signal path with approximately
30 kHz bandwidth. Additional gain is provided by an input
buffer, op amp circuit that can be set anywhere from 0 dB to 20 dB
for a total signal path gain of up to 80 dB. The device operates
on a single 5 V supply, accepts input signals up to 1 V rms, and
produces output signal levels >1 V rms (3 V p-p) into loads >5 k.
The internal rms detector has a time constant set by an external
capacitor.
The SSM2166 contains an input buffer and automatic gain
control (AGC) circuit for audio-band and voice-band signals.
Circuit operation is optimized by providing a user-adjustable
time constant and compression ratio. A downward expansion
(noise gating) feature eliminates circuit noise in the absence of
an input signal. The SSM2166 allows the user to set the downward
expansion threshold, the limiting threshold (rotation point), the
input buffer fixed gain, and the internal VCA nominal gain at
the rotation point. The SSM2166 also features a power-down
mode and muting capability.

SIGNAL PATH
Figure 16 illustrates the block diagram of the SSM2166. The
audio input signal is processed by the input buffer and then
by the VCA. The input buffer presents an input impedance of
approximately 180 k to the source. A dc voltage of approximately
1.5 V is present at AUDIO +IN (Pin 7), requiring the use of a
blocking capacitor (C1) for ground referenced sources. A 0.1 F
capacitor is a good choice for most audio applications. The input
buffer is a unity-gain stable amplifier that can drive the low
impedance input of the VCA.
The VCA is a low distortion, variable-gain amplifier (VGA)
whose gain is set by the side-chain control circuitry. The input
to the VCA is a virtual ground in series with approximately 1 k.
An external blocking capacitor (C6) must be used between the
buffer output and the VCA input. The 1 k impedance between
amplifiers determines the value of this capacitor, which is typically
between 1 F and 10 F. An aluminum electrolytic capacitor is
an economical choice. The VCA amplifies the input signal current
flowing through C6 and converts this current to a voltage at the
OUTPUT pin (Pin 13). The net gain from input to output can
be as high as 60 dB (without additional buffer gain), depending
on the gain set by the control circuitry.

Figure 15. General Input/Output Characteristics

Rev. E | Page 8 of 20

Data Sheet

SSM2166
LEVEL DETECTOR

The gain of the VCA at the rotation point is set by the value of a
resistor, RGAIN, connected between Pin 2 and GND. The relationship
between the VCA gain and RGAIN is shown in Figure 6. The AGC
range can be as high as 60 dB. The VCAIN pin (Pin 3) is the noninverting input terminal to the VCA. The inverting input of the
VCA is available at the VCAR pin (Pin 4) and exhibits an input
impedance of 1 k, as well. As a result, this pin can be used for
differential inputs or for the elimination of grounding problems
by connecting a capacitor whose value equals that used in series
with the VCAIN pin to ground (see Figure 26 for more details).

The SSM2166 incorporates a full-wave rectifier and true rms

level detector circuit whose averaging time constant is set by
an external capacitor connected to the AVG CAP pin (Pin 8).
For optimal low frequency operation of the level detector
down to 10 Hz, the value of the capacitor should be 2.2 F.
Some experimentation with larger values for the AVG CAP
may be necessary to reduce the effects of excessive low frequency
ambient background noise. The value of the averaging capacitor
affects sound quality: too small a value for this capacitor may
cause a pumping effect for some signals, while too large a value
may result in slow response times to signal dynamics. Electrolytic
capacitors are recommended for lowest cost and should be in
the range of 2 F to 47 F. Capacitor values from 18 F to 22 F
have been found to be more appropriate in voice-band applications
where capacitors on the low end of the range seem more
appropriate for music program material.

The output impedance of the SSM2166 is typically less than 75 ,

and the external load on Pin 13 should be >5 k. The nominal
output dc voltage of the device is approximately 2.2 V. Use a
blocking capacitor for grounded loads.
The bandwidth of the SSM2166 is quite wide at all gain settings.
The upper 3 dB point is approximately 30 kHz at gains as high as
60 dB (using the input buffer for additional gain, circuit bandwidth
is unaffected). The gain bandwidth (GBW) plots are shown in
Figure 11. The lower 3 dB cutoff frequency of the SSM2166 is
set by the input impedance of the VCA (1 k) and C6. While the
noise of the input buffer is fixed, the input referred noise of the
VCA is a function of gain. The VCA input noise is designed to
be a minimum when the gain is at a maximum, thereby optimizing
the usable dynamic range of the part. A plot of wideband peakto-peak output noise is shown in Figure 10.

The rms detector filter time constant is approximately given by

10 CAVG milliseconds, where CAVG is in F. This time constant
controls both the steady-state averaging in the rms detector as
well as the release time for compression; that is, the time it takes
for the system gain to react when a large input is followed by
a small signal. The attack time, the time it takes for the gain to
be reduced when a small signal is followed by a large signal, is
controlled partly by the AVG CAP value but is mainly controlled by
internal circuitry that speeds up the attack for large level changes.
This limits overload time to less than 1 ms in most cases.

C6
10F

BUF OUT
14

BUFFER
IN

VCAIN

1k

VCAR
1k

VCA

AUDIO
+IN

13

OUTPUT

VOUT

C1
0.1F

RGAIN

SSM2166

RGATE

+
1F
RMS
LEVEL
DETECTOR

CONTROL
CIRCUIT

11
12
8

NOISE GATE SET

ROTATION SET

RROT PT

POWER DOWN

10

AVG CAP

GND

V+

GAIN ADJUST

CAVG
2.2F

COMP
RATIO SET
RCOMP

Figure 16. Functional Block Diagram and Typical Application

Rev. E | Page 9 of 20

00357-016

R2
10k

V+
R1
10k

C7
10F (OPTIONAL)

SSM2166

Data Sheet

The performance of the rms level detector is illustrated for a

CAVG of 2.2 F in Figure 17 and for a CAVG of 22 F in Figure 18.
In each of these images, the input signal to the SSM2166 (not
shown) is a series of tone bursts in six successive 10 dB steps.
The tone bursts range from 66 dBV (0.5 mV rms) to 6 dBV
(0.5 V rms). As shown in Figure 17 and Figure 18, the attack
time of the rms level detector is dependent only on CAVG, but the
release times are linear ramps whose decay times are dependent
on both CAVG and the input signal step size. The rate of release is
approximately 240 dB/s for a CAVG of 2.2 F and 12 dB/s for a
CAVG of 22 F.
100mV
100

6dBV

Compression Ratio
Changing the scaling of the control signal fed to the VCA causes a
change in the circuit compression ratio, r. This effect is shown
in Figure 20. The compression ratio can be set by connecting a
resistor between the COMP RATIO SET pin (Pin 10) and GND.
Lowering RCOMP gives smaller compression ratios as shown in
Figure 19, with values of approximately 0.17 k or less resulting
in a compression ratio of 1:1. AGC performance is achieved
with compression ratios between 2:1 and 15:1 and is dependent
on the application. A 100 k potentiometer can be used to
allow this parameter to be adjusted. On the evaluation board
(see Figure 26), an optional resistor can be used to set the
compression equal to 1:1 when the wiper of the potentiometer
is at its full counterclockwise (CCW) position.

90

1:1
0.1
0.1
0.1

ROTATION POINT
100mV rms
300mV rms
1V rms

66dBV

2:1
8.7
8.7
8.7

5:1
19.4
19.4
19.4

10:1
45
45
45

15:1
395
N/A
N/A

TYPICAL RCOMP VALUES IN k.

10

85dBV

Figure 19. Compression Ratio vs. RCOMP (Pin 10 to GND)

00357-017

0%

100ms

15:1

Figure 17. RMS Level Detector Performance with CAVG = 2.2 F

100

5:1

1s

VCA GAIN

2:1

6dBV

1:1

OUTPUT (dB)

100mV

00357-031

COMPRESSION
RATIO

90

66dBV
1
10

85dBV

VDE

INPUT (dB)

VRP

00357-019

00357-018

0%

Figure 20. Effect of Varying the Compression Ratio

Figure 18. RMS Level Detector Performance with CAVG = 22 F

Rotation Point

CONTROL CIRCUITRY
The output of the rms level detector is a signal proportional to
the log of the true rms value of the buffer output with an added
dc offset. The control circuitry subtracts a dc voltage from this
signal, scales it, and sends the result to the VCA to control the
gain. The gain control of the VCA is logarithmica linear change
in the control signal causes a decibel change in gain. It is this
control law that allows linear processing of the log rms signal to
provide the flat compression characteristic on the input/output
characteristic shown in Figure 15.

An internal dc reference voltage in the control circuitry, used to

set the rotation point, is user specified, as illustrated in Figure 9.
The effect on rotation point is shown in Figure 21. By varying a
resistor, RROT PT, connected between the positive supply and the
ROTATION SET pin (Pin 11), the rotation point may be varied
by approximately 20 mV rms to 1 V rms. From Figure 21, the
rotation point is inversely proportional to RROT PT. For example, a
1 k resistor would typically set the rotation point at 1 V rms,
whereas a 55 k resistor would typically set the rotation point
at approximately 30 mV rms.

Rev. E | Page 10 of 20

Data Sheet

SSM2166

Because limiting occurs for signals larger than the rotation point
(VIN > VRP), the rotation point effectively sets the maximum output
signal level. It is recommended that the rotation point be set at
the upper extreme of the range of typical input signals so that
the compression region covers the entire desired input signal
range. Occasional larger signal transients are then attenuated by
the action of the limiter.

The gain of the VCA can be reduced below 0 dB by making

RGAIN smaller than 1 k. Switching Pin 2 through 330 or less
to GND mutes the output. Either a switch connected to ground or a
transistor can be used, as shown in Figure 23. To avoid audible
clicks when using the mute feature, a capacitor (C5) can be
connected from Pin 2 to GND. The value of the capacitor is
arbitrary and should be determined empirically, but a 0.01 F
capacitor is a good starting value.
SSM2166

VCA
GAIN
r:1

OUTPUT (dB)

VCA
GAIN

GAIN ADJUST
330
C5

NOTES
1. ADDITIONAL CIRCUIT DETAILS OMITTED
FOR CLARITY.

1
1

Figure 23. Details of Mute Option

VRP1 VRP2
INPUT (dB)

VRP3

Downward Expansion Threshold

00357-020

VDE

MUTE
(CLOSED SWITCH)
00357-022

VCA
GAIN

RGAIN

Figure 21. Effect of Varying the Rotation Point

VCA Gain Setting and Muting

The maximum gain of the SSM2166 is set by the GAIN ADJUST
pin (Pin 2) via RGAIN. This resistor, with a range of 1 k to
20 k, causes the nominal VCA gain to vary from 0 dB to
approximately 20 dB, respectively. Setting the VCA gain to its
maximum can also be achieved by leaving the GAIN ADJUST
pin in an open condition (no connect). Figure 22 illustrates the
effect on the transfer characteristic by varying this parameter.
For low level signal sources, the VCA should be set to maximum
gain using a 20 k resistor.

OUTPUT (dB)

r:1

The downward expansion threshold, or noise gate, is determined via a second reference voltage internal to the control
circuitry. This second reference can be varied in the SSM2166
using a resistor, RGATE, connected between the positive supply
and the NOISE GATE SET pin (Pin 9). The effect of varying this
threshold is shown in Figure 24. The downward expansion
threshold can be set between 300 V rms and 20 mV rms by
varying the resistance value between Pin 9 and the supply
voltage. Like the ROTATION SET pin, the downward expansion
threshold is inversely proportional to the value of this resistance:
setting this resistance to 1 M sets the threshold at approximately
250 V rms, whereas a 10 k resistance sets the threshold at
approximately 20 mV rms. This relationship is illustrated in
Figure 5. A potentiometer network is provided on the evaluation
board for this adjustment. In general, the downward expansion
threshold should be set at the lower extreme of the desired range of
the input signals so that signals below this level are attenuated.

VCA GAIN
r:1

VRP

Figure 22. Effect of Varying the VCA Gain Setting

1

VDE2
VDE3
VDE1

INPUT (dB)

VRP

00357-023

INPUT (dB)

00357-021

VDE

VCA GAIN

OUTPUT (dB)

Figure 24. Effect of Varying the Downward Expansion (Noise Gate) Threshold

Rev. E | Page 11 of 20

SSM2166

Data Sheet

The supply current of the SSM2166 can be reduced to less than

100 A by applying an active high, 5 V CMOS-compatible input
to the POWER DOWN pin (Pin 12). In this state, the input and
output circuitry of the SSM2166 assumes a high impedance
state; as such, the potentials at the input pin and the output pin are
determined by the external circuitry connected to the SSM2166.
The SSM2166 takes approximately 200 ms to settle from a powerdown to power-on command. For power-on to power-down,
the SSM2166 requires more time, typically less than 1 second.
Cycling the power supply to the SSM2166 can result in quicker
settling times: the off-to-on settling time of the SSM2166 is less
than 200 ms, while the on-to-off settling time is less than 1 ms.
In either implementation, transients may appear at the output of
the device. To avoid these output transients, use mute control of
the VCA gain as previously mentioned.

PCB LAYOUT CONSIDERATIONS

Because the SSM2166 is capable of wide bandwidth operation
and can be configured for as much as 80 dB of gain, special care
must be exercised in the layout of the PCB that contains the IC
and its associated components. The following recommendations
should be considered and/or followed:

In some high system gain applications, the shielding of input

wires to minimize possible feedback from the output of the
SSM2166 back to the input circuit may be necessary.

A single-point (star) ground implementation is recommended in addition to maintaining short lead lengths and
PCB runs. The evaluation board layout shown in Figure 27,
Figure 28, and Figure 29 demonstrates the single-point
grounding scheme. In applications where an analog ground
and a digital ground are available, the SSM2166 and its
surrounding circuitry should be connected to the analog
ground of the system. Because of these recommendations,
wire-wrap board connections and grounding
implementations should be avoided.

The internal buffer of the SSM2166 was designed to drive only

the input of the internal VCA and its own feedback network.
Stray capacitive loading to ground from the BUF OUT pin in
excess of 5 pF to 10 pF can cause excessive phase shift and
can lead to circuit instability.

When using high impedance sources (5 k), system gains

in excess of 60 dB are not recommended. This configuration
is rarely appropriate because virtually all high impedance
inputs provide larger amplitude signals that do not require
as much amplification. When using high impedance sources,
however, it can be advantageous to shunt the source with a
capacitor to ground at the input pin of the IC (Pin 7) to
lower the source impedance at high frequencies, as shown
in Figure 25. A capacitor with a value of 1000 pF is a good
starting value and sets a low-pass corner at 31 kHz for 5 k
sources. In applications where the source ground is not as
clean as would be desirable, a capacitor (illustrated as C7
on the evaluation board) from the VCAR input to the source
ground may prove beneficial. This capacitor is used in
addition to the grounded capacitor (illustrated as C2 on the
evaluation board) used in the feedback around the buffer,
assuming that the buffer is configured for gain.
C1
0.1F
AUDIO +IN
(RS > 5k)

AUDIO +IN
7

CX
1000pF

SSM2166

NOTES
1. ADDITIONAL CIRCUIT DETAILS OMITTED
FOR CLARITY.

00357-024

POWER-DOWN FEATURE

Figure 25. Circuit Configuration for Use with High Impedance Signal Sources

The value of C7 should be the same as C6, which is the capacitor

value used between BUF OUT and VCAIN. This connection
makes the source ground noise appear as a common-mode signal
to the VCA, allowing the common-mode noise to be rejected by
the VCA differential input circuitry. C7 can also be useful in
reducing ground loop problems and in reducing noise coupling
from the power supply by balancing the impedances connected
to the inputs of the internal VCA.

Rev. E | Page 12 of 20

Data Sheet

SSM2166

EVALUATION BOARD
330 resistance to ground. This is provided on the evaluation
board via R11 and S1. Capacitor C5, connected between Pin 2
and ground and provided on the evaluation board, can be used
to avoid audible clicks when using the mute function.

A schematic diagram of the SSM2166 evaluation board is

illustrated in Figure 26. As a design aid, the layouts for the
topside silkscreen and the topside and backside metallization
layers are shown in Figure 27, Figure 28, and Figure 29. Although
not shown to scale, the finished dimension of the evaluation
board is 3.5 inches by 3.5 inches and comes complete with pin
sockets and a sample of the SSM2166.

To configure the SSM2166 input buffer for gain, provisions for

R1, R2, and C2 have been included. To configure the input buffer
for unity-gain operation, R1 and R2 are removed and a direct
connection is made between the IN pin (Pin 6) and the BUF OUT
pin (Pin 5).

Signal sources are connected to the SSM2166 through a 1/8-inch

phone jack where a 0.1 F capacitor couples the input signal
to the AUDIO +IN pin (Pin 7). As shown in Figure 26 and in
microphone applications, the phone jack shield can be optionally
connected to the ground plane of the board (Jumper J1 inserted
into the board socket for Pin 1 and Pin 2) or to the VCAR input
at Pin 4 (J1 inserted into the board socket for Pin 1 and Pin 3).
If the signal source is a waveform or function generator, the
phone jack shield should be connected to ground.

The output stage of the SSM2166 is capable of driving >1 V rms

(3 V p-p) into >5 k loads and is externally available through
an RCA phono jack provided on the board. If the output of the
SSM2166 is required to drive a lower load resistance or an audio
cable, the on-board OP113 can be used. To use the OP113 buffer,
insert Jumper J4 into the board socket for Pin 4 and Pin 5 and
insert Jumper J5 into the board socket for Pin 6 and Pin 7. If the
output buffer is not required, remove Jumper J5 and insert Jumper
J4 into board socket Pin 5 and Pin 7.

For ease in making adjustments for all configuration parameters,

single-turn potentiometers are used throughout. Optional Jumper
J2 connects the COMP RATIO SET pin to ground and sets the
SSM2166 for no compression (that is, compression ratio = 1:1).
Optional Jumper J3 connects the POWER DOWN (Pin 12) input
to ground for normal operation. J3 can be replaced by an opendrain logic buffer for a digitally controlled shutdown function.
An output signal mute function can be implemented on the
SSM2166 by connecting the GAIN ADJUST pin (Pin 2) through a

There are no blocking capacitors either on the input or at

the output of the buffer. As a result, the output dc level of the
buffer matches the output dc level of the SSM2166, which is
approximately 2.3 V. A dc blocking capacitor can be inserted at
Pin 6 and Pin 7. An evaluation board and setup procedure
is available from an Analog Devices, Inc., sales representative.

+V
C3
0.1F

C6
10F
+

R4
500
3

BUF OUT VCAIN

R2
10k

C2
1F

MIC
PWR

J3

CCW

CW
5

R12
100k

R8
500

R7
1M

R3
50k

11

14

ROTATION
SET

V+

12

NOISE GATE POWER DOWN

SET

SSM2166

IN

GND 1

AUDIO +IN

VCAR

AVG CAP

GAIN ADJUST

COMP RATIO SET

OUTPUT

10

13

C1
0.1F
INPUT
JACK
1/8"
PHONE

1
3
2

+ C7
10F

+ C4
22F

R9
1k

GAIN
ADJ
CW

R11
330
R10
20k

C5
0.01F

MUTE
SWITCH

R6
100k
CW

COMP
RATIO
OP113
ADJ
6
7

Figure 26. Evaluation Board Schematic

Rev. E | Page 13 of 20

OUTPUT
JACK
RCA
PHONO

00357-025

R1
10k

NOISE GATE ADJ

ROTATION
PT ADJ

SSM2166

Data Sheet

IC2

00357-026

00357-028

IC1

Figure 27. Evaluation Board Topside Silkscreen (Not to Scale)

Figure 29. Evaluation Board Backside Metallization (Not to Scale)

EVALUATION BOARD EXAMPLES

To illustrate how easy it is to program the SSM2166, a practical
example is provided. The SSM2166 was used to interface an
electret-type microphone to a postamplifier. The evaluation
board or the circuit configuration shown in Figure 26 can be
used. The signal from the microphone was measured under
actual conditions to vary from 1 mV to 15 mV. The postamplifier
requires no more than 500 mV at its input. The required gain
from the SSM2166 is, therefore

00357-027

GTOTAL = 20 log(500/15) = 30 dB

Figure 28. Evaluation Board Topside Metallization (Not to Scale)

The input buffer gain is set to 20 dB, and the VCA gain is adjusted
to 10 dB. The limiting or rotation point is set at 500 mV output.
A 2:1 compression ratio and a noise gate threshold that operates
below 100 V is also used. These objectives are summarized in
Table 5. The transfer characteristic implemented is illustrated in
Figure 30.
Table 5. Objective Specifications
Parameter
Input Range
Output Range
Limiting Level
Compression
Buffer Gain
VCA Gain
Noise Gate

Rev. E | Page 14 of 20

Value
1 mV to 15 mV
To 500 mV
500 mV
2:1
20 dB
10 dB
100 V

Data Sheet

SSM2166

Note that the SSM2166 processes the output of the buffer, which
in the previous example is 20 dB or 10 times the input level. Use
the oscilloscope to verify that the buffer is not being driven into
clipping with excessive input signals. In the application, take the
minimum gain in the buffer consistent with the average source
level as well as the crest factor (ratio of peak to rms).

Step 3: Testing Setup

With the power on, adjust the generator for an input level of
15 mV, 1 kHz. The output meter should indicate approximately
100 mV; if not, check the setup.
Set the input level to 15 mV and observe the output on the
oscilloscope. Adjust R3, ROTATION PT ADJ, until the output
level just begins to drop, then reverse so that the output is 500 mV.
The limiting has been set to 500 mV.

500

OUTPUT (mV)

With the power off, preset the potentiometers per Table 6.

Step 4: Adjusting the Rotation Point

ROTATION POINT

COMPRESSION
REGION

Step 2: Initializing Potentiometers

LIMITING REGION
1
2

Step 5: Adjusting the VCA Gain

40

Set the input level to 15 mV. Adjust R10, GAIN ADJ, clockwise
(CW) for an output level of 500 mV. The VCA gain has been set
to 10 dB.

0.1

1.0

10

00357-029

GATE THRESHOLD

15

INPUT (mV)

Step 6: Adjusting the Compression Ratio

Figure 30. Transfer Characteristic

EVALUATION BOARD SETUP PROCEDURE

When building a breadboard, keep the leads to Pin 3, Pin 4, and
Pin 5 short. An evaluation board is available from an Analog
Devices sales representative. The R and C designations refer to
the demonstration board schematic of Figure 26 and the parts
list in Table 7.

TEST EQUIPMENT SETUP

The recommended equipment and configuration are shown in
Figure 31. A low noise audio generator with a smooth output
adjustment range of 50 V to 50 mV is a suitable signal source.
A 40 dB pad is useful to reduce the level of most generators by
100 to simulate the microphone levels. The input voltmeter
can be connected before the pad and need only go down to
10 mV. The output voltmeter should go up to 2 V. The oscilloscope
is used to verify that the output is sinusoidal and that no clipping
occurs in the buffer, and to set the limiting and noise gating
knees.
SSM2166
EVALUATION
BOARD

AC
VOLTMETER

OSCILLOSCOPE

AC
VOLTMETER

00357-030

SIGNAL
GENERATOR

Figure 31. Test Equipment Setup

Set the input signal for an output of 500 mV but not in limiting.
Note the value (around 15 mV). Next, reduce the input to 1/10
of the value noted (around 1.5 mV) for a change of 20 dB. Next,
adjust R6, COMP RATIO ADJ, CW until the output is 160 mV for
an output change of 10 dB. The compression, which is the
ratio of the output change to the input change, in decibels (dB),
has been set to 2:1.

Step 7: Setting the Noise Gate

With the input set at 100 V, observe the output on the oscilloscope
and adjust R7, NOISE GATE ADJ, CCW until the output drops
rapidly. Rock the control back and forth to find the knee. The
noise gate has been set to 100 V. The range of the noise gate is
from 0.3 mV to over 0.5 mV relative to the output of the buffer.
To fit this range to the application, it may be necessary to attenuate
the input or apportion the buffer gain and VCA gain differently.

Step 8: Listening
At this time, it may be desirable to connect an electret microphone to the SSM2166 and listen to the results. Be sure to include
the proper power for the internal FET of the microphone
(usually 2 V dc to 5 V dc through a 2.2 k resistor). Experiment
with the settings to hear how the results change. Varying the
averaging capacitor, C4, changes the attack and decay times,
which are best determined empirically. The compression ratio
keeps the output steady over a range of microphone to speaker
distances, and the noise gate keeps the background sounds
subdued.

Step 1: Configure the Buffer

Step 9: Recording Values

The SSM2166 has an input buffer that can be used when the
overall gain required exceeds 20 dB, the maximum user-selectable
gain of the VCA. In the example, the desired output is 500 mV
for an input of ~15 mV, requiring a total gain of 30 dB. Set the
buffer gain at 20 dB and adjust the VCA for 10 dB. In the socket
pins provided on the evaluation board, insert R1 = 100 k and
R2 = 11 k. The buffer gain is set to 20 dB (10).

With the power removed from the test fixture, measure and
record the values of all potentiometers, including any fixed
resistance in series with them. If the averaging capacitor, C4,
changes, also note its value.

Rev. E | Page 15 of 20

SSM2166

Data Sheet

SETUP SUMMARY
The transfer condition of Figure 2 has been implemented. For
inputs below the 100 V noise gate threshold, circuit and background noise is minimized. Above it, the output increases at a
rate of 1 dB for each 2 dB input increase until the 500 mV rotation
point is reached at an input of approximately 15 mV. For higher
inputs that drive the output beyond 500 mV, limiting occurs
and there is little further increase. The SSM2166 processes the
output of the buffer, which in the previous example is 20 dB, or

10 the input level. Use the oscilloscope to ensure that the

buffer is not being driven into clipping with the highest expected
input peaks. Always take the minimum gain in the buffer consistent with the average source level and crest factor (ratio of peak
to rms). The wide program range of the SSM2166 makes it
useful in many applications other than microphone signal
conditioning.

Table 6. Initial Potentiometer Settings

Function
Gain Adjust (VCA)
Rotation Point
Compression Point
Noise Gate

Potentiometer
R10
R3
R6
R7

Range
0 k to 20 k
0 k to 50 k
0 k to 100 k
0 k to 1 M

Initial Position
CCW
CCW
CCW
CW

Initial Resistance
0
0
0
1 M

Effect of Change
0 dB; CW to increase VCA gain
1 V; CW to reduce rotation point
1:1; CW to increase compression
300 V; CCW to increase threshold

Table 7. Demonstration Board Parts List

Component
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
C1
C2
C3
C4
C5
C6
C7
IC1
IC2
S1
J1
J2

Value
10 k resistor
10 k resistor
50 k potentiometer
500 resistor
0 resistor
100 k potentiometer
1 M potentiometer
500 resistor
1 k resistor
20 k potentiometer
330 resistor
100 k resistor
0.1 F capacitor
1 F capacitor
0.1 F capacitor
2.2 F to 22 F capacitor
0.01 F capacitor
10 F capacitor
10 F capacitor
SSM2166
OP113, IC
SPST, Switch
1/8-inch mini phone plug jumper
RCA female jumper

Description
Feedback
Input
Rotation point, adjust
Rotation point, fixed
Compression ratio, fixed
Compression ratio, adjust
Noise gate, adjust
Noise gate, fixed
Gain adjust, fixed
Gain adjust
Mute
Power-down, pull-up
Input dc block
Buffer low F, G = 1
+V bypass
Average capacitor
Mute click suppress
Coupling
VCA noise/dc balance
MIC preamp
Operational amplifier, output buffer
Mute
MIC input
Output jack

Rev. E | Page 16 of 20

Data Sheet

SSM2166

OUTLINE DIMENSIONS
8.75 (0.3445)
8.55 (0.3366)
8

14
1

1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10

0.51 (0.0201)
0.31 (0.0122)

6.20 (0.2441)
5.80 (0.2283)

0.50 (0.0197)
0.25 (0.0098)

1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE

45

8
0
0.25 (0.0098)
0.17 (0.0067)

1.27 (0.0500)
0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

060606-A

4.00 (0.1575)
3.80 (0.1496)

Figure 32. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model 1
SSM2166SZ
SSM2166SZ-REEL
SSM2166SZ-REEL7
1

Temperature Range
40C to +85C
40C to +85C
40C to +85C

Package Description
14-Lead SOIC_N
14-Lead SOIC_N
14-Lead SOIC_N

Package Option
R-14
R-14
R-14

Z = RoHS Compliant Part.

Top Branding Revision Reflecting Die Replacement

Version
Pb-Free (RoHS) Version

1
2

Original Die Revision

(Prior to Rev. C of Data Sheet)
Top Line 1: SSM
Top Line 2: 2166
Top Line 3: # XXXX 2

New Die Revision

(Rev. C to Current Revision of Data Sheet)
Top Line 1: SSM
Top Line 2: 2166A 1
Top Line 3: # XXXX2

Letter A designates new die revision; refer to revised external component values in Figure 5, Figure 6, Figure 9, and Figure 19.
# designates RoHS version.

Rev. E | Page 17 of 20

SSM2166

Data Sheet

NOTES

Rev. E | Page 18 of 20

Data Sheet

SSM2166

NOTES

Rev. E | Page 19 of 20

SSM2166

Data Sheet

NOTES

19962013 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D00357-0-10/13(E)

Rev. E | Page 20 of 20