Datasheet,Version 2.

0, December 4, 2009

ICE2QS03
Quasi-Resonant
Controller

PWM

Power Management & Supply

N e v e r

s t o p

t h i n k i n g .

ICE2QS03
Revision History:

December 4, 2009

Previous Version:

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Datasheet

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CoolMOS, CoolSET are trademarks of Infineon Technologies AG.

Edition December 4, 2009

Published by
Infineon Technologies AG
81726 Mnchen, Germany

Infineon Technologies AG 12/4/09.

All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (Beschaffenheitsgarantie). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
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ICE2QS03
Quasi-Resonant PWM Controller
Product Highlight
Active burst mode for low standby power
Digital frequency reduction for better overall system efficiency
Integrated power cell for IC self-power supply

Features

Description

ICE2QS03 is a quasi-resonant PWM controller

optimized for off-line switch power supply applications
such as LCD TV, CRT TV and notebook adapter. The
digital frequency reduction with decreasing load
enables a quasi-resonant operation till very low load.
As a result, the overall system efficiency is significantly
improved compared to other conventional solutions.
The active burst mode operation enables an ultra-low
power consumption at standby mode with small and
controllable output voltage ripple. Based on the
BiCMOS technology, the product has a wide operation
range (up to 26V) of IC power supply and lower power
consumption. The numerous protection functions give
a full protection of the power supply system in failure
situations. All of these make the ICE2QS03 an
outstanding controller for quasi-resonant flyback
converter in the market.

Quasiresonant operation till very low load

Active burst mode operation at light/no load for low
standby input power (< 100mW)
Digital frequency reduction with decreasing load
Power cell for VCC pre-charging with constant
current
Built-in digital soft-start
Foldback correction and cycle-by-cycle peak
current limitation
Auto restart mode for VCC Overvoltage protection
Auto restart mode for VCC Undervoltage protection
Auto restart mode for openloop/overload protection
Latch-off mode for adjustable output overvoltage
protection
Latch-off mode for Short-winding protection

Typical Application Circuit

Wp

Snubber

Cbus
85 ~ 265Vac

RVCC

Lf

DO

DVCC

CVCC

VO

Cf

Ws
CO

RZC2

RZC1
Wa

Dr1~Dr4
CZC
HV

VCC

ZC

CPS

Power
Cell

GND

Control Unit

Q1
Rb1

Zero Crossing Detection

Active Burst Mode

FB

Gate
Driver

GATE
Optocoupler

Current
Limitation

Protection Block
ICE2QS03

Version 2.0

Rovs1
Rc1

CS
RCS

Current Mode Control

Type
ICE2QS03

Rb2

Power Management
Digital Process Block

CFB

CDS

TL431

Cc1

Cc2
Rovs2

Package
PG-DIP-8-6
3

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Table of Contents

Page

1
1.1
1.2
1.3

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Package PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3
3.1
3.2
3.3
3.3.1
3.3.1.1
3.3.1.2
3.3.2
3.3.3
3.4
3.4.1
3.5
3.5.1
3.5.2
3.5.3
3.6

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
VCC Pre-Charging and Typical VCC Voltage During Start-up . . . . . . . . . . .7
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Digital Frequency Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Up/down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Zero crossing (ZC counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ringing suppression time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Switch Off Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Entering Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . .10
During Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Leaving Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4
4.1
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Digital Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Version 2.0

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Pin Configuration and Functionality

Pin Configuration and

Functionality

1.1

1.3

ZC (Zero Crossing)
At this pin, the voltage from the auxiliary winding after
a time delay circuit is applied. Internally, this pin is
connected to the zero-crossing detector for switch-on
determination. Additionally, the output overvoltage
detection is realized by comparing the voltage Vzc with
an internal preset threshold.

Pin Configuration with PG-DIP8-6

Pin

Symbol

Function

ZC

Zero Crossing

FB

Feedback

CS

Current Sense

HV

High Voltage Input

HV

High Voltage Input

GATE

Gate Drive Output

VCC

Controller Supply Voltage

GND

Controller Ground

1.2

FB (Feedback)
Normally, an external capacitor is connected to this pin
for a smooth voltage VFB. Internally, this pin is
connected to the PWM signal generator for switch-off
determination (together with the current sensing
signal), the digital signal processing for the frequency
reduction with decreasing load during normal
operation, and the Active Burst Mode controller for
entering Active Burst Mode operation determination
and burst ratio control during Active Burst Mode
operation. Additionally, the open-loop / over-load
protection is implemented by monitoring the voltage at
this pin.
CS (Current Sense)
This pin is connected to the shunt resistor for the
primary current sensing, externally, and the PWM
signal generator for switch-off determination (together
with the feedback voltage), internally. Moreover, shortwinding protection is realised by monitoring the voltage
Vcs during on-time of the main power switch.

Package PG-DIP-8-6

ZC

GND

FB

VCC

CS

GATE

HV

HV

Figure 1

Pin Functionality

GATE (Gate Drive Output)

This output signal drives the external main power
switch, which is a power MOSFET in most case.
HV (High Voltage)
The pin HV is connected to the bus voltage, externally,
and to the power cell, internally. The current through
this pin pre-charges the VCC capacitor with constant
current once the supply bus voltage is applied.
VCC (Power supply)
VCC pin is the positive supply of the IC. The operating
range is between VVCCoff and VVCCOVP.

Pin Configuration PG-DIP-8-6(top view)

GND (Ground)
This is the common ground of the controller.

Version 2.0

December 4, 2009

Figure 2

Version 2.0

2pF

25kO

RFB

VREF

D1

C3

C2

VFBBOff

VFBBOn

VFBEB

VFBZL

VFBZH

VFBR1

VFBOLP

VZCRS

VZCOVP

C10

C9

C8

C7

C6

C5

C4

Count=7

C1

Comparator

ZC counter

tBEB

&

Active
Burst Mode

Ringing
Suppression

G1

Active Burst Block

Regulation

tOLP_B

Delay
tZCOVP

tCOUNT

Up/down counter

clk

Zero Crossing

VVCCOVP

VPWM

OSC

f
en sB

PWM
Comparator

Soft-start

18V

Current Mode

10.5

Undervoltage Lockout

Power Management

GPWM

G3

G4
R

G8

C15

G2

G7

1
S

C14

Leading
Edge
Blanking
tLEB

TOnMax

1pF

VCSSW

10kO

Current Limiting

D2

Gate
Drive

Depl. CoolMOS

Gate Drive

R
latched
Protect

&
G9

Protection

R
Autorestart
Protect
S Q

TOffMax

Delay
tCSSW

OTP

Foldback
Correction

C13 VCSB

10us

Internal
Bias

PWM Control

PWM OP

&
G6

&
G5

C12

Voltage
Reference

Startup Cell

HV

CS

GND

GATE

FB

ZC

VZCC

VCC

Quasi-Resonant PWM Controller

ICE2QS03
Representative Block diagram

Representative Block diagram

Representative Block diagram

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Functional Description

Functional Description

then will reach a constant value depending on output

load.

3.1

VCC Pre-Charging and Typical

VCC Voltage During Start-up

3.2

At the time ton, the IC begins to operate with a soft-start.

By this soft-start the switching stresses for the switch,
diode and transformer are minimised. The soft-start
implemented in ICE2QS03 is a digital time-based
function. The preset soft-start time is 12ms with 4
steps. If not limited by other functions, the peak voltage
on CS pin will increase step by step from 0.32V to 1V
finally.

In ICE2QS03, a high voltage startup cell is integrated..

As shown in Figure 2, the start cell consists of a high
voltage device and a controller, whereby the high
voltage device is controlled by the controller. The
startup cell provides a pre-charging of the VCC
capacitor till VCC voltage reaches the VCC turned-on
threshold VVCCon and the IC begins to operate.
Once the mains input voltage is applied, a rectified
voltage shows across the capacitor Cbus. The high
voltage device provides a current to charge the VCC
capacitor Cvcc. Before the VCC voltage reaches a
certain value, the amplitude of the current through the
high voltage device is only determined by its channel
resistance and can be as high as several mA. After the
VCC voltage is high enough, the controller controls the
high voltage device so that a constant current around
1mA is provided to charge the VCC capacitor further,
until the VCC voltage exceeds the turned-on threshold
VVCCon. As shown as the time phase I in Figure 3, the
VCC voltage increase near linearly and the charging
speed is independent of the mains voltage level.

Vcs_sst
(V)
1.00
0.83
0.66
0.49
0.32

ton

Figure 4

VVCC
VVCCon

ii

3.3

iii

Figure 3

t2

VCC voltage at start up

The time taking for the VCC pre-charging can then be

approximately calculated as:
t

V
C
VCCon vcc
= -----------------------------------------1
I VCCch arg e2

[1]

where IVCCcharge2 is the charging current from the

startup cell which is 1.05mA, typically.
Exceeds the VCC voltage the turned-on threshold
VVCCon of at time t1, the startup cell is switched off, and
the IC begins to operate with a soft-start. Due to power
consumption of the IC and the fact that still no energy
from the auxiliary winding to charge the VCC capacitor
before the output voltage is built up, the VCC voltage
drops (Phase II). Once the output voltage is high
enough, the VCC capacitor receives then energy from
the auxiliary winding from the time point t2 on. The VCC

Version 2.0

12

Time(ms)

Maximum current sense voltage during

softstart

Normal Operation

The PWM controller during normal operation consists

of a digital signal processing circuit including an up/
down counter, a zero-crossing counter (ZC counter)
and a comparator, and an analog circuit including a
current measurement unit and a comparator. The
switch-on and -off time points are each determined by
the digital circuit and the analog circuit, respectively. As
input information for the switch-on determination, the
zero-crossing input signal and the value of the up/down
counter are needed, while the feedback signal VFB and
the current sensing signal VCS are necessary for the
switch-off determination. Details about the full
operation of the PWM controller in normal operation
are illustrated in the following paragraphs.

VVCCoff

t1

Soft-start

3.3.1
Digital Frequency Reduction
As mentioned above, the digital signal processing
circuit consists of an up/down counter, a ZC counter
and a comparator. These three parts are key to
implement digital frequency reduction with decreasing
load. In addition, a ringing suppression time controller
is implemented to avoid mistriggering by the high
frequency oscillation, when the output voltage is very
low under conditions such as soft start or output short
circuit . Functionality of these parts is described as in
the following.

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Functional Description
threshold voltages, VFBZL and VFBZH, are changed
internally depending on the line voltage levels.

3.3.1.1
Up/down counter
The up/down counter stores the number of the zero
crossing to be ignored before the main power switch is
switched on after demagnetisation of the transformer.
This value is fixed according to the feedback voltage,
VFB, which contains information about the output
power. Indeed, in a typical peak current mode control,
a high output power results in a high feedback voltage,
and a low output power leads to a low regulation
voltage. Hence, according to VFB, the value in the up/
down counter is changed to vary the power MOSFET
off-time according to the output power. In the following,
the variation of the up/down counter value according to
the feedback voltage is explained.
The feedback voltage VFB is internally compared with
three threshold voltages VRL, VRH and VRM, at each
clock period of 48ms. The up/down counter counts then
upward, keep unchanged or count downward, as
shown in Table 1.

up/down counter
action

Always lower than VFBZL

Count upwards till

7

Once higher than VFBZL, but

always lower than VFBZH

Stop counting, no
value changing

Once higher than VFBZH, but

always lower than VFBR1

Count downwards
till 1

Once higher than VFBR1

VFBR1
VFBZH
VFBZL

n+2

n+2

n+2

n+2

n+1

n-1

t
n+1

Up/down
counter
Case 1

3 1

Case 2

1 1

Case 3

4 1

Figure 5

Up/down counter operation

3.3.1.2
Zero crossing (ZC counter)
In the system, the voltage from the auxiliary winding is
applied to the zero-crossing pin through a RC network,
which provides a time delay to the voltage from the
auxiliary winding. Internally, this pin is connected to a
clamping network, a zero-crossing detector, an output
overvoltage detector and a ringing suppression time
controller.
During on-state of the power switch a negative voltage
applies to the ZC pin. Through the internal clamping
network, the voltage at the pin is clamped to certain
level.
The ZC counter has a minimum value of 0 and
maximum value of 7. After the internal MOSFET is
turned off, every time when the falling voltage ramp of
on ZC pin crosses the 100mV threshold, a zero
crossing is detected and ZC counter will increase by 1.
It is reset every time after the GATE output is changed
to high.
The voltage vZC is also used for the output overvoltage
protection. Once the voltage at this pin is higher than
the threshold VZCOVP during off-time of the main switch,
the IC is latched off after a fixed blanking time.
To achieve the switch-on at voltage valley, the voltage
from the auxiliary winding is fed to a time delay network
(the RC network consists of Dzc, Rzc1, Rzc2 and Czc as
shown in typical application circuit) before it is applied
to the zero-crossing detector through the ZC pin. The
needed time delay to the main oscillation signal t
should be approximately one fourth of the oscillation
period (by transformer primary inductor and drainsource capacitor) minus the propagation delay from

Set up/down
counter to 1

In the ICE2QS03, the number of zero crossing is

limited to 7. Therefore, the counter varies between 1
and 7, and any attempt beyond this range is ignored.
When VFB exceeds VFBR1 voltage, the up/down counter
is initialised to 1, in order to allow the system to react
rapidly to a sudden load increase. The up/down
counter value is also intialised to 1 at the start-up, to
ensure an efficient maximum load start up. Figure 5
shows some examples on how up/down counter is
changed according to the feedback voltage over time.
The use of two different thresholds VFBZL and VFBZH to
count upward or downward is to prevent frequency
jittereing when the feedback voltage is close to the
threshold point. However, for a stable operation, these
two thresholds must not be affected by the foldback
current limitation (see Section 3.4.1), which limits the
VCS voltage. Hence, to prevent such situation, the

Version 2.0

VFB

Operation of the up/down counter

vFB

T=48ms

Table 1

clock

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Functional Description
thedetected zero-crossing to the switch-on of the main
switch tdelay, theoretically:
T osc
t = ------------ t
delay
4

To avoid mistriggering caused by the voltage spike

across the shunt resistor at the turn on of the main
power switch, a leading edge blanking time, tLEB, is
applied to the output of the comparator. In other words,
once the gate drive is turned on, the minimum on time
of the gate drive is the leading edge blanking time.
In addition, there is a maximum on time, tOnMax,
limitation implemented in the IC. Once the gate drive
has been in high state longer than the maximum on
time, it will be turned off to prevent the switching
frequency from going too low because of long on time.

[2]

This time delay should be matched by adjusting the

time constant of the RC network which is calculated as:

td

= C

R zc1 R zc2
--------------------------------zc R
+R
zc1
zc2

[3]

3.4
3.3.2
Ringing suppression time
After MOSFET is turned off, there will be some
oscillation on VDS, which will also appear on the voltage
on ZC pin. To avoid that the MOSFET is turned on
mistriggerred by such oscillations, a ringing
suppression timer is implemented. The timer is
dependent on the voltage vZC. When the voltage vZC is
lower than the threshold VZCRS, a longer preset time
applies, while a shorter time is set when the voltage vZC
is higher than the threshold.

There is a cycle by cycle current limitation realized by

the current limit comparator to provide an overcurrent
detection. The source current of the MOSFET is
sensed via a sense resistor RCS. By means of RCS the
source current is transformed to a sense voltage VCS
which is fed into the pin CS. If the voltage VCS exceeds
an internal voltage limit, adjusted according to the
Mains voltage, the comparator immediately turns off
the gate drive.
To prevent the Current Limitation process from
distortions caused by leading edge spikes, a Leading
Edge Blanking time (tLEB) is integrated in the current
sensing path.
A further comparator is implemented to detect
dangerous current levels (VCSSW) which could occur if
one or more transformer windings are shorted or if the
secondary diode is shorted. To avoid an accidental
latch off, a spike blanking time of tCSSW is integrated in
the output path of the comparator .

3.3.2.1
Switch on determination
After the gate drive goes to low, it can not be changed
to high during ring suppression time.
After ring suppression time, the gate drive can be
turned on when the ZC counter value is higher or equal
to up/down counter value.
However, it is also possible that the oscillation between
primary inductor and drain-source capacitor damps
very fast and IC can not detect enough zero crossings
and ZC counter value will not be high enough to turn on
the gate drive. In this case, a maximum off time is
implemented. After gate drive has been remained off
for the period of TOffMax, the gate drive will be turned on
again regardless of the counter values and VZC. This
function can effectively prevent the switching
frequency from going lower than 20kHz, otherwise
which will cause audible noise, during start up.

3.4.1
Foldback Point Correction
When the main bus voltage increases, the switch on
time becomes shorter and therefore the operating
frequency is also increased. As a result, for a constant
primary current limit, the maximum possible output
power is increased, which the converter may have not
been designed to support.
To avoid such a situation, the internal foldback point
correction circuit varies the VCS voltage limit according
to the bus voltage. This means the VCS will be
decreased when the bus voltage increases. To keep a
constant maximum input power of the converter, the

3.3.3
Switch Off Determination
In the converter system, the primary current is sensed
by an external shunt resistor, which is connected
between low-side terminal of the main power switch
and the common ground. The sensed voltage across
the shunt resistor vCS is applied to an internal current
measurement unit, and its output voltage V1 is
compared with the regulation voltage VFB. Once the
voltage V1 exceeds the voltage VFB, the output flip-flop
is reset. As a result, the main power switch is switched
off. The relationship between the V1 and the vCS is
described by:
V

= 3.3 V

Version 2.0

CS

+ 0.7

Current Limitation

[4]

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Functional Description
about Active Burst Mode operation are explained in the
following paragraphs.

required maximum VCS versus various input bus

voltage can be calculated, which is shown in Figure 6.

3.5.1
Entering Active Burst Mode Operation
For determination of entering Active Burst Mode
operation, three conditions apply:
the feedback voltage is lower than the threshold of
VFBEB(1.25V). Accordingly, the peak current sense
voltage across the shunt resistor is 0.17;
the up/down counter is 7; and
a certain blanking time (tBEB).
Once all of these conditions are fulfilled, the Active
Burst Mode flip-flop is set and the controller enters
Active Burst Mode operation. This multi-condition
determination for entering Active Burst Mode operation
prevents mistriggering of entering Active Burst Mode
operation, so that the controller enters Active Burst
Mode operation only when the output power is really
low during the preset blanking time.

Vcs-max(V)

0.9

0.8

0.7

0.6
80

100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400
Vin(V)

Figure 6

Variation of the VCS limit voltage according

to the IZC current

According to the typical application circuit, when

MOSFET is turned on, a negative voltage proportional
to bus voltage will be coupled to auxiliary winding.
Inside ICE2QS03, an internal circuit will clamp the
voltage on ZC pin to nearly 0V. As a result, the current
flowing out from ZC pin can be calculated as
I

V BUS N a
= -----------------------ZC
R
N
ZC1 P

3.5.2
During Active Burst Mode Operation
After entering the Active Burst Mode the feedback
voltage rises as VOUT starts to decrease due to the
inactive PWM section. One comparator observes the
feedback signal if the voltage level VBH (3.6V) is
exceeded. In that case the internal circuit is again
activated by the internal bias to start with swtiching.
Turn-on of the power MOSFET is triggered by the
timer. The PWM generator for Active Burst Mode
operation composes of a timer with a fixed frequency of
52kHz, typically, and an analog comparator. Turn-off is
resulted by comparison of the voltage signal v1 with an
internal threshold, by which the voltage across the
shunt resistor VcsB is 0.34V, accordingly. A turn-off can
also be triggered by the maximal duty ratio controller
which sets the maximal duty ratio to 50%. In operation,
the output flip-flop will be reset by one of these signals
which come first.
If the output load is still low, the feedback signal
decreases as the PWM section is operating. When
feedback signal reaches the low threshold VBL(3.0V),
the internal bias is reset again and the PWM section is
disabled until next time regultaion siganl increases
beyond the VBH threshold. If working in Active Burst
Mode the feedback signal is changing like a saw tooth
between 3.0V and 3.6V shown in Figure 7.

[5]

When this current is higher than IZC_1, the amount of

current exceeding this threshold is used to generate an
offset to decrease the maximum limit on VCS. Since the
ideal curve shown in Figure 6 is a nonlinear one, a
digital block in ICE2QS03 is implemented to get a
better control of maximum output power. Additional
advantage to use digital circuit is the production
tolerance is smaller compared to analog solutions. The
typical maximum limit on VCS versus the ZC current is
shown in Figure 7.
1

Vcs-max(V)

0.9

0.8

0.7

3.5.3
Leaving Active Burst Mode Operation
The feedback voltage immediately increases if there is
a high load jump. This is observed by one comparator.
As the current limit is 34% during Active Burst Mode a
certain load is needed so that feedback voltage can
exceed VLB (4.5V). After leaving active busrt mode,
maximum current can now be provided to stabilize VO.
In addition, the up/down counter will be set to 1

0.6
300

500

700

900

1100

1300

1500

1700

1900

2100

Iz c(uA)

Figure 7

3.5

VCS-max versus IZC

Active Burst Mode Operation

At light load condition, the IC enters Active Burst Mode

operation to minimize the power consumption. Details

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Quasi-Resonant PWM Controller

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Functional Description
IC is reset and the main power switch is then kept off.
After the VCC voltage falls below the threshold VVCCoff,
the startup cell is activated. The VCC capacitor is then
charged up. Once the voltage exceeds the threshold
VVCCon, the IC begins to operate with a new soft-start.
In case of open control loop or output over load, the
feedback voltage will be pulled up . After a blanking
time of 24ms, the IC enters auto-restart mode. The
blanking time here enables the converter to provide a
high power in case the increase in VFB is due to a
sudden load increase. During off-time of the power
switch, the voltage at the zero-crossing pin is
monitored for output over-voltage detection. If the
voltage is higher than the preset threshold vZCOVP, the
IC is latched off after the preset blanking time.
If the junction temperature of IC exceeds 140 C, the IC
enter into autorestart mode.
If the voltage at the current sensing pin is higher than
the preset threshold vCSSW during on-time of the power
switch, the IC is latched off. This is short-winding
protection.
During latch-off protection mode, when the VCC
voltage drops to 10.5V,the startup cell is activated and
the VCC voltage is charged to 18V then the startup cell
is shut down again and repeats the previous procedure.
There is also an maximum on time limitation inside
ICE2QS03. Once the gate voltage is high longer than
tOnMAx, it is turned off immediately.

immediately after leaving Active Burst Mode. This is

helpful to decrease the output voltage undershoot.

VFB

Leaving
Active Burst
Mode

Entering
Active Burst
Mode

VFBLB
VFBBOn
VFBBOff
VFBEB

Blanking Window (tBEB)

VCS

1.0V

Current limit level

during Active Burst
Mode

VCSB

VVCC

VVCCoff

VO

t
Max. Ripple < 1%

Figure 8

3.6

Signals in Active Burst Mode

Protection Functions

The IC provides full protection functions. The following

table summarizes these protection functions.
Table 2
Protection features
VCC Overvoltage

Auto Restart Mode

VCC Undervoltage

Auto Restart Mode

Overload/Open Loop

Auto Restart Mode

Over temperature

Auto Restart Mode

Output Overvoltage

Latched Off Mode

Short Winding

Latched Off Mode

During operation, the VCC voltage is continuously

monitored. In case of an under- or an over-voltage, the

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Electrical Characteristics

Electrical Characteristics

Note:

All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are
not violated.

4.1
Note:

Absolute Maximum Ratings

Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7
(VCC) is discharged before assembling the application circuit.

Parameter

Symbol

Limit Values
min.

max.

Unit

Remarks

HV Voltage

VHV

500

VCC Supply Voltage

VVCC

-0.3

27

FB Voltage

VFB

-0.3

5.0

ZC Voltage

VZC

-0.3

5.0

CS Voltage

VCS

-0.3

5.0

GATE Voltage

VOUT

-0.3

27

Maximum current out from ZC pin

IZCMAX

mA

Junction Temperature

Tj

-40

125

Storage Temperature

TS

-55

150

Thermal Resistance
Junction -Ambient

RthJA

90

K/W

PG-DIP-8

ESD Capability (incl. Drain Pin)

VESD

kV

Human body model1)

1)

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)

4.2
Note:

Operating Range
Within the operating range the IC operates as described in the functional description.

Parameter

Symbol

Limit Values
min.

max.

Unit

VCC Supply Voltage

VVCC

VVCCoff

VVCCOVP V

Junction Temperature of
Controller

TjCon

-25

125

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Quasi-Resonant PWM Controller

ICE2QS03
Electrical Characteristics
4.3
4.3.1
Note:

Characteristics
Supply Section
The electrical characteristics involve the spread of values within the specified supply voltage and junction
temperature range TJ from 25 C to 125 C. Typical values represent the median values, which are
related to 25C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.

Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

Test Condition

Start Up Current

IVCCstart

300

550

VVCC =VVCCon -0.2V

VCC Charge Current

IVCCcharge1

5.0

mA

VVCC = 0V

IVCCcharge2

0.8

mA

VVCC = 1V

IVCCcharge3

1.0

mA

VVCC =VVCCon -0.2V

Maximum Input Current of

Startup Cell and CoolMOS

IDrainIn

mA

VVCC =VVCCon -0.2V

Leakage Current of
Startup Cell and CoolMOS

IDrainLeak

0.2

50

VDrain = 610V
at Tj=100C

Supply Current in normal

operation

IVCCNM

1.5

2.3

mA

output low

Supply Current in
Auto Restart Mode with Inactive
Gate

IVCCAR

300

IFB = 0A

Supply Current in Latch-off Mode

IVCClatch

300

Supply Current in Burst Mode with

inactive Gate

IVCCburst

500

950

VCC Turn-On Threshold

VVCCon

17.0

18.0

19.0

VCC Turn-Off Threshold

VVCCoff

9.8

10.5

11.2

VCC Turn-On/Off Hysteresis

VVCChys

7.5

4.3.2

VFB = 2.5V, exclude the

current flowing out from
FB pin

Internal Voltage Reference

Parameter
Internal Reference Voltage

Version 2.0

Symbol
VREF

Limit Values
min.

typ.

max.

4.80

5.00

5.20

13

Unit

Test Condition

Measured at pin FB
IFB=0

December 4, 2009

Quasi-Resonant PWM Controller

ICE2QS03
Electrical Characteristics
4.3.3

PWM Section

Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

Feedback Pull-Up Resistor

RFB

14

23

33

PWM-OP Gain

GPWM

3.18

3.3

Offset for Voltage Ramp

VPWM

0.63

0.7

Maximum on time in normal

operation

tOnMax

22

30

41

4.3.4

Current Sense

Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

Peak current limitation in normal

operation

VCSth

0.97

1.03

1.09

Leading Edge Blanking time

tLEB

200

330

460

ns

Peak Current Limitation in

Active Burst Mode

VCSB

0.29

0.34

0.39

4.3.5

Test Condition

Soft Start

Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

Soft-Start time

tSS

8.5

12

ms

soft-start time step

tSS_S1)

ms

Internal regulation voltage at

first step

VSS11)

1.76

Internal regulation voltage step

at soft start

VSS_S1)

0.56

1)

Test Condition

Test Condition

The parameter is not subjected to production test - verified by design/characterization

4.3.6

Foldback Point Correction

Parameter

Symbol

Limit Values
min.

typ.

max.

Unit

ZC current first step threshold

IZC_FS

0.35

0.5

0.621

mA

ZC current last step threshold

IZC_LS

1.8

2.2

mA

CS threshold minimum

VCSMF

0.66

Version 2.0

14

Test Condition

Izc=2.2mA, VFB=3.8V

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Quasi-Resonant PWM Controller

ICE2QS03
Electrical Characteristics
4.3.7

Digital Zero Crossing

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Zero crossing threshold voltage VZCCT

50

100

170

mV

Ringing suppression threshold

VZCRS

0.7

Minimum ringing suppression

time

tZCRS1

1.8

2.5

3.4

VZC > VZCRS

Maximum ringing suppression

time

tZCRS2

25

VZC < VZCRS

Threshold to set Up/Down

Counter to one

VFBR1

3.9

Threshold for downward

counting at low line

VFBZHL

3.2

Threshold for upward counting

at low line

VFBZLL

2.5

Threshold for downward

counting at hig line

VFBZHH

2.9

Threshold for upward counting

at highline

VFBZLH

2.3

ZC current for IC switch

threshold to high line

IZCSH

1.3

mA

ZC current for IC switch

threshold to low line

IZCSL

0.8

mA

Counter time1)

tCOUNT

Maximum restart time in normal

operation

tOffMax

1)

48
30

42

ms
57.5

The parameter is not subjected to production test - verified by design/characterization

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Quasi-Resonant PWM Controller

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Electrical Characteristics
4.3.8

Active Burst Mode

Parameter

Symbol

Limit Values

Unit

min.

typ.

max.

1.25

Feedback voltage for entering

Active Burst Mode

VFBEB

Minimum Up/down value for

entering Active Burst Mode

NZC_ABM

Blanking time for entering Active

Burst Mode

tBEB

24

ms

Feedback voltage for leaving

Active Burst Mode

VFBLB

4.5

Feedback voltage for burst-on

VFBBOn

3.6

Feedback voltage for burst-off

VFBBOff

Fixed Switching Frequency in

Active Burst Mode

fsB

52

Max. Duty Cycle in Active Burst

Mode

DmaxB

0.5

4.3.9

3.0

V
kHz

Protection

Parameter

Symbol

Limit Values
min.

typ.

max.

24.0

25.0

26.0

Unit

VCC overvoltage threshold

VVCCOVP

Over Load or Open Loop

Detection threshold for OLP
protection at FB pin

VFBOLP

Over Load or Open Loop

Protection Blanking Time

tOLP_B

20

30

44

ms

Output Overvoltage detection

threshold at the ZC pin

VZCOVP

3.55

3.7

3.84

Blanking time for Output

Overvoltage protection

tZCOVP

Threshold for short winding

protection

VCSSW

1.63

1.68

1.78

Blanking time for short-windding

protection

tCSSW

190

ns

Over temperature protection1)

TjCon

140

Note:

Test Condition

4.5

Test Condition

V
V

100

The trend of all the voltage levels in the Control Unit is the same regarding the deviation except VVCCOVP

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Quasi-Resonant PWM Controller

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Electrical Characteristics
4.3.10

Gate Drive

Parameter

Symbol

Limit Values
min.

Output voltage at logic low

VGATElow

Output voltage at logic high

VGATEhigh

9.0

Unit

Test Condition

VVCC=18V
IOUT = 20mA

VVCC=18V
IOUT = -20mA

1.0

V
V

VVCC = 7V
IOUT = 20mA

typ.

max.

1.0

10.0

Output voltage active shut down VGATEasd

Rise Time

trise

117

ns

COUT = 1.0nF
VGATE= 2V ... 8V

Fall Time

tfall

27

ns

COUT = 1.0nF
VGATE= 8V ... 2V

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Quasi-Resonant PWM Controller

ICE2QS03
Outline Dimension

Outline Dimension

PG-DIP-8-6 / PG-DIP-8-9
(Leadfree Plastic Dual In-Line Outline)

Figure 9

PG-DSO-8 (Pb-free lead plating Plastic Dual Small Outline)

Dimensions in mm

Version 2.0

18

December 4, 2009

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