PARISUTHAM INSTITUTE OF TECHNOLOGY & SCIENCE,

THANJAVUR

DEPARTMENT OF ECE

COURSE FILE
Digital Electronics
EC6302

Content
Aim, objectives
Syllabus
Lesson Plan
Assignments
Seminars
URLS
Question Bank
Student Result Analysis
University Question papers
Prepared By
Dinesh Sundar.S
AP/ECE,

Digital Electronics
EC6302
AIM

To analyze different methods used for simplification of Boolean expressions.

To design and implement Combinational circuits.

To design and implement synchronous and asynchronous sequential circuits.

To write simple HDL codes for the circuits.

OBJECTIVES

To introduce basic postulates of Boolean algebra and shows the correlation between
Boolean expressions

To introduce the methods for simplifying Boolean expressions

To outline the formal procedures for the analysis and design of combinational circuits
and sequential circuits

To introduce the concept of memories and programmable logic devices.

To illustrate the concept of synchronous and asynchronous sequential circuits

Syllabus
EC6302
UNIT I

DIGITAL ELECTRONICS

LTPC

MINIMIZATION TECHNIQUES AND LOGIC GATES

3003
9

Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle

of Duality - Boolean expression - Minimization of Boolean expressions Minterm
Maxterm - Sum of Products (SOP) Product of Sums (POS) Karnaugh map Minimization
Dont care conditions Quine - Mc Cluskey method of minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR
Implementations of Logic Functions using gates, NANDNOR implementations Multi
level gate implementations- Multi output gate implementations. TTL and CMOS Logic and
their characteristics Tristate gates.
UNIT II
COMBINATIONAL CIRCUITS
9
Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel
binary adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial
Adder/Subtractor - BCD adder Binary Multiplier Binary Divider - Multiplexer/
Demultiplexer decoder - encoder parity checker parity generators code converters Magnitude Comparator.
UNIT III
SEQUENTIAL CIRCUITS
9
Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation
Application table Edge triggering Level Triggering Realization of one flip flop using
other flip flops serial adder/subtractor- Asynchronous Ripple or serial counter
Asynchronous Up/Down counter - Synchronous counters Synchronous Up/Down counters
Programmable counters Design of Synchronous counters: state diagram- State table
State minimization State assignment - Excitation table and maps-Circuit implementation Modulon counter, Registers shift registers - Universal shift registers Shift register
counters Ring counter Shift counters - Sequence generators.
UNIT IV
MEMORY DEVICES
9
Classification of memories ROM - ROM organization - PROM EPROM EEPROM
EAPROM, RAM RAM organization Write operation Read operation Memory cycle Timing wave forms Memory decoding memory expansion Static RAM Cell- Bipolar
RAM cell MOSFET RAM cell Dynamic RAM cell Programmable Logic Devices
Programmable Logic Array (PLA) - Programmable Array Logic (PAL) Field
Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using
ROM, PLA, PAL
UNIT V

SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

9

Synchronous Sequential Circuits: General Model Classification Design Use of

Algorithmic State Machine Analysis of Synchronous Sequential Circuits

Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits
Incompletely specified State Machines Problems in Asynchronous Circuits Design of
Hazard Free Switching circuits. Design of Combinational and Sequential circuits using
VERILOG.
TOTAL: 45 PERIODS
TEXT BOOK:
1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 /
Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.
REFERENCES:
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008.
2. John.M Yarbrough, Digital Logic Applications and Design , Thomson Learning, 2006.
3. Charles H.Roth. Fundamentals of Logic Design, 6th Edition, Thomson Learning, 2013.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications , 6th
Edition, TMH, 2006.
5. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc, 2011 6.
Donald D.Givone, Digital Principles and Design, TMH, 2003.

LESSON PLAN

Sub Code& Name : EC6302 - DIGITAL ELECTRONICS

Unit: I
UNIT I

Branch: ECE

Semester:III

MINIMIZATION TECHNIQUES AND LOGIC GATES

Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of

Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm - Sum of
Products (SOP) Product of Sums (POS) Karnaugh map Minimization Don t care conditions
Quine - McCluskey method of minimization.
Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR and ExclusiveNOR Implementations
of Logic Functions using gates, NANDNOR implementations Multi level gate implementationsMulti output gate implementations. TTL and CMOS Logic and their characteristics Tristate gates.
Objective: To introduce basic postulates of Boolean algebra and shows the correlation between
Boolean expressions

Session
No
1.
2.

Teaching
Method
Topics to be covered
AND, OR, NOT, NAND, NOR, ExclusiveOR
and ExclusiveNOR Implementations of Logic
Functions using gates
Boolean postulates and laws and De-Morgans
Theorem

Time

Ref

50m

50m

Pg.No
1
PPT&BB
1

PPT&BB

PPT&BB

10

PPT&BB

14

PPT&BB

20

PPT&BB

3.

Principle of Duality

50m

4.

Boolean expression and Minimization of Boolean

expressions.

50m

5.

Minterm and Maxterm

50m

6.

Sum of Products (SOP) and Product of Sums

(POS)

50m

7.

Karnaugh map Minimization

50m

22

PPT&BB

8.

Dont care conditions

50m

25

PPT&BB

Quine - Mc Cluskey method of minimization.

50m

30

PPT&BB

50m

39

PPT&BB

10.

NAND,NOR implementations and Multi level

gate implementations- Multi output gate
implementations.

11.

TTL and CMOS Logic and their characteristics.

50m

42

PPT&BB

12.

Tristate gates.

50m

45

PPT&BB

9.

2
2,4

LESSON PLAN

Sub Code& Name : EC6302 - DIGITAL ELECTRONICS

Unit: II
Branch: ECE
Semester: III
UNIT II
COMBINATIONAL CIRCUITS
9
Design procedure Half adder Full Adder Half subtractor Full subtractor Parallel binary
adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor BCD adder Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder - encoder
parity checker parity generators code converters - Magnitude Comparator.
Objective: To study the design procedure of combinational circuits

Session
No

Topics to be covered

Pg.No

Teaching
Method

61

PPT&BB

Time

Ref
1,4
1,4

PPT&BB

13.

Design procedure of Half adder and Full Adder

14.

Half subtractor and Full subtractor

50m
50m

15.

Parallel binary adder

50m

1,4

PPT&BB

16.

parallel binary Subtractor

50m

1,4

PPT&BB

17.

Fast Adder and Carry Look Ahead adder

50m

PPT&BB

18.

Serial Adder/Subtractor

50m

1
1,4

19.

BCD adder Binary Multiplier

50m

PPT&BB

20.

Binary Divider - Multiplexer/ Demultiplexer

50m

PPT&BB

21.

decoder - encoder

50m

PPT&BB

22.

parity checker parity generators

50m

1,4

PPT&BB

23.

code converters

50m

PPT&BB

24.

Magnitude Comparator

50m

PPT&BB

25.

Quiz Hour

50m

26.

Video Hour

50m

PPT&BB

PPT

LESSON PLAN

Sub Code& Name : EC6302 - DIGITAL ELECTRONICS

Unit: III
Branch: ECE
Semester: III

UNIT III
SEQUENTIAL CIRCUITS
9
Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation
Application table Edge triggering Level Triggering Realization of one flip flop using
other flip flops serial adder/subtractor- Asynchronous Ripple or serial counter
Asynchronous Up/Down counter - Synchronous counters Synchronous Up/Down counters
Programmable counters Design of Synchronous counters: state diagram- State table
State minimization State assignment - Excitation table and maps-Circuit implementation Modulon counter, Registers shift registers - Universal shift registers Shift register
counters Ring counter Shift counters - Sequence generators.
Objective: To study the design procedure of sequential circuits.

Session
No

Topics to be covered

Time

Ref

Pg.No

Teaching
Method

27.

Latches, Flip-flops - SR, JK, D

50m

PPT&BB

28.

T, and Master-Slave FF

50m

PPT&BB

29.

Edge triggering Level Triggering

50m

PPT&BB

30.

Realization of one flip flop using other flip flops

50m

PPT&BB

31.

serial adder/subtractor

50m

1,4

PPT&BB

32.

Asynchronous Ripple or serial counter

50m

1,3

PPT&BB

33.

Asynchronous Up/Down counter

50m

PPT&BB

34.

Synchronous counters and Synchronous Up/Down

counters

50m

1,4

PPT&BB

35.

Programmable counters

50m

PPT&BB

36.

Design of Synchronous counters

PPT&BB

PPT&BB

PPT&BB

PPT&BB

37.

shift registers - Universal shift registers

38.

Shift register counters Ring counter

39.

Shift counters - Sequence generators.

50m
50m
50m
50m

LESSON PLAN

Sub Code& Name : EC6302 - DIGITAL ELECTRONICS

Unit: IV
Branch: ECE
Semester: III
UNIT IV
MEMORY DEVICES
9
Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM,
RAM RAM organization Write operation Read operation Memory cycle - Timing wave forms
Memory decoding memory expansion Static RAM Cell- Bipolar RAM cell MOSFET RAM
cell Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA) Programmable Array Logic (PAL) Field Programmable Gate Arrays (FPGA) - Implementation of
combinational logic circuits using ROM, PLA, PAL
Objective: To introduce the concept of memories and programmable logic devices
Session
No

Topics to be covered

Time

Ref

Pg.No

Teaching
Method

40.

Classification of memories

50m

PPT&BB

41.

ROM - ROM organization - PROM EPROM

50m

PPT&BB

42.

EEPROM EAPROM,

50m

PPT&BB

43.

RAM RAM organization

50m

1,4

PPT&BB

44.

Memory decoding and memory expansion

50m

PPT&BB

45.

Static RAM Cell- Bipolar RAM cell

50m

PPT&BB

46.

MOSFET RAM cell Dynamic RAM cell

50m

1,7

PPT&BB

47.

Programmable Logic Devices

50m

1,7

PPT&BB

48.

Programmable Logic Array (PLA)

50m

1,7

PPT&BB

49.

Programmable Array Logic (PAL) Field Programmable

Gate Arrays (FPGA)

50m

1,7

PPT&BB

50.

Quiz Hour

50m

51.

Video Hour

50m

PPT

LESSON PLAN
Sub Code& Name : EC6302 - DIGITAL ELECTRONICS
Unit: II
Branch: ECE
Semester: III
UNIT V

SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Synchronous Sequential Circuits: General Model Classification Design Use of

Algorithmic State Machine Analysis of Synchronous Sequential Circuits
Asynchronous Sequential Circuits: Design of fundamental mode and pulse mode circuits
Incompletely specified State Machines Problems in Asynchronous Circuits Design of
Hazard Free Switching circuits. Design of Combinational and Sequential circuits using
VERILOG.
Session
No

Topics to be covered

Time

Ref

Pg.No

Teaching
Method

52.

General Model Synchronous Sequential Circuits

50m

PPT&BB

53.

Classification of Synchronous Sequential Circuits

50m

1,3

PPT&BB

54.

Design of Synchronous Sequential Circuits

50m

1,3

PPT&BB

55.

Use of Algorithmic State Machine

50m

PPT&BB

56.

Analysis of Synchronous Sequential Circuits

Design of fundamental mode of Asynchronous

50m

PPT&BB

PPT&BB

57.

50m

Sequential Circuits

58.

pulse mode circuits

50m

PPT&BB

59.

Problems in Asynchronous Circuits

50m

1,4

PPT&BB

60.

Incompletely specified State Machines

50m

1,4

PPT&BB

61.

Design of Hazard Free Switching circuits

Design of Combinational and Sequential circuits
using VERILOG.

50m

PPT&BB

PPT&BB

62.

50m

TEXT BOOK:
1. M. Morris Mano, Digital Design, 4th Edition, Prentice Hall of India Pvt. Ltd., 2008 /
Pearson Education (Singapore) Pvt. Ltd., New Delhi, 2003.

REFERENCES:
1. John F.Wakerly, Digital Design, Fourth Edition, Pearson/PHI, 2008.
2. John.M Yarbrough, Digital Logic Applications and Design , Thomson Learning, 2006.
3. Charles H.Roth. Fundamentals of Logic Design, 6th Edition, Thomson Learning, 2013.
4. Donald P.Leach and Albert Paul Malvino, Digital Principles and Applications , 6th
Edition, TMH, 2006.
5. Thomas L. Floyd, Digital Fundamentals, 10th Edition, Pearson Education Inc, 2011
6. Donald D.Givone, Digital Principles and Design, TMH, 2003.

PARISUTHAM INSTITUTE OF TECHNOLOGY & SCIENCE, THANJAVUR

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC6302 - DIGITAL ELECTRONICS

Assignment Topics
1. Basic law of Boolean algebra and demorgans theorems
2. Asynchronous Up/Down counters and Synchronous Up/Down counters
3. ROM - ROM organization and RAM RAM organization
4. PLD, PLA, PAL, FPGA
5. Combinational and Sequential circuits using VERILOG
TOPIC

ASSIGNED DATE

S.
N
1.
2.
3.

D.NO

3501
3502
3503

NAME OF THE
STUDENT
ANANDHI.R
ANITHA.A
ARAVIND.R

4.

3505

BALATHANGAM.
R

5.

3508

JAGADESH.R.P

6.

3509

7.

3510

8.

3511

9.

3513

MAHALAKSHMI.
R

10.

3514

MATHIPRIYA.P

11.

3515

12.

3516

MATHIVATHINI.V
MEHARAJ
BEGUM.R

13.

3517

PAVITHRA.R

14.

3518

PRAVEENA.T
PRIYADHARSHIN
I.K

15.

3519

KRISHNA
KUMAR.R
KRISHNAVARTHI
NI.M
KRISHNAVENI.A

SUB. DATE

MARK

SUB.
DATE

MARK

SUB.
DATE

MARK

SUB.
DATE

MARK

SUB.
DATE

MARK

16.
17.
18.
19.
20.

3520

RAMYA DEVI.B

3521

RAMYA.G

3522

RANJITHA.R

3523
3524

SABEENA.P

SANKARI.M
SHREEN
SITHARA.M

21.

3525

22.

3526

SIVAKAMI.N

23.

3527

SUGANYA.P

24.

3528

SWATHI.K

25.

3529

26.

3530

VIDHYA.J
VISWADHARSHI
NI.G

27.

PRITHIVIRAJ.G

PARISUTHAM INSTITUTE OF TECHNOLOGY & SCIENCE, THANJAVUR

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING

S.No.
1.

D.No.
3501

2.
3502
3.
3503
4.
3505
5.
3508
6.
3509
7.
3510
8.

Name

Seminar Topics
EC6302 - DIGITAL ELECTRONICS
Seminar Topic

ANANDHI.R

Problems on Boolean postulates and

laws and De-Morgans Theorem

ANITHA.A

Problems on Principle of Duality

ARAVIND.R

Problems on Boolean expression and

Minimization of Boolean expressions.

BALATHANGAM.R

Problems on Minterm and Maxterm

JAGADESH.R.P
KRISHNA KUMAR.R
KRISHNAVARTHINI.M

Problems on Dont care conditions

KRISHNAVENI.A

Problems on Quine - Mc Cluskey

method of minimization.

3511
9.

MAHALAKSHMI.R

3513
10.

MATHIPRIYA.P

3514
11.
3515
12.
3516
13.
3517

MATHIVATHINI.V

15.
3519

Problems on : AND, OR, NOT, NAND,

NOR, ExclusiveOR and Exclusive
NOR Implementations of Logic
Functions using gates
Problems on : NAND,NOR
implementations and Multi level gate
implementations- Multi output gate
implementations.
Problems on : Half adder and Full Adder

MEHARAJ BEGUM.R

Problems on : Half subtractor and Full

subtractor

PAVITHRA.R

Problems on Parallel binary adder

14.
3518

Problems on Sum of Products (SOP) and

Product of Sums (POS)
Problems on Karnaugh map
Minimization

PRAVEENA.T
PRIYADHARSHINI.K

16.

Problems on parallel binary Subtractor

Problems on Fast Adder and Carry
Look Ahead adder
Problems on Serial Adder/Subtractor

3520

RAMYA DEVI.B

3521

RAMYA.G

3522

RANJITHA.R

Problems on BCD adder Binary

Multiplier
Problems on Binary Divider Multiplexer/ Demultiplexer

SABEENA.P

Problems on decoder - encoder

3524

SANKARI.M

Problems on parity checker parity

generators

3525

SHREEN SITHARA.M

17.
18.
19.
3523
20.
21.

Problems on code converters

Signature

22.
3526
23.
3527
24.
3528

SIVAKAMI.N
SUGANYA.P
SWATHI.K

25.

Problems on Latches, Flip-flops - SR,

JK, D
Problems on T, and Master-Slave FF
Problems on Edge triggering Level

3529
26.
3530
27.

Problems on Magnitude Comparator

VIDHYA.J
VISWADHARSHINI.G
PRITHIVIRAJ.G

Triggering
Problems on Realization of one flip

flop using other flip flops

Problems on serial adder/subtractor

Student Result Progress

DEPARTMENT - E.C.E
EC6302 - DIGITAL
ELECTRONICS
S.N

D.NO

NAME OF THE
STUDENT

3501 ANANDHI.R

3502 ANITHA.A

3503 ARAVIND.R

3505 BALATHANGAM.R

3508 JAGADESH.R.P

3509 KRISHNA KUMAR.R

3510 KRISHNAVARTHINI.M

3511 KRISHNAVENI.A

3513 MAHALAKSHMI.R

10

3514 MATHIPRIYA.P

11

3515 MATHIVATHINI.V

12

3516 MEHARAJ BEGUM.R

13

3517 PAVITHRA.R

14

3518 PRAVEENA.T

15

3519 PRIYADHARSHINI.K

16

3520 RAMYA DEVI.B

17

3521 RAMYA.G

18

3522 RANJITHA.R

19

3523 SABEENA.P

20

3524 SANKARI.M

21

3525 SHREEN SITHARA.M

22

3526 SIVAKAMI.N

23

3527 SUGANYA.P

24

3528 SWATHI.K

25

3529 VIDHYA.J

26

3530 VISWADHARSHINI.G

27

PRITHIVIRAJ.G

II YEAR III SEMESTER

DAT1

DAT2

CAT1

DAT5
DAT3

DAT4

CAT2

RH

PARISUTHAM INSTITUTE OF TECHNOLOGY & SCIENCE, THANJAVUR

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING

EC6302 - DIGITAL ELECTRONICS

URLs
https://www.youtube.com/watch?v=eJHmVlzH_9Q
https://www.youtube.com/watch?
v=KHANLI4UPcs&list=PL1bJYTiT8D7znDBm008s56WsSYc40r2TF
https://www.youtube.com/watch?v=eJHmVlzH_9Q&list=PL0bnDC6WD-NwXyPx7QSDpKwG9-yvgKHR
https://www.youtube.com/watch?v=95kv5BF2Z9E&list=PLOVLSMwk-KPbRbgHx3OZyVZkVWI-210O
https://www.youtube.com/watch?v=q2OBYz3K6PM&index=2&list=PLOVLSMwkKPbRbgHx3OZy-VZkVWI-210O
https://www.youtube.com/watch?
v=MsABf5IkxEU&index=2&list=PL1bJYTiT8D7znDBm008s56WsSYc40r2TF
https://www.youtube.com/watch?
v=PCT76PsDr6g&list=PL1bJYTiT8D7znDBm008s56WsSYc40r2TF&index=3
https://www.youtube.com/watch?v=K6cj3NaUqyU&index=4&list=PLOVLSMwkKPbRbgHx3OZy-VZkVWI-210O
https://www.youtube.com/watch?v=cdMJvFT-Afc&list=PLOVLSMwk-KPbRbgHx3OZyVZkVWI-210O&index=7
https://www.youtube.com/watch?
v=aAm96cCZ76g&list=PL1bJYTiT8D7znDBm008s56WsSYc40r2TF&index=9
http://www.google.co.in/url?
sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0CBsQFjAA&url=http
%3A%2F%2Fcomputerju.com%2FMaterials%2FDSD%2FDigital-Design-4th-ed-M-MorrisMano
%2520.pdf&ei=8jKqU_mGB9CLuATlzYHYAw&usg=AFQjCNEQ1JDOV9FunyFwP_KEF1
rXJaK3Eg&bvm=bv.69620078,d.c2E

http://www.ddpp.com/

PARISUTHAM INSTITUTE OF TECHNOLOGY & SCIENCE, THANJAVUR

DEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING

QUESTION BANK
EC6302 - DIGITAL ELECTRONICS
UNIT I
MINIMIZATION TECHNIQUES AND LOGIC GATES
PART A
1.
2.
3.
4.

Convert binary number 11011110 into its decimal equivalent.

State Demorgans theorem.
Write the application of gray code.
The solution of the quadratic equation X^2-11x +22=0 is x=3 and x=6. What is the
base of the numbers?
5. Map the standard SOP expression on a karnaugh map. ABC + A B C +ABC +ABC
6. Draw the logic diagram of OR gate using universal gates.
7. Draw an active-high tri-state buffer and write its truth table.
8. Prove that the logical sum of all minterms of a Boolean function of 2 variables is 1.
9. Show that a positive logic NAND gate is a negative logic NOR gate.
10. Convert 10002 into gray code and Excess 3 code.
11. Simplify the given function : F=ABC +ABC+ABC+ABC+ABC.
12. Using 2s compliment perform the given subtraction 1011012 1101002
13. Using Boolean algebra prove xy + xy =x + y.
14. Convert the binary number 10112 to gray code.
15. Minimize the function using Boolean algebra f=x(y+wz)+wxz
16. Define Minterm & Maxterm.
17. What are the methods adopted to reduce Boolean function?
18. What is a karnaugh map?
19. State the limitations of karnaugh map?
20. Explain list out the advantages and disadvantages of K-map method?
21. List out the advantages and disadvantages of Quine-Mc Cluskeymethod?
22. Define Duality Theorem?
23. What are called dont care conditions?
24. What is a Logic gate?
25. Which gates are called as the universal gates? What are its advantages?
26. What are the types of TTL logic?
27. List the different versions of TTL
28. State advantages and disadvantages of TTL
29. Define duality property.
30. Define the sum of products?
31. Define the product of sum?
32. What are the methods adopted to reduce Boolean function?

PART B
1. Convert the following decimal numbers to their hexadecimal equivalent. i)1410 ii) 8010 iii)
300010 iv) 250010
Explain the canonical and standard forms of Boolean expression with examples.
2. Elaborate the basic laws of Boolean alzebra with sample. Write the steps for multiplying a
logic expression using a karnaugh map.
3. Implement the switching function F(x,y,z) = m(1,2,3,4,5,7)
4. Minimize the expression using Quine Mccluskey(Tabulation) method
Y=ABCD+ABCD+ABCD+ABCD+ABCD+ABCD
5. Simplify the logic function using Quine McCluskey method and realize using NAND
gates. f(A,B,C,D)=m(1,3,5,9,10,11)+d(6,8)
6. a) Draw a TTL circuit with totem pole output and explain its working.
b) With a neat diagram, explain the operation of CMOS NAND and NOR gates. i) Express
the Boolean function as POS form
(1) SOP form D = (A + B) (B + C) (4)
(ii)Minimize the given terms
M (0, 1, 4, 11, 13, 15) + p d (5, 7, 8) using Quine-McClusky methods and verify the results
using K-map methods. (12)
7. i)Implement the following function using NOR gates. (8)
Output = 1 when the inputs are S m(0,1,2,3,4) = 0 when the inputs are S m(5,6,7) .
(ii) Discuss the general characteristic of TTL and CMOS logic families.(8)
8. (a) (i) Express the Boolean function F = XY + XZ in product of Maxterm.(6)
9. Reduce the following function using K-map technique)
10. f (A, B, C, D) = p (0, 3, 4, 7, 8, 10, 12, 14) + d (2, 6) . (10)).
11. Simplify the following Boolean function by using Quine Mcclusky method
F(A,B,C,D)= S(0, 2, 3 , 6, 7, 8, 10, 12, 13)(16)
12. Simplify the given function using K map F=m(1,3,4,5,9,11,12,13,14,15)
13. List all the prime implicants and draw the logic diagram for the minimized expression
using gates (4)
14. Solve the given expression using tabular method
F= m(0,2,3,6,7,10,12,14,15) (16)
15. For the given functions :g(w,x,y,z)=m(0,3,4,5,8,11,12,13,14,15). List all prime
implicants and find the minimum product of sum expression.
16. For the given function f(a,b,c,d)=m(0,2,3,6,8,12,15)+d(1,5) Find the minimum sum of
products expression using Quine McCluskey method.
17. Find the minimum sum of product expression using K map for the function,

F= m(7,9,10,11,12,13,14,15) and realize the minimized function using only NAND gates
18. Simplify using Quine Mc Clusky method F= m(0,1,2,3,10,11,12,13,14,15)

UNIT II
COMBINATIONAL CIRCUITS
PART A
1. What is tristate logic? What are its demerits?
2. State the features of bipolar logic families.
3. Draw the logic diagram and give the truth table of half subtractor.
4. What is meant by look ahead carry?
5. Give the logical expression for sum output and carry output of a full adder.
6. Write an expression for borrow and difference in a full subtractor circuit.
7. Draw the circuits diagram for 4 bit Odd parity generator.
8. Suggest a solution to overcome the limitation on the speed of an adder.
9. Differentiate a decoder from a demultiplexer.
10. Design a half adder using verilog.
11. Draw the logic diagram of a master /slave JK flip flop.
12. Draw a 2 input CMOS NOR gate.
13. Define fanout of a digital IC.
14. What is the advantage of using schottky TTL gate?
15. Define propagation delay.
16. Define combinational logic
17. Explain the design procedure for combinational circuits
18. Define half adder and full adder
19. Define Decoder?
20. What is binary decoder?
21. Define Encoder?
22. What is priority Encoder?
23. Define multiplexer?
24. What do you mean by comparator?
25. What is BCD adder?
26. What is Magnitude Comparator?
27. What is code converter?
28. Give the applications of Demultiplexer.
29. Mention the uses of Demultiplexer
30. Give other name for Multiplexer and Demultiplexer.
31. List out the applications of multiplexer?
32. Define half subtractor and full subtractor.
33. What is meant by parity generation and checking?
34. 4bit binary adder parallel binary adder?
PART B
1. Design Half and Full subtractor circuits
2. Design a circuit that converts 8421 BCD code to Excess -3 code.
3. Design a 2 bit comparator and explain its operation in detail.

4. a)Draw the circuit of BCD adder and explain. b)What is priority encoder? How is it
different from encoder? Draw the circuit of 4 bit priority encoder and explain.
5. i)Derive the equation for a 4-bit look ahead carry adder circuit. (6)
(ii)Draw and explain the block diagram of a 4-bit serial adder to add the contents of two
registers. (10)
6. Multiply (1011)2 by (1101)2 using addition and shifting operation so draw block diagram
of the 4-bit by 4 bit parallel multiplier. (8)
Design and implement the conversion circuits for Binary code to gray code. (8) Design a
carry look ahead adder with necessary diagrams. (16)
7. (i) Implement full subtractor using demultiplexer. (10) (ii) Implement the given Boolean
function using 8 : 1 multiplexer
F(A, B, C) = S(1, 3, 5, 6) . (6)
8. Design a mod 10 synchronous counter and draw the timing diagram of it.
9. Design a 4 bit universal shift register and explain its function.
10. Design a 4:1 multiplexer using transmission gates and explain its operation.
11. Draw a 2 input NAND gate using schotky TTL logic and explain its operation.
12. Draw the circuit diagrams of 2 input CMOS NOR gate and CMOS NAND gate using
CMOS logic and explain their operation.
13. What are the different types of TTL gates available? Explain their operations taking
suitable example.
UNIT III
SEQUENTIAL CIRCUITS
PART A
1. Draw the logic diagram and give the truth table of Half Subtractor.
2. State the principle of parity checker.
3. Draw the logic diagram of T flip flop using JK flip flop.
4. How can a SIPO register used as a SISO register?
5. Mention any two differences between the edge triggering and level triggering.
6. What is meant by programmable counter? Mention its application.
7. Write down the characteristic equation for JK flipflop.
8. Distinguish between synchronous and asynchronous sequential circuits.
9. Differentiate combinational and sequential circuits.
10. What is an essential hazard?
11. Implement the function f=m(0,1,4,5,7) using 8:1 multiplexer. Design a half
subtractor using 2 to 4 decoder.
12. Design a 2 input NAND gate using 2:1 multiplexer.
13. Design a half adder.
14. Define Flip flop.
15. What are the different types of flip-flop?
16. What is the operation of RS flip-flop?
17. What is the operation of SR flip-flop?
18. What is the operation of D flip-flop?
19. What is the operation of JK flip-flop?

20. What is a master-slave flip-flop?

21. Define race around condition.
22. What is edge-triggered flip-flop?
23. Define registers.
24. Define shift registers.
25. Write the uses of a shift register
26. What are the different types of shift type?
27. What is the difference between synchronous and asynchronous counter?
28. Name the different types of counter.
29. What is up counter?
30. What is down counter?
31. What is up/down counter?
32. What is a ripple counter?
33. What are the uses of a counter?
34. Define state diagram
35. What is the use of state diagram?
36. What is state table?
37. What is a state equation?
38. What is the classification of sequential circuits?
39. Define sequential circuit?
PART B
1. Implement a fulladder with two 4x1 multiplexers.
2. Implement the following function using PLA. A(x,y,z)=m(1,2,4,6) B(x,y,z)=m(0,1,6,7)
C(x,y,z)=m(2,6)
3. a i) Draw the logic diagram of master slave SR flip flop and explain its working with truth
table.(10)
ii) Design a D flip flop using JK flip flop and explain with its truth table.(6)
4. Draw the logic diagram of 4 bit binary up /down synchronous counter and explain with
truth table .Also draw the timing diagram.
5. (a) (i) Construct a clocked JK flip flop which is triggered at the positive edge of the clock
pulse from a clocked SR flip flop consisting of NOR gates. (4)
(ii) Design a synchronous up/down counter that will count up from zero to one to two to
three, and will repeat whenever an external input x is logic 0, and will count down from three
to two to one to zero, and will repeat whenever the external input x is logic 1.
Implement your circuit with one TTL SN74LS76 device and one TTL SN74LS00 device.
(12)
(b) (i)Write down the Characteristic table for the JK flip flop with NOR gates. (4) (ii)What is
meant by Universal Shift Register? Explain the principle of Operation of 4-bit Universal Shift
Register. (12)
6. i) How will you convert a D flipflop into JK flipflop? (8
ii)Explain the operation of a JK master slave flipflop. (8)
7. Explain in detail the operation of a 4 bit binary ripple counter. (16)
8. An asynchronous circuit is described by the following excitation and output functions:

Y=x1 x2 +(x1+x2)y , z=y a) Draw the logic diagram b) Derive the transistion table and
output map.
9. Differentiate synchronous and asynchronous sequential circuits with examples.(6)
Write short notes on race conditions in asynchronous sequential circuits and explain how they
can be avoided.(10)
10. a)Design a BCD Excess 3 code converter and implement it using logic gates.(8)
b)Design a 4 bit ripple carry adder. (12)
11. Design the given functions using PAL and PROM F1=m(0,1,4,5,7,9,11,13)
F2=m(1,3,5,6,9,11,14,15)
12. Design 4 bit comparator using logic gates.
13. Implement the given function using PROM and PAL F1=m(0,1,3,5,7,9)
F2=m(1,2,4,7,8,10,11)
UNIT IV
MEMORY DEVICES
PART A
1.
2.
3.
4.

Mention any four applications of shift registers.

How does JK flip flop differ from an SR flip flop in its basic operation.
What is the need for output buffer in a PLA system?
Bring out the difference between fundamental mode and pulse mode sequential
circuits.
5. What is meant by memory expansion? Mention its limit.
6. What are the advantages of static RAM compared to Dynamic RAM?
7. Compare and contrast static RAM and dynamic RAM.
8. What is PAL? How does it differ from PLA?
9. How the semiconductor memories are classified?
10. Design a D flips flop using verilog.
11. Draw the logic diagram of 3 bit ring counter.
12. Write the excitation tables of JK and D flip flops.
13. Write the characteristic equation of JK FF and show how JKFF can be converted to
TFF.
14. Draw the logic diagram of 4 bit universal shift register.
15. Classification of memories?
16. List basic types of programmable logic devies
17. Define ROM
18. Explain ROM
19. What are the types of ROM?
20. Define ROM.
21. List the basic types of DRAMs
22. Explain PROM.
23. Explain EPROM
24. Explain EEPROM.
25. What is RAM?
26. Define RAM
27. List the two categories of RAMs.
28. Why RAMs are called as Volatile?

29. Define Static RAM and dynamic RAM

30. List the two types of SRAM
31. List the basic types of DRAMs
32. Define address and word:
33. What are the types of ROM.
34. What is programmable logic array? How it differs from ROM?
35. Why was PAL developed?
36. Why the input variables to a PAL are buffered
37. List the major differences between PLA and PAL
38. Define PLD.
39. Give the classification of PLDs.
40. Define FPGA.
41. Comparison between SRAM & DRAM
42. Comparison between PROM, PAL, PLA
PART B
1. Design the sequential circuit specified by the state diagram using JK flip flop
2. Draw a 4 bit ripple counter with D flip flop.
3. Draw the basic block diagram of PLA device and explain each block. List out its
applications. Implement a combinational circuit using PLA by taking a suitable Boolean
function.
4. a)Explain the operation of static and dynamic MOS RAM cell with necessary diagrams.
(12)
b)What are the advantages of FPGA.
5. (a) (i) We can expand the word size of a RAM by combining two or more RAM chips. For
instance, we can use two 32 8 memory chips where the number 32 represents the number of
words and 8 represents the number of bits per word, to obtain a 32 16 RAM. In this case
the number of words remains the same but the length of each word will two bytes long. Draw
a block diagram to show how we can use two 16 4 memory chips to obtain a 16 8 RAM.
(8)
(ii) Explain the principle of operation of Bipolar SRAM cell. (8)
6. (b) (i) A combinational circuit is defined as the functions
F1 = ABC+ABC+ABC
F 2 = ABC+ABC+ABC
7. i)Implement the digital circuit with a PLA having 3 inputs, 3 product terms, and 2 outputs.
(8)
(ii) Write a note on SRAM based FPGA. (8)
8. (a) Implement the following Boolean functions with a PLA
F1(A ,B ,C ) = S(0, 1, 2, 4) F2( A,B ,C ) = S(0, 5, 6, 7)
F3(A ,B , C) = S(0, 3, 5, 7) . (16)

9. Design a combinational circuit using a ROM. The circuit accepts a three bit number and
outputs a binary number equal to the square of the input number. (16)
10. Draw the logic diagram of Xilinx 4000 CLB and I/O blocks and explain their function.
11. Implement the given functions using PROM F1=m(0,1,3,4,6,7) F2=m(1,2,3,5)
12. Design a binary to gray code converter using verilog.
UNIT V
SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS
PART A
1. Define Race condition.
2. What is meant by essential hazards?
3. Give the difference between RAM and ROM.
4. What is meant by hazard and how it could be avoided?
5. Draw the block diagram for Moore model.
6. What are hazard free digital circuits?
7. What are Hazards?
8. Compare the ASM chart with a conventional flow chart.
9. Implement 2 input XOR gate using NAND-NAND logic.
10. List any two advantages of using CMOS logic.
11. What are the different types of races that occur in fundamental mode circuits.
12. Define cycle in asynchronous sequential circuits.
13. What is a hazard in asynchronous sequential circuit.
14. What are the different methods of operation in asynchronous sequential circuits.
15. What is the classification of sequential circuits?
16. Give the comparison between synchronous & Asynchronous sequential circuits?
17. Define Asynchronous sequential circuit?
18. Give the comparison between synchronous & Asynchronous counters?
19. What are the steps for the design of asynchronous sequential circuit?
20. What are the steps for the design of asynchronous sequential circuit?
21. What are the types of asynchronous circuits?
22. What is fundamental mode?
23. What is fundamental mode sequential circuit?
24. What is pulse mode circuit?
25. What are the problems involved in asynchronous circuits?
26. Define hazards.
27. What are the types of shift register?
28. State the types of counter?
29. What are the 16basic building blocks of algorithmic state machine chart?
30. What is combinational circuit?
PART B
1. Design an asynchronous sequential circuit that has 2 inputs X2 and X1 and one output z.
When X1=0 ,the output z is O. The first change X2 that occurs while X1 is 1will cause output
Z to be 1. The output Z will remain 1 until X1 returns to 0.

2. Find the circuit that has no static hazards and implement the Boolean function
F(A,B,C,D)= m(1,3,5,7,8,9,14,15)
3. i)Write short notes on shared row state assignment with an example.(8) (AUC NOV 2011)
(8)
ii)A sequential circuit has 3 D flip flop. A,B and C and one input X. It is desired by the
following flip flop functions(8)
DA=(BC+BC)X +(BC+BC)X ; DB=A , DC=B
Derive the state table for the circuit and draw two state diagrams for X=0 and other for X=1
4. i)Explain the method to eliminate static hazard in an asynchronous circuit with an example.
(10)
ii)Write short notes on verilog.(6)
5. (a) For the circuit shown in figure, write down the state table and draw the state diagram
and analyze the operation. (16)
(b) What are called as essential hazards? How does the hazard occur in sequential circuits?
How can the same be eliminated using SR latches?Give an example. (16)
6. (a) Design a three bit binary counter using T flipflops. (16)
7. (b) Design a negative-edge triggered T flipflop. (16)
8. a) Draw a 2 input NAND gate in TTL logic and explain its operation.(12)
b) Write short notes on BICMOS logic.
9. a) Design a 2 input NOR gate using CMOS logic.
b)Write short notes on CMOS logic and interfacing.
10. Discuss on the different types of hazards that occur in asynchronous sequential circuits.
11. Write short notes on i) race free assignments ii) pulse mode circuits.
12. Write short notes on races and cycles that occur in fundamental mode circuits(10)
What is an essential hazard? Explain with example.(6)
13. Explain how hazard free realization can be obtained for a boolean function.(8)
Discuss a method used for race free assignments with example.(8)
14. i. Explain run length encoding in detail. (8)
ii. Explain Transform coding in detail. (8)

Student Result Analysis

PARISUTHAM INSTITUTE OF TECHNOLOGY AND SCIENCE
RESULT ANALYSIS FOR MEASUREMENT AND INSTRUMENTATION
DEPARTMENT OF ECE

SL.NO

II \III(YEAR\SEM)

SUBJECT
CODE

BATCHES

PERCENTAGE

2008-2012

PRIMROSE

2009-2013

ACACIA

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2010-2014

FELICIA

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S.N
o

Subject Name

1.

EC6302
DIGITAL
ELECTRONICS

Re
DAT CAT
DAT CAT DAT
DAT-1
DAT
hea
-2
-1
-4
-2
-5
-3
rsa
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Felicia

Acaci
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