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The syllabus for COE 202 Fundamentals of Computer Engineering covers topics such as digital circuits, Boolean algebra, combinational and sequential circuit design, and register transfer level operations. The course includes a grading policy based on assignments, quizzes, and exams, as well as a detailed weekly breakdown of topics and course materials. Students are expected to attend regularly, with penalties for unexcused absences.

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2 views

Outline

The syllabus for COE 202 Fundamentals of Computer Engineering covers topics such as digital circuits, Boolean algebra, combinational and sequential circuit design, and register transfer level operations. The course includes a grading policy based on assignments, quizzes, and exams, as well as a detailed weekly breakdown of topics and course materials. Students are expected to attend regularly, with penalties for unexcused absences.

Uploaded by

AbdulrahmanMohammed
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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COE 202 Fundamentals of Computer Engineering

Syllabus

Catalog Description
Introduction to Computer Engineering. Digital Circuits. Boolean algebra and switching theory.
Manipulation and minimization of Boolean functions. Combinational circuits analysis and design,
multiplexers, decoders and adders. Sequential circuit analysis and design, basic flip-flops,
clocking and edge-triggering, registers, counters, timing sequences, state assignment and
reduction techniques. Register transfer level operations. (Prerequisite: PHYS 102)
Instructor
Muhammad Elrabaa Room 22-332 Phone: 1496 e-mail:elrabaa@ccse
Course Material:

1. Text Book: Morris Mano and Charles Kime, Logic and Computer Design Fundamentals,
Second Edition, Prentice Hall International, 2000.

2. Course CD: A CD containing all course lectures with animations and sound is available. The
material can be downloaded from \\coe-elrabaa\On Line Course Material. The material is divided
into 6 units with several lessons in each unit.

Grading Policy: Assignments & Quizzes 20%


Exam I 20%
Exam II 20%
Final 40%

Course Learning Outcomes Table

Course Learning Outcomes Outcome Indicators & Details


1. Ability to use math and Boolean ¾ Represent integer and fractional values in various number
algebra in performing systems
computations in various number
systems and simplification of ¾ Convert number representation from one system to another
Boolean algebraic expressions. ¾ Perform arithmetic operations in various number systems
¾ Represent data in different binary codes including error detecting
codes (parity)
¾ Simplify Boolean expressions using Boolean algebra & identities
2. Ability to design efficient ¾ Derive gate-level implementation of a given Boolean expression
combinational and sequential logic and vice versa
circuit implementations from
functional description of digital ¾ Ability to build larger combinational functions using predefined
systems. modules (e.g., decoders, multiplexers, adders, Magnitude
comparators.)
¾ Ability to build a state diagram / table for both Moore & Mealy
models from functional description
¾ Ability to design & implement Moore & Mealy model
synchronous sequential circuits using different Flip-Flop types.
¾ Ability to draw timing diagrams for major signals of both
sequential and combination circuits
3. Ability to use CAD tools to ¾ Ability to simulate and verify the operation of combinational
simulate and verify logic circuits. circuits
¾ Ability to simulate and verify the operation of sequential circuits
Course Road Map & Weekly Breakdown

Week Topic CD Material Book Ref.


Unit Lessons
Introduction, Number System and 1 1,2 and 3 1.1-1.3
1 Arithmetic
Number Base conversion, Signed Numbers 1 4, 5 and 6 5.3-5.4
2 and Signed Numbers Arithmetic
Codes and Binary Logic, Basic Identities, 1 Lesson 7. 5.4, 1.4-1.7 & 2.1-2.2
3 Algebraic Simplification 2 Lesson 1.
Canonical and Standard Forms, Physical 2 2&3 2.3 & 3.2
4 Properties of Gates
Logic Simplification using K-Maps, K- 2 4&5
5 Maps manipulation
2.4-2.5

2-Level and Multi-level implementations, 2 6&7


6 Universal Gates
2.6-2.8 & 3.4

Combinational Logic and Adders 3 1&2


7 4.3-4.5
MSI Parts 3 3&4
8 4.3-4.5 & 5.1-5.2
Design with MSI Parts 3 5, 6, 7
9 4.6 & 5.5-5.6
Sequential Circuits, Latches and FFs 4 1&2
10 6.1-6.3 & 6.7
Design of Sequential Circuits 4 3&4
11 6.4 -6.6
Analysis of Sequential Circuits 4 5
12 6.4 -6.6
Registers, Counters and Programmable 5& 1-4
13 Logic 6 1 &2
7.1-7.2 , 7.6 , 3.6,
4.6, 9.1, & 9.2
14 Data Path and Control Unit Design Hand Outs
15

Attendance Policy

• Attendance will be taken regularly. Students who are more than 10 minutes late are considered
absent,
• There will be a 0.5% grade deduction for every unexcused absence,
• Excuses for officially authorized absences must be presented no later than one week following
resumption of class attendance.
Online Lessons included on the course CD
Unit I : Number System and Codes
1 Introduction. Information Processing, and representation. Digital vs Analog quantities.
2 Number Systems. Binary, Octal and Hexadecimal #’s
3 Number System Arithmetic. Binary arithmetic (Addition, Subtraction & Multiplication). Arithmetic
in other systems.
4 Number base conversion (Dec to Bin, Oct, and Hex, General). Conv (Bin, OCT, Hex)
5 Binary Storage & Registers. Signed Binary Number representation, Signed Mag, R’s &(R-1)’s
Complement
6 Signed Binary Addition and Subtraction. R’s Complement. Signed Binary Addition and Subtraction.
(R-1)’s Complement
7 Codes. BCD, Excess-3, Parity Bits, ASCII & Uni-Codes
Unit II : Binary Logic & Gates
1 Binary logic and gates, Boolean Algebra, Basic identities of Boolean algebra. Algebraic
manipulation, Complement of a function.
2 Canonical and Standard forms, Minterms and Maxterms, Sum of products and Products of Sums.
3 Physical properties of gates: fan-in, fan-out, propagation delay. Timing diagrams. Tri-state drivers.
4 Map method of simplification: Two-, Three-, and Four-variable K-Map.
5 Map manipulation: Essential prime implicants, Non-essential prime implicants, Simplification
procedure, POS simplification, Don’t care conditions and simplification, Five, and Six-variable K-
Map.
6 Universal gates; NAND, NOR gates: 2-level implementation. Multilevel Circuits.
7 Exclusive-OR (XOR) and Equivalence (XNOR) gates, Odd and Even Functions, Parity generation
and checking.
Unit III : Combinational Logic
1 Combinational Logic, Design Procedure & Examples.
2 Half and Full Adders, Half and Full Subtractor
Ripple Carry Adder design and delay analysis
Binary Adders: 4-Bit Ripple Carry Adder,
3 Carry Look-Ahead Adder, Binary Adder-Subtractor. BCD Adder, Binary Multiplier
4 MSI parts. Decoders, Decoder expansion, combinational logic implementation using decoders,
Encoders & Priority Encoders
5 Multiplexers, Function Implementation using multiplexers, Demultiplexers
6 Magnitude Comparator.
7 Examples of MSI designs
Unit IV : Sequential Circuits
1 Sequential Circuits: Latches, Clocked latches: SR , D, T and JK. Race problem in clocked JK-Latch.
Function & Excitation Tables of clocked latches: SR, D, and JK.
2 Flip-Flops: Master-Slave, T-FF. Function & Excitation Tables of T-FF. Asynchronous/Direct Clear
and Set Inputs. Setup, Hold
3 Sequential Circuit Design: Excitation Tables. Design procedure, State diagrams and state tables.
4 Sequential Circuit Analysis: Input equations, State table.
5 Mealy vs. Moore models of FSMs. Examples.
Unit V : Registers & Counters
1 Registers, Registers with parallel load, Shift Registers. Bi-directional shift register.
2 Synchronous Binary Counters: Up-Down Counters.
3 Counters with Parallel load, enable, synchronous clear and asynchronous clear. Use of available
counters to build counters of different count.
4 Other counters: Ripple Counter, Arbitrary Count Sequence.
Unit VI : Memory & PLDs
1 Memory devices: RAMs & ROMs . Combinational Circuit Implementation with ROM

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