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HMC624ALP4E
v00.0912
ATTENUATORS - DIGITAL - SMT
0.5 dB LSB GaAs MMIC 6-BIT

DIGITAL ATTENUATOR, DC - 6 GHz
Typical Applications
Features
The HMC624ALP4E is ideal for:
0.5 dB LSB Steps to 31.5 dB
Cellular/3G Infrastructure
Power-Up State Selection
WiBro / WiMAX / 4G
High Input IP3: +55 dBm
Microwave Radio & VSAT
Low Insertion Loss: 2.2 dB @ 3.5 GHz
Test Equipment and Sensors
TTL/CMOS Compatible, Serial, Parallel

or Latched Parallel Control
IF & RF Applications
0.25 dB Typical Step Error

Single +3V or +5V Supply
24 Lead 4x4mm SMT Package: 16mm2
Functional Diagram
General Description
The HMC624ALP4E is a broadband 6-bit GaAs IC
Digital Attenuator in a low cost leadless SMT package.
This versatile digital attenuator incorporates off-chip
AC ground capacitors for near DC operation, making
it suitable for a wide variety of RF and IF applications.
The dual mode control interface is CMOS/TTL
compatible, and accepts either a three wire serial
input or a 6 bit parallel word. The HMC624ALP4E also
features a user selectable power up state and a serial
output port for cascading other Hittite serial controlled
components. The HMC624ALP4E is housed in a
RoHS compliant 4x4 mm QFN leadless package, and
requires no external matching components.
Electrical Specifications,
TA = +25 C, 50 Ohm System, with Vdd = +5V & Vctl = 0/+5V (Unless Otherwise Noted)
Parameter
Frequency (GHz)
DC - 3 GHz
3.0 - 6.0 GHz
Insertion Loss
Attenuation Range
Min.
Typ.
Max.
Units
1.5
2.3
2.4
3.8
dB
dB
31.5
dB
DC - 6 GHz
15
dB
DC - 0.8 GHz
0.8 - 6.0 GHz
(0.10 + 5% of Atten. Setting) Max.

(0.30 + 3% of Atten. Setting) Max.
dB
dB
Input Power for 0.1 dB Compression
DC - 6 GHz
30
dBm
Input Third Order Intercept Point

(Two-Tone Input Power = 10 dBm Each Tone)
DC - 6 GHz
55
dBm
DC - 6 GHz
60
90
ns
ns
Return Loss (ATTIN, ATTOUT, All Atten. States)

Attenuation Accuracy: (Referenced to Insertion Loss)
All Attenuation States
Switching Speed
tRise, tFall (10 / 90% RF)
rON , tOFF (50% LE to 10 / 90% RF)
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343
Fax: 978-250-3373
Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
HMC624ALP4E
v00.0912

Insertion Loss vs. Temperature
Normalized Attenuation [1]

(Only Major States are Shown)
[1]
-1
-2
-3
-4
-5
-10
-15
-20
-25
-30
-35
-5
0
+25 C
+85 C
0.5 dB
2 dB
1 dB
-40 C
Input Return Loss [1]
4 dB
8 dB
16 dB
31.5 dB
-5
-5
-10
-10
RETURN LOSS (dB)
RETURN LOSS (dB)
Output Return Loss [1]
-15
-20
-25
-30
-35
-15
-20
-25
-30
-35
-40
-40
0
FREQUENCY (GHz)
IL
0.5 dB
1 dB
FREQUENCY (GHz)
2 dB
4 dB
8 dB
16 dB
31.5 dB
IL
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.5 dB
Bit Error vs. Frequency [1]
Bit Error vs. Attenuation State [1]
0.8
1.5
0.6
0.4
BIT ERROR (dB)
BIT ERROR (dB)
FREQUENCY (GHz)
FREQUENCY (GHz)
0
NORMALIZED ATTENUATION (dB)
INSERTION LOSS (dB)
0.2
0
-0.2
-0.4
31.5 dB
0.5
0
-0.5
-1
-0.6
-1.5
-0.8
-1
0
12
16
20
24
28
32
-2
ATTENUATION STATE (dB)
FREQUENCY (GHz)
100 MHz
2 GHz
4 GHz
500 MHz
3 GHz
1 GHz
[1] Data taken with bias tees on input and output RF ports. Vdd = +5V & Vctl = 0/+5V.
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912

Worst Case Step Error
Between Successive Attenuation States [1]
IP3 @ Major Attenuation States [1]

70
60
0.4
IP3 (dBm)
STEP ERROR (dB)
0.6
0.2
0
-0.2
-0.4
50
40
-0.6
-0.8
30
-1
0
31.5dB
16dB
8dB
4dB
2dB
1dB
IL
.5dB
1dB
.5dB
IP3 vs. Temperature, Min. Attn State [1]
2dB
4dB
8dB
16dB
31.5dB
P0.1dB vs. Temperature, Min. Attn State [1]
70
40
35
P0.1dB (dBm)
60
50
40
30
25
20
30
15
0
FREQUENCY (GHz)
+25 C
FREQUENCY (GHz)
+85 C
+25 C
-40 C

(Low Frequency Detail)
+85 C
-40 C

70
40
35
P0.1dB (dBm)
60
IP3 (dBm)
FREQUENCY (GHz)
FREQUENCY (GHz)
IP3 (dBm)
1
0.8
50
40
30
25
20
30
15
0
0.1
0.2
0.3
0.4
0.5
0.1
FREQUENCY (GHz)
+25 C
+85 C
0.2
0.3
0.4
0.5
FREQUENCY (GHz)
-40 C
+25 C
+85 C
-40 C
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912


40
70
P0.1dB (dBm)
IP3 (dBm)
50
40
30
25
20
15
30
0
+25 C
+85 C
+25 C
-40 C

+85 C
-40 C

70
40
35
P0.1dB (dBm)
60
IP3 (dBm)
FREQUENCY (GHz)
FREQUENCY (GHz)
50
40
30
25
20
30
15
0
0.1
0.2
0.3
0.4
0.5
0.1
FREQUENCY (GHz)
+25 C
+85 C
0.2
0.3
0.4
0.5
35
60
FREQUENCY (GHz)
-40 C
+25 C
+85 C
-40 C
Serial Control Interface
The HMC624ALP4E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). The serial control interface
is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK
and LE requires clean transitions. If mechanical switches are used, sufficient debouncing should be provided. When
LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to
prevent data transition during output loading.
When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and the input register is loaded with
parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data changes the state of the part per truth table.
For all modes of operations, the state will stay constant while LE is kept low.
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912

Timing Diagram (Latched Parallel Mode)

Min. [1]
Min. serial period, tSCK
70 ns
Control set-up time, tCS
15 ns
Typ. [1]
Control hold-time, tCH
20 ns
LE setup-time, tLN
Parallel Mode
(Direct Parallel Mode & Latched Parallel Mode)
15 ns
Min. LE pulse width, tLEW
10 ns
Min LE pulse spacing, tLES
630 ns
Serial clock hold-time from LE, tCKN
10 ns
Hold Time, tPH.
0 ns
Latch Enable Minimum Width, tLEN
10 ns
Setup Time, tPS
2 ns
Note: The parallel mode is enabled when P/S is set to low.

Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch
Enable) must be at a logic high at all times to control the attenuator in this manner.
Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the
LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the
desired states the LE is pulsed. See timing diagram above for reference.
Power-Up States
PUP Truth Table
If LE is set to logic LOW at power-up, the logic state of

PUP1 and PUP2 determines the power-up state of the
part per PUP truth table. If the LE is set to logic HIGH
at power-up, the logic state of D0-D5 determines the
power-up state of the part per truth table. The attenuator latches in the desired power-up state approximately 200 ms after power-up.
Power-On Sequence
The ideal power-up sequence is: GND, Vdd, digital
inputs, RF inputs. The relative order of the digital
inputs are not important as long as they are powered
after Vdd / GND
Bias Voltage
PUP1
PUP2
Relative Attenuation
-31.5
-24
-16
Insertion Loss
0 to -31.5 dB
Note: The logic state of D0 - D5 determines the powerup state per truth table shown below when LE is high
at power-up.
Truth Table
Control Voltage Input
D5
D4
D3
D2
D1
D0
Reference
Insertion
Loss
High
High
High
High
High
High
0 dB
-0.5 dB
Idd (Typ.) (mA)
High
High
High
High
High
Low
2.4
High
High
High
High
Low
High
-1 dB
2.6
High
High
High
Low
High
High
-2 dB
High
High
Low
High
High
High
-4 dB
High
Low
High
High
High
High
-8 dB
Low
High
High
High
High
High
-16 dB
Low
Low
Low
Low
Low
Low
-31.5 dB
State
Vdd = +3V
Vdd = +5V
Low
0 to 0.5V @ 15 A
0 to 0.8V @ 15 A
High
2 to 3V @ 45 A
2 to 5V @ 65 A
[1] Vdd = 5V
LE
Vdd (V)
Control Voltage Table
Parameter
Any combination of the above states will provide an attenuation

equal to the sum of the bits selected.
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912

RF Input Power (DC - 6 GHz)
28 dBm (T = +85 C)
Digital Inputs (P/S, CLK, SERIN,

LE, PUP1, PUP2, D0-D5)
-1 to Vdd +1V
Bias Voltage (Vdd)
5.6 V
Channel Temperature
150 C
Continuous Pdiss (T = 85 C)
(derate 9.8 mW/C above 85 C) [1]
0.56 W
Thermal Resistance
116 C/W
Storage Temperature
-65 to +150 C
Operating Temperature
-40 to +85 C
ESD Sensitivity (HBM)
Class 1A
ELECTROSTATIC SENSITIVE DEVICE

OBSERVE HANDLING PRECAUTIONS
Outline Drawing
Absolute Maximum Ratings
NOTES:
1. LEADFRAME MATERIAL: COPPER ALLOY
2. DIMENSIONS ARE IN INCHES [MILLIMETERS]
3. LEAD SPACING TOLERANCE IS NON-CUMULATIVE.
4. PAD BURR LENGTH SHALL BE 0.15mm MAXIMUM.
PAD BURR HEIGHT SHALL BE 0.05mm MAXIMUM.
5. PACKAGE WARP SHALL NOT EXCEED 0.05mm.
6. ALL GROUND LEADS AND GROUND PADDLE MUST BE
SOLDERED TO PCB RF GROUND.
7. REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED
LAND PATTERN.
Package Information
Part Number
Package Body Material
Lead Finish
HMC624ALP4E
RoHS-compliant Low Stress Injection Molded Plastic
100% matte Sn
MSL Rating
MSL1
[2]
Package Marking [1]

H624A
XXXX
[1] 4-Digit lot number XXXX

[2] Max peak reflow temperature of 260 C
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912

Pin Descriptions
Pin Number
Function
Description
P/S
CLK
SERIN
LE
5, 14
GND
These pins and package bottom

must be connected to RF/DC ground.
6, 13
ATTIN,
ATTOUT
These pins are DC coupled and matched to 50 Ohms.

Blocking capacitors are required. Select value based
on lowest frequency of operation.
7 - 12
ACG1 - ACG6
External capacitors to ground is required. Select value for

lowest frequency of operation. Place capacitor as close to
pins as possible.
15
SEROUT
Serial input data delayed by 6 clock cycles.
16, 17
PUP2, PUP1
19 - 24
D5, D4, D3,

D2, D1, D0
18
Vdd
Interface Schematic
See truth table, control voltage

table and timing diagram.
See truth table, control voltage

table and timing diagram.
Supply voltage
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912

Application Circuit
Phone: 978-250-3343
Fax: 978-250-3373
HMC624ALP4E
v00.0912

Evaluation PCB
List of Materials for Evaluation PCB

117212 - HMC624ALP4 [1]
Item
Description
J1, J2
PCB Mount SMA Connector
J3
18 Pin DC Connector
J8, J11
DC Pin
C1, C6
330 pF Capacitor, 0402 Pkg.
C7, C8
1000 pF Capacitor, 0402 Pkg.
R1 - R14
100 kOhm Resistor, 0402 Pkg.
SW1, SW2
SPDT 4 Position DIP Switch
U1
HMC624ALP4E Digital Attenuator
PCB [2]
117210 Evaluation PCB
The circuit board used in the application should

use RF circuit design techniques. Signal lines
should have 50 Ohm impedance while the package
ground leads and exposed paddle should be connected directly to the ground plane similar to that
shown. A sufficient number of via holes should be
used to connect the top and bottom ground planes.
The evaluation circuit board shown is available from
Hittite upon request.
[1] Reference this number when ordering complete evaluation PCB

[2] Circuit Board Material: Arlon 25FR
Phone: 978-250-3343
Fax: 978-250-3373
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Analog Devices Inc.:

HMC624ALP4ETR HMC624ALP4E

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Analog Devices Welcomes

Hittite Microwave Corporation

THIS PAGE INTENTIONALLY LEFT BLANK

ATTENUATORS - DIGITAL - SMT

0.5 dB LSB GaAs MMIC 6-BIT

The HMC624ALP4E is ideal for:

0.5 dB LSB Steps to 31.5 dB

Power-Up State Selection

High Input IP3: +55 dBm

Microwave Radio & VSAT

Low Insertion Loss: 2.2 dB @ 3.5 GHz

Test Equipment and Sensors

TTL/CMOS Compatible, Serial, Parallel

0.25 dB Typical Step Error

(0.10 + 5% of Atten. Setting) Max.

Input Power for 0.1 dB Compression

Input Third Order Intercept Point

Return Loss (ATTIN, ATTOUT, All Atten. States)

0.5 dB LSB GaAs MMIC 6-BIT

Normalized Attenuation [1]

Input Return Loss [1]

(Only Major States are Shown)

RETURN LOSS (dB)

RETURN LOSS (dB)

Output Return Loss [1]

(Only Major States are Shown)

Bit Error vs. Frequency [1]

Bit Error vs. Attenuation State [1]

(Only Major States are Shown)

BIT ERROR (dB)

BIT ERROR (dB)

ATTENUATORS - DIGITAL - SMT

INSERTION LOSS (dB)

ATTENUATION STATE (dB)

0.5 dB LSB GaAs MMIC 6-BIT

IP3 @ Major Attenuation States [1]

STEP ERROR (dB)

IP3 vs. Temperature, Min. Attn State [1]

P0.1dB vs. Temperature, Min. Attn State [1]

IP3 vs. Temperature, Min. Attn State [1]

P0.1dB vs. Temperature, Min. Attn State [1]

ATTENUATORS - DIGITAL - SMT

0.5 dB LSB GaAs MMIC 6-BIT

P0.1dB vs. Temperature, Min. Attn State [2]

IP3 vs. Temperature, Min. Attn State [2]

P0.1dB vs. Temperature, Min. Attn State [2]

ATTENUATORS - DIGITAL - SMT

Serial Control Interface

0.5 dB LSB GaAs MMIC 6-BIT

ATTENUATORS - DIGITAL - SMT

Timing Diagram (Latched Parallel Mode)

Min. serial period, tSCK

Control set-up time, tCS

Control hold-time, tCH

(Direct Parallel Mode & Latched Parallel Mode)

Min. LE pulse width, tLEW

Min LE pulse spacing, tLES

Serial clock hold-time from LE, tCKN

Hold Time, tPH.