Perspectives of UTBB FD SOI MOSFETs

for Analog and RF Applications

Valeriya Kilchytska, Sergej Makovejev,
Mohd Khairuddin Md Arshad, Jean-Pierre Raskin
and Denis Flandre

Abstract Ultra-thin body and buried oxide (UTBB) fully depleted (FD) siliconon-insulator (SOI) MOSFETs are widely recognized as a promising candidate for
20 nm technology node and beyond, due to outstanding electrostatic control of
short channel effects (SCE). Introduction of a highly-doped layer underneath thin
buried oxide (BOX), so called ground-plane (GP), targets suppression of detrimental parasitic substrate coupling and opens multi-threshold voltage (VTh) and
dynamic-VTh opportunities within the same process as well as the use of back-gate
control schemes [1, 2]. Electrostatics, scalability and variability issues in UTBB
MOSFETs as well as their perspectives for low power digital applications are
widely discussed in the literature [15]. At the same time assessment of UTBB FD
SOI for analog and RF applications received less attention. This chapter will
discuss Figures of Merit (FoM) of UTBB MOSFETs of interest for further analog/
RF applications summarizing our original research over the last years [615].
Device analog/RF performance is assessed through the key parameters such as the
transconductance, gm, the output conductance, gd, the intrinsic gain, Av and the cutoff frequencies, fT and fmax. Particular attention is paid to (1) a wide-frequency
band assessment, the only approach that allows fair performance prediction for
analog/RF applications; (2) the effect of parasitic elements, whose impact on the
device performance increases enormously in deeply downscaled devices, in which
they can even dominate device performance. Whenever possible, we will compare
FoM achievable in UTBB FD SOI devices with those reported for other advanced
devices.

V. Kilchytska (&)  S. Makovejev  J.-P. Raskin  D. Flandre

ICTEAM Institute, Universit Catholique de Louvain, 1348 Louvain-la-Neuve, Belgium
e-mail: valeriya.kilchytska@uclouvain.be
M.K. Md Arshad
Institute of Nanoelectronic Engineering, Universiti Malaysia Perlis, 01000 Kangar, Perlis,
Malaysia
 Springer International Publishing Switzerland 2014
A. Nazarov et al. (eds.), Functional Nanomaterials and Devices for Electronics,
Sensors and Energy Harvesting, Engineering Materials,
DOI 10.1007/978-3-319-08804-4_2

27

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V. Kilchytska et al.

1 Introduction
Enormous progress of the semiconductor technology during the last decade is mostly
driven by the continuous demand for the increase of the operation speed and the
integration density of complex digital circuits. In order to be able to continue device
scaling down to 20 nm and beyond, both new materials and new device architectures
are unavoidably employed. Therefore, nowadays we deal not simply with proportional shrinking of respective device dimensions, but as well as with new architectures and materials in both channel and gate oxide. Both these factors will evidently
affect analog/RF device features. From the device architecture point of view, two
main contenders clearly appear as able to satisfy ITRS requirements for device
downscaling: planar FD SOI with ultra-thin body and ultra-thin BOX (so-called
UTBB, or UTBOX, or UT2B or ETSOI) and multiple-gate devices or MuGFET.
Focus of this chapter is UTBB FD SOI MOSFETs, while some benchmarking
with other devices is provided whenever possible. Main features which allow
UTBB FD SOI withstanding ITRS requirements for 20 nm-node and beyond are
the following:
outstanding electrostatic integrity;
effective suppression of fringing fields through the BOX (by BOX thinning);
ease of heat exhaust through the thin BOX and thus attenuated self-heating
(SH) is expected;
possibility of back-gate control schemes implementation.
However, lateral coupling of source and drain through the substrate is enhanced
in the case of thin-BOX devices. This calls for realization of highly-doped layer
just under the BOX, or so-called Ground Plane (GP), which screens or prevents
electric field lines penetration into the substrate and thus coupling through the
substrate. Furthermore, GP opens a practical way for multi-VTh and back-gate
biasing schemes realization.
Technological aspects, electrostatics, scalability and variability issues in UTBB
FD SOI MOSFETs as well as their perspectives for low power digital applications
are widely discussed and shown to be excellent [15]. However, till now almost no
attention has been paid to analog and RF performance of these devices. Similarly,
UTBB MOSFET small-signal behavior in a wide frequency range is rarely discussed except in our works issued during last 3 years [615].

2 Devices
UTBB FD SOI MOSFETs discussed in this chapter have been processed at CEALeti on UNIBONDTM SOI wafers with either 25 or 10 nm-thick BOX. Wafers
without GP, with n- and p-type GP are considered. The Si film in the channel
region is thinned down to 78 nm, depending on the wafer, and left undoped.
Elevated source-drain structures are employed to reduce parasitic resistance. The

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

29

gate stack is formed by a HfSiON dielectric with the equivalent oxide thickness of
*1.3 nm and a TiN electrode. More process details can be found e.g. in [1, 2].
The studied devices are n-channel MOSFETs with the gate length L ranging
from 30 nm to 10 lm and the channel width W from 80 nm to 10 lm. Multifingers devices are used and embedded in coplanar waveguide access pads for
performing RF characterization.

3 MOSFETs Key Parameters and Methodology Applied

It is worth firstly to list the key device parameters and FoM of interest for analog/
RF applications and describe the methodological approach, which allows a fair
comparison of different devices under different bias conditions.
Main key-factors of any MOSFET are: cut-off frequencies (fT and fmax) and
intrinsic voltage gain (Av0), which itself varies in a frequency range (as will be
discussed in Sect. 5):
gm
;
2  p  Cgg

gm gm

 VEA 6 constf
gd
Id

fT
Av0

These key factors in turn depend on such device parameters as transconductance (gm), drive/drain current (Id), output conductance (gd), Early voltage
(VEA = Id/gd), gm/Id, gate capacitance (Cgg), etc. One should not forget as well
about parasitic capacitance and resistance elements (as will be discussed below).
If one considers the application circuit level (e.g. amplifier), then it involves
gain bandwidth product, GBW, which depends in turn on the same device
parameters (gm/Id and Id):
GBW

gm
gm
Id


;
2  p  CL
Id 2  p  C L

where CL is load capacitance.

From methodological point of view, a very useful approach for analog performance assessment of different devices is calculating gm/Id as a function of
normalized drain current [16, 17]. Firstly, because such plot gives a complete
picture of studied device, which is valid for different applications: from base-band
applications, where high gain, high precision is needed, to high frequency application where high drive current is requested (Fig. 1). Secondly, as gm/Id is
inversely proportional to the subthreshold swing, S in weak inversion regime and
proportional to lCox/n (where l is mobility, Cox is oxide capacitance and n is body
factor) in strong inversion, such plot is independent of threshold voltage, VTh, of
substrate/back gate (or body) bias, Vbg and to the first order is also independent of

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V. Kilchytska et al.

Fig. 1 gm/Id versus Id/(W/L)

curves for 28 nm-long UTBB
FD SOI nMOSFET measured
at different Vbg from -2 to
2 V. Vd = 1 V. Dashed lines
are drawn to represent
Id/(W/L) extraction approach
at a fixed gm/Id = 10 or
5 V-1

L. In practice, one may fix gm/Id value and extract corresponding Id/(W/L) values as
shown in Fig. 1. This allows assessment of device performance purely related to
physical parameters as l or body factor, thus providing a fair comparison of
devices issued from different technologies, featuring different dimensions and
operated at different conditions.
Figure 2 presents the complete small-signal equivalent circuit of a MOSFET. It is
important to clearly distinguish between intrinsic elements, i.e. related to the device
itself and extrinsic (or parasitic) elements, as access resistances, fringing and overlap
capacitances. Parasitic capacitive components (for instance, capacitive coupling
between source and drain through the BOX and substrate, fringing gate-to-source
and gate-to-drain coupling, etc.) attain particular importance at high/RF frequencies.
With device length scaling down, importance of parasitic components increases
enormously. Parasitic elements can even dominate the device performance (as will
be shown in Sect. 6). Thus, ability of separate extraction of intrinsic and
extrinsic elements in advanced nowadays technologies becomes crucial. Firstly,
this allows for predicting intrinsically achievable idealistic or target values one
can reach with optimization of parasitics. Secondly, for the process/configuration
optimization, it is important to know wherefrom the problem comes (either
intrinsic or extrinsic part). Indeed, if extrinsic part limits device performance, any
innovations introduced to boost intrinsic performance (e.g. strain, orientation, etc.)
will give negligible improvement to the final device performance.
Considering equivalent circuit shown in Fig. 2, MOSFET expressions for cutoff frequencies (Eq. 1) become more complex, accounting for parasitic elements
and clearly reflecting SCE (through Cgs/Cgd ratio):
fT 

gm
1




2  p  Cgs 1 Cgd Rs Rd  Cgd  gm gd gd
Cgs

Cgs

4a

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

31

Fig. 2 MOSFET complete small-signal equivalent circuit, including both intrinsic (denoted i)
and extrinsic (denoted e) elements

fmax 

gm
1

r


 1 Cgd 
4  p  Cgs 
Cgd
Cgd
1 Cgs
gd Rg Rs 2  Cgs Rs  gm Cgs

4b

With length shrinkage, Cgd/Cgs ratio increases indicating the lost of a gate
control over the channel and dominance of control from the drain (increase of
capacitive coupling between gate and drain). Comparing Eqs. 4a, 4b and 1 one can
see that this effect can strongly degrade intrinsic cut-off frequency. Next to that,
fT and fmax are degraded by the parasitic access resistances, Rs and Rd. Gate
resistance, Rg, however, affects only fmax (see Eq. 4b). According to Eq. 1, as gm is
inversely proportional to L and proportional to W, while Cgg is proportional to the
area, fT is expected to increase with L and be independent of W. However, this does
not hold in experiments due to strong parasitic effects (as will be shown in Sect. 6).
Extraction of a complete equivalent circuit demands S-parameter measurements
in a wide frequency range. Therefore, adequate structures with RF access pads
must be included in the layout from a very beginning of the technology development. Details on the extraction procedure can be found for instance in [18].

4 UTBB FD SOI MOSFET Analog FoM

4.1 Benchmarking with Other MOSFETs
Extended benchmarking of analog FoM of UTBB FD SOI MOSFETs with respect
to other both planar FD SOI MOSFETs and multiple-gate SOI-based FinFETs was
performed in [6]. Table 1 summarizes analog FoM achievable in UTBB FD SOI
with different geometries and compares them with SOI FinFET ones. One can see
that UTBB FD SOI devices feature rather high values of Id, VEA, Av0, gm_max,
which are comparable and in certain cases can be even higher than in another

L = 100 nm
FinFET
strained FinFET
UTBB FD SOI W = 10 lm
UTBB FD SOI W = 80 nm
strained UTBB FD SOI W = 10 lm
Vd = 1 V. Vsub = 0 V

L = 30 nm
FinFET
strained FinFET
UTBB FD SOI W = 10 lm
UTBB FD SOI W = 80 nm
strained UTBB FD SOI W = 10 lm

700
1,050
810
1,220
985

1,050
1,410
1,015
1,510
1,375

gm max,
(lS/lm)

Table 1 Main analog FoM for different devices

3.1
4.7
4
6
5.6

1.2
1.3
1.74
2.3

Id/(W/L) gm/Id =
10 V-1 (lA)

10.8
16.6
13
20
17

5.1
6.4
5.4
7.2
8

Id/(W/L) gm/Id =
5 V-1 (lA)

4
5
8
15
5.5

1.2
1.5
3.4
5.5

VEA Vg * VTh (V)

12
18
20
20
16

5.1
6
11
10

VEA Vg * 1 V (V)

40
43
46
51
40.5

33.5
34
36
38

Av0_max (dB)

32
V. Kilchytska et al.

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

33

Fig. 3 gm/W as a function of Av0 for different devices and processes. Vd is in saturation (1 V in
our works and 1.1 V in [19] ). Vg = VTh + 0.6 V, Vbg = 0 V. L = 30 nm1 lm for UTBB FD
SOI MOSFETs. L = 45 nm1 lm for FinFETs. Lines are intended to guide eyes

advanced architecture as FinFET. This becomes more visible in gm/W versus Avo
metric plotted in Fig. 3 for various device architectures with different gate lengths.
It reveals that UTBB FD SOI MOSFETs clearly outperform planar MOSFETs and
non-optimized FinFETs. UTBB FD SOI MOSFETs are also very close and can
even outperform optimized FinFETs particularly if narrow channel devices
(offered simultaneously higher gm/W and higher Avo) are used.
It would be important to point out that UTBB FD SOI MOSFETs maintain their
excellent performance in a wide temperature range, with very limited degradation
of main parameters [6]. For instance, only 5 dB reduction of Av0 was observed
over 200 C. This makes UTBB FD SOI MOSFETs particularly attractive for
high-precision analog circuits. Furthermore, Avo was demonstrated [6] to be
maximized in the moderate inversion regime (at *VTh), which is beneficial for
low-power applications.

4.2 Effect of GP and Back Gate Bias

A unique feature of UTBB FD SOI architecture is related to the possibility of backgate biasing. In order to implement this back-gate biasing scheme, a highly-doped
region, or ground plane, should be formed just below the BOX. Realization of GP
region requires heavy implantation through the Si film and hence one can think
about possible l degradation. Next to that, GP suppresses substrate depletion, which
means that there is no BOX thickening (provided by substrate depletion region)
and hence body factor might be higher comparing to the no-GP case. Therefore, the
question is how these two facts affect Analog FoM? Answering this question,
[3, 8] demonstrate that gm_max and Id values stay almost unaffected. In the same time
[8] reveals the sensitivity of the intrinsic gain to GP realization and hence a special

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V. Kilchytska et al.

Fig. 4 gm/W as a function of Av0 for different Vbg. Vd = 1 V. Vg = VTh + 0.6 V.

L = 30100 nm. Lines are intended to guide eyes. Inset-table summarizes effect of back-gate
bias polarity on main analog FoM

care has to be taken in order to assure high doping level just under the BOX. If the
GP implantation is not well adjusted some reduction of intrinsic gain may appear
(due to DIBL and related VEA degradation) [8].
Effect of back-gate biasing on electrostatic and digital figures have been widely
studied [35]. In this section we discuss how back-gate bias application affects
analog FoM. From one side, negative back-gate bias results in VTh increase and
hence on-current Ion reduction, but in the same time it provides S and DIBL
decrease (i.e. improvement). From another side, application of positive Vbg pushes
channel centroid [5] to the bottom Si/BOX interface and hence higher gm and Ion
(due to higher l values [20]) might be expected. These two trends give a clear
trade-off for analog FoM. [6] demonstrates that 510 % enhancement of Id and gm
may be achieved by application of positive Vbg and that 510 dB higher Avo is
reached in the case of negative Vbg. Thus, trends in Id and Av0 dependence on the
back-gate bias are opposite and hence the choice of positive or negative bias
application for performance boosting finally depends on the target application
(either high Id or Av0) (Fig. 4).
Another way to boost the device performance available in UTBB devices with
GP is realization of so-called asymmetric double-gate (ADG) regime, i.e. gate to GP
connection Vg = Vbg (inset in Fig. 5), similar to DTMOS regime in PDSOI devices.
[2, 8] reveals that such regime does not only allow improved SCE control, but also
*20 % performance enhancement in terms of Id and gm (Fig. 5). This evidently
results into improved gm versus Avo metric; more details can be found in [8].
Even further performance boost can be expected in the case of so-called quasidouble gate (QDG) realization, i.e. simultaneous sweep of top and back gates with
a certain coefficient k (k [ 1) Vg = k*Vbg [12, 14]. Possibility of VTh modulation
together with improved SCE control accompanied by improved Ion and constant
Ioff achieved in QDG mode can be exploited for digital applications. Higher gm and

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

35

Fig. 5 gm and Ion improvement in ADG mode comparing to a standard single-gate (SG) mode
(calculated as gm_ADG/gm_SG and Ion_ADG/Ion_SG) as a function of DIBL improvement in ADG
mode (=DIBLSG - DIBLADG). Insert schematically shows ADG regime. gm is taken at
Vg = VTh + 0.6 V and Vd = 1 V. Ion is taken at Vg = Vd = 1 V. L = 30250 nm. BOX
thickness, TBOX = 10 nm

Id combined with a lower DIBL (and hence higher Av0) (Fig. 6) can potentially be
exploited for analog applications. Thinner BOX evidently appears more promising
for QDG realization [14], allowing lower k values for the same performance boost
level (Fig. 6). More details on advantages of QDG mode and its exploitation for
boosting the sleep transistor performances in the practical use case of a powergated processor can be found in [13, 14].

5 Wide Frequency Band Assessment

This section points out an importance of the wide-frequency band assessment.
Indeed, above-discussion was built on DC results but cited figures of merit vary
over frequency. Figure 7 quasi-schematically shows simulated gd variation as a
function of frequency in FD SOI MOSFET. Increase of output conductance with
frequency results in turn into decrease/degradation of intrinsic gain. This graph
points out that solely DC and/or RF based extractions are not sufficient to reproduce and predict device behavior at different frequencies. Usual DC-based
extractions give overestimated performance, whereas purely RF-based one, done
in GHz range, underestimates device performance in MHz region. Only wide
frequency band measurements allow a complete picture and thus fair analysis and
comparison of different devices.
Different effects contribute to gd variation with frequency.

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V. Kilchytska et al.

Fig. 6 Ion improvement in ADG mode comparing to a SG mode (calculated as Ion_QDG/Ion_SG) as

a function of DIBL improvement in ADG mode (=DIBLSG - DIBLQDG). BOX thicknesses of 10
and 25 nm are considered. Ion is taken at Vg % VTh. Vd = 1 V. L = 30250 nm

Fig. 7 Simulated gd variation with frequency in FD SOI nMOSFET. Dashed lines schematically
indicate transitions related to self-heating (SH) and substrate (SUB) effects. Inset-table
summarizes evolution of these effects with technology advances

gd f gd

in

Dgd

FB f

Dgd

SH f

Dgd

SUB f

The frequency independent intrinsic term gd_in is related to channel length

modulation and DIBL. The second term, Dgd_FB related to the floating body effect
can be for the first order neglected in thin-film FD SOI MOSFETs under standard
operation conditions. Two main reasons for gd variation with frequency in
advanced FD SOI devices are related to self-heating, Dgd_SH and source-to-drain
coupling through the substrate, Dgd_SUB. Self-heating effect and its increased

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

37

importance in SOI-based devices are widely known [21, 22]. Less known, substrate-related frequency dependent effect [23, 24] appears as a result of a substrate
capacitance, Csub variation with frequency resulting in the variation of the
potential at the SUB-BOX interface, which then through gm is translated into gd
variation [23]:
Dgd
tBGS

SUB

n  1  gm 

tBGS
;
tDS

CBGD
 tDS
CBGD CSBG CGBG Csub

6a
6b

Frequency dependence of Csub can be represented in a first order by two RC

networks related to majority and minority carriers response [23, 24]. With frequency increase, first minority (in tens-hundreds Hz range) and then majority
carriers (in a 100 MHz range) become unable to follow AC excitation so that Csub
decreases. Thus, two substrate-related transitions appear in gd versus frequency
curve.
Inset-Table in Fig. 7 schematically summarizes how the main effects which
degrade output conductance evolve with technology advances.
Technology progress is mostly motivated by the need of SCE control and thus,
first UTB, then UTBB and finally UTBB with GP were introduced.
Considering SH behavior with device downsizing and related technology
advances, one can expect that
1. With channel length reduction phonon boundary scattering increases, thermal
capacitance decreases, density of the current passing through the device
increases and moreover SOI-like structures, known to suffer from enhanced
self-heating start to be widely employed. All these facts contribute to the selfheating enhancement.
2. With thinning of the Si film (i.e. UTB devices) interface proximity enhances
interface scattering resulting in thermal conductivity reduction [25] and hence
thermal resistance Rth increase confirmed by simulations (see e.g. [26, 27]).
Thus, self-heating is expected to increase with Si film thinning.
3. With BOX thinning one expects reduction of self-heating due to thinner thermal
barrier and therefore easier heat exhaust from the channel. This assumption was
also confirmed by simulations [26, 27].
4. Finally, GP introduction is not expected, in a first order, to modify SH.
Considering evolution of substrate-related effect with device downsizing and
related technology advances, one can expect that
1. With channel length shortening source and drain become closer to each other
thus naturally enhancing coupling through the substrate. Therefore, substraterelated degradation is expected to increase [28, 29].
2. There is almost no effect of Si film thinning on the substrate-related effect in a
first order.

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V. Kilchytska et al.

3. With BOX thinning electric field lines penetrate stronger in the substrate. Thus,
coupling through the substrate is naturally expected to be enhanced. 2D simulations performed in [28, 29], indeed, confirm this hypothesis.
4. Finally, as GP acts as screen layer preventing substrate depletion and electric
lines penetration, thus, coupling through the substrate and related gd variation
with frequency are expected to strongly reduced.
Figure 8 gives an example of experimental gd variation with frequency in
30 nm long UTBB FD SOI device without GP under different bias conditions.
Firstly, one can see that both SH- and substrate-related transitions clearly
appear in gd frequency response. Secondly, it would be important to point out that
gd variation over the frequency range is very strong: low-frequency values are
about three times lower than those at high frequency. Thirdly, such curves allow
extracting temperature rise in the device [22]:
DT Rth  Id  Vd ; where Rth

Dgd SH
Id gLF  Vd  dId =dTa

Makovejev et al. [7] reveals that despite the use of ultra-thin BOX, device
temperature in UTBB MOSFETs can reach about 100 C at high Vg and Vd. The
temperature rise results in 57 % Id degradation [11]. However, the main problem
caused by SH in advanced UTBB devices is gd degradation which is an important
issue for analog applications. Finally, it is important to emphasize that in UTBB
devices without GP, substrate-related degradation exceeds SH-related one. This
gives an additional motivation for GP introduction.
Makovejev et al. [10], indeed, demonstrates that p-GP implementation allows
efficient reduction of substrate-related gd transition (Fig. 9) thanks to suppression
of source-to-drain coupling through the substrate. This in turn results in significantly smaller Av0 reduction at high frequencies (Fig. 9) [10].
Nowadays UTBB FD SOI devices employ BOX with thickness of either 25 or
10 nm. Makovejev et al. [11] compares them in terms of SH and its effect on the
Analog FoM degradation. It reveals that while temperature rise is indeed stronger
in devices with 25 nm-thick BOX (see inset table in Fig. 10), there is almost no
difference in gd and Id degradation caused by device heating in 10 and 25 nm-thick
BOX devices at fixed bias conditions (Fig. 10) [11]. This suggests that thicker
BOX might be used to reduce e.g. coupling through the substrate, without having
much impact on the Id and gd degradation caused by thermal effects.
Finally, comparing Av0 reduction at high frequencies in FinFETs and UTBB
MOSFETs with GP (Fig. 11), one can conclude that Av0 reduction level is very
similar (*1215 %) for these two main approaches for deeply downscaled
MOSFET realization. While both SH and substrate-related effects are present in
both types of devices, SH appears as a main source of Av0 variation (*10 %).
Therefore, further developments should be focused on the optimization of device
configuration/materials to ease the heat evacuation.

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

39

Fig. 8 The experimental gd frequency response at Vg = 0.6 and 1.2 V, Vd = 1.2 V in the UTBB
FD SOI MOSFET without GP. L = 30 nm. Wtot = W 9 Nf = 0.25 9 80 lm. TBOX = 10 nm

Fig. 9 gd and Av0 variations with frequency with respect to their values at 100 kHz at
Vg = VTh + 0.4 V, Vd = 1 V in the devices with (dashed lines) and without GP (solid lines).
L = 100 nm. Wtot = W 9 Nf = 1 9 30 lm. TBOX = 10 nm

6 UTBB FD SOI MOSFETS RF FOM

6.1 Length and Width Dependence
This section discusses the evolution of UTBB FD SOI MOSFET RF FoM with L and
W shrinking down. Thanks to the outstanding SCE control in UTBB FD SOI
MOSFETs gm/gd and Cgs/Cgd ratios (see Eq. 4a, 4b for their effect on fT, fmax) stay
higher than in other technologies [9] thus allowing relatively high fT, fmax (particularly
for the process/devices which were not optimized for RF applications) (Fig. 12).

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V. Kilchytska et al.

Fig. 10 Amplitude of SH-related gd transition as a function of Vg for UTBB FD SOI MOSFETs

with BOX thickness of 10 nm (triangles) and 25 nm (crosses). L = 100 nm. Inset table gives
respective thermal resistance, temperature rise and SH-related analog FoM degradation taken at
Vg = 1.2 V, Vd = 1 V

Fig. 11 Variation of the

intrinsic gain with frequency
with respect to its value at
100 kHz in FinFET (solid
line) and UTBB FD SOI
MOSFET (dashed line) with
pGP

As was discussed above, intrinsic cut-off frequencies are expected to increase

with L scaling down and be independent of W provided that effect of parasitic
elements is not strong. [9] studies L and W dependences of cut-off frequencies and
different parasitic elements. It reveals that while fT increases with length shrinking
(Fig. 12), this increase is smaller then one could expect from Eq. 1. Analysis of
Cgg and gm dependence on L allows for concluding that fT dependence is dominated by Cgg reduction (which is nevertheless lower than expected), while gm stays
almost constant. Another interesting observation to be pointed out is that, contrarily to general expectations and results for previous technology generations, in
advanced devices fT may become higher than fmax as a result of strong Rg effect.

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

41

Fig. 12 fT, fmax, Cgg and gm as a function of gate length in UTBB FD SOI nMOSFET without
GP. TBOX = 10 nm. Wtot = W 9 Nf = 0.5 9 80 lm. Cgg is the total gate capacitance
(Cgg = Cgs + Cgd)

Fig. 13 fT, fmax and Cgg as a function of gate width in UTBB FD SOI nMOSFET without GP.
L = 30 nm. TBOX = 10 nm. Nf = 120

Furthermore, [9] demonstrates that expected W independence of fT and fmax is not

maintained in UTBB FD SOI MOSFETs. Indeed, both fT and fmax degrade with
W reduction. It is important noting that this trend is opposite to the one obtained
from DC measurements (see e.g. Figs. 3 and 13) thus indicating the role of parasitic
elements which degrade RF performance. Effect of parasitic elements is indeed
confirmed by the equivalent circuit extraction performed in [9, 15]. W reduction was

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V. Kilchytska et al.

demonstrated to result in sub-linear Cgg decrease (whereas gm scales down almost

linearly) suggesting strong fringing field effect at the perimeter.
Next section details effect of parasitic elements and distinguishes between
extrinsic and intrinsic values.

6.2 Harmful Effect of Parasitic Elements on FoM

Md Arshad et al. [15] decomposes total (or as measured)Cgg in intrinsic Cgg_intr
(i.e. related to useful device) and extrinsic Cgg_extr (i.e. related to parasitics)
parts (Fig. 14), Cgg = Cgg_intr + Cgg_extr. It is interesting to note that extrinsic
part is smaller that intrinsic one in 100 nm-long devices, but it dominates in the
case of 50 and 30 nm long ones. In fact, Cgg_extr stays almost constant independently of the device length. As a result total measured Cgg does not scale proportionally to L.
Next to that, [15] clarifies effect of Rsd on gm extracting both as measured and
intrinsic/ideally achievable (i.e. free from Rsd) gm values. With L reduction
impact of Rsd increases and while intrinsic gm continues to growth, as measured
one stays almost invariable (Fig. 14).
Finally both these above-described effects affect cut-off frequency. [15] distinguishes as measured fT and intrinsic one when first Rsd and then both Cgg_extr and
Rsd effects are withdrawn. As measured fT is seen to be strongly degraded comparing to the intrinsically achievable one, particularly in the shortest device
(Fig. 15). One can see that while intrinsic fT (with Rsd and Cgg_extr withdrawn)
continues to grow strongly with L reduction, as measured fT slows down. It is worth
to point out again that the process was not optimized for RF applications and specific
approaches used for reduction of extrinsic Cgg and Rsd lowering were not employed.
From another side intrinsic fT with Rsd and Cgg_extr withdrawn is evidently overestimated comparing to the really achievable one as parasitic elements are
unavoidably present in real devices. Therefore, [15] goes further and calculates fT
which one could achieve in the case Rsd and Cgg_extr requirements imposed by ITRS
are respected. It demonstrates that in this case fT values of 310 GHz are achievable in
30 nm-long device, i.e. as high as requested by ITRS for LP applications.
Therefore, future work should be focused on the optimization (i.e. minimization)
of the parasitics. There are indeed some works devoted to the optimization of
parasitic elements. For example, faceted Source/Drain was demonstrated to be of
interest for the fringing capacitance reduction [30, 31]. Thicker and/or low-k capping layer, thicker gate, etc. are also discussed as a potential solution for Cgg_extr
reduction [32, 33]. Different silicides, both conventional ones (as NiSi, CoSi, etc.)
and emerging ones (e.g. platinum, erbium or ytterbium) are studied as potential
materials allowing for Rsd reduction [3436]. Furthermore, different possibilities of
performance improvement by geometry and overlap/underlap optimization are
considered [37, 38]. However, this is a subject of separate discussion which is out of
scope of this chapter. More detailed information can be found e.g. in [15].

Perspectives of UTBB FD SOI MOSFETs for Analog and RF

43

Fig. 14 Measured and intrinsic gm (gm_as measured and gm_intr) (squares) as well as total measured,
extrinsic and intrinsic Cgg (Cgg_total measured, Cgg_intr, Cgg_extr, respectively) (triangles) as a
function of gate length for UTBB FD SOI nMOSFET, without GP. TBOX = 10 nm.
Wtot = W 9 Nf = 0.5 9 80 lm

Fig. 15 Measured fT, fT with Rsd withdrawn and intrinsic fT with both Rsd and Cgg_extr withdrawn
as a function of gate length for UTBB FD SOI MOSFETs without GP. Triangle gives fT
estimation in the case of Rsd and Cgg_extr values from ITRS. TBOX = 10 nm.
Wtot = W 9 Nf = 0.5 9 80 lm. ITRS requirements based on 27 nm technology node FD-SOI
targeted high performance (HP, L = 22 nm) and low power (LP, L = 24 nm) applications are
indicated by dashed lines

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V. Kilchytska et al.

7 Conclusions
There are two main conclusions which one should keep from this chapter:
1. First conclusion concerns UTBB FD SOI MOSFET performance. This device
architecture features promising performance for analog/RF applications, which is
comparable or even outperform other technologies, particularly in the cases when
combination of high frequency with LOP/LSTP feature is needed. Furthermore,
UTBB FD SOI MOSFETs possess potential for further performance improvement through the optimization of parasitics. This suggests UTBB FD SOI as a
good contender for mobile/wireless applications with LOP/LSTP options.
2. Second conclusion concerns importance of wide frequency band characterization. We have shown that performance prediction based on DC data
exclusively may be inaccurate and device benchmarking may appear even
misleading. Next to that, impact of parasitics on device performance enormously increases with L downscaling and hence separation of intrinsic and
extrinsic elements and related performances becomes mandatory in nowadays advanced devices. These two points call for the wide frequency band
analysis for a fair FoM assessment. Therefore, adequate structures with RF
access pads should be included in the layout from the very beginning of the
technology development.
Acknowledgments The work has been partly funded by the FNRS (Belgium), by the FP7 NoE
EuroSOI+ and by Catrene Reaching 22 projects. The authors would like to thank Olivier
Faynot, Thierry Poiroux and Franois Andrieu from CEA-Leti, MINATEC, Grenoble, France for
the provided devices and valuable discussions as well as Pascal Simon from WELCOME
characterization platform of Universit catholique de Louvain, Louvain-la-Neuve, Belgium for
his assistance with high-frequency measurements setup.

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