Integrated Circuit Systems, Inc
Integrated Circuit Systems, Inc
Integrated Circuit Systems, Inc
Integrated
Circuit
Systems, Inc.
Features
Applications
Graphics: The AV9110 generates low jitter, high speed pixel
(or dot) clocks. It can be used to replace multiple expensive
high speed crystal oscillators. The flexibility of this device
allows it to generate nonstandard graphics clocks, allowing
the user to program frequencies on-the-fly.
Block Diagram
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
AV9110
Pin Configuration
Pin Descriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
P I N NA M E
X1
AV D D
AGND
VDD
GND
DATA
SCLK
CE#
CLK/X
GND
VDD
CLK
OE
X2
PIN
TYPE
Input
P ow e r
P ow e r
P ow e r
P ow e r
Input
Input
Input
Output
P ow e r
Power
Output
Input
Output
DESCRIPTION
Crystal input or TTL reference clock.
ANALOG power supply. Connect to +5V.
ANALOG GROUND.
Digital power supply. Connect to +5V.
Digital GROUND.
Serial DATA pin.
SERIAL CLOCK. Clocks shift register.
CHIP ENABLE. Active low, controls data transfer.
CMOS CLOCK divided by X output.
Digital GROUND.
Digital power supply. Connect to +5V.
CMOS CLOCK output.
OUTPUT ENABLE. Tristates both outputs when low.
Crystal input or TTL reference clock.
AV9110
Electrical Characteristics
VDD = +5V10%, TA = 0 70 C unless otherwise stated
DC/STATIC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIL
VDD = 5V
0.8
VIH
VDD = 5V
2.0
IIL
VIN = OV
-5
IIH
VIN = VDD
VOL
IOL = 8Ma
0.4
2.4
ICLKr
20
ns
ICLKf
20
ns
Supply Current
IDD
25
mA
0.78
130
MHz
No load
AC/DYNAMIC
fo
tr
25pF load
ns
tf
25pF load
ns
dt
25pF load
40
60
40
ps
125
ps
14.318
32
MHz
Jitter, 1 sigma
Jitter, absolute
fREF
Crystal input
fREF
TTL input
0.6
14.318
32
MHz
fDATA
32
MHz
tskew
400
ps
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
AV9110
Serial Programming
the data to internal latches on the rising edge of the 24th
cycle of the SCLK. Any data entered after the 24th cycle is
ignored until CE# must remain low for a minimum of 24 SLCK
clock cycles. If CE# is taken high before 24 clock cycles have
elapsed, the data is ignored (no frequency change occurs)
and the counter is reset. Tables 1 and 2 display the bit location
for generating the output clock frequency and the output
divider circuitry, respectively.
BIT
EQUATION
VARIABLE
ASSIGNMENT
N
Integer
DEFAULT
BIT
-01
-02
10
10
11
11
12
12
13
13
14
14
15
16
17
18
M
Integer
V
X
R
15
16
17
18
19
19
20
20
21
21
22
22
23
23
AV9110
Table 2
COD1
COD0
CLK/X
Output Divide
(X)
COD1
COD0
VCO
Output Divide
(R)
fREF
< 5MHz
M
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
fVCO =
NV fREF
M
fVCO
R
fCLK/X =
fVCO
RX
= NV fREF
MR
=
fVCLK
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
AV9110
Jitter
For high performance applications, the AV9110 offers extremely low jitter and excellent power supply rejection. The
one sigma jitter distribution is typically less than 125ps.
For optimum performance, the device should be decoupled
with both a 2.2mF and a 0.1mF capacitor. Refer to
Recommended Board Layout diagram on page 8.
Power-On Reset
Output Enable
CLK output
25.175 MHz
25.175 MHz
CLK/X output
6.29 MHz
12.59 MHz
CLK output
25.255 MHz
25.255 MHz
CLK/X output
6.31 MHz
12.63 MHz
AV9110
Epson
Part Number
MA-505 or ......... Surface mount crystal
MA-506
CA-301 .............. Through-hole crystal
AV9110
This is the recommended layout for the AV9110 to maximize clock performance. Shown are the power and ground connections,
the ground plane, and the input/output traces.
Use of the isolated ground plane and power connection, as shown, will prevent stray high frequency ground and system noise
from coupling to the AV9110. As when compared to using the system ground and power planes, this technique will lessen
output clock jitter. The isolated ground plane should be connected to the system ground plane at one point near the 2.2mF
decoupling cap. For lowest jitter performance, the isolated ground plane should be kept away from clock output pins and
traces. Keeping the isolated ground plane area as small as possible will minimize EMI radiation. Use a sufficient gap between
the isolated ground plane and system ground plane to prevent AC coupling. The ferrite bead in the VDD line is optional, but
will help reduce EMI.
The traces to distribute the output clocks should be over an unbroken system ground or power supply plane. The trace width
should be about two times the thickness of the PC board between the trace and the underlying plane. These guidelines help
minimize clock jitter and EMI radiation. The traces to distribute power should be as wide as possible.
AV9110
MHz
mA
AV9110 Idd
CL = pF, R = 1
MHz
AV9110
Ordering Information
AV9110-01CN14LF, AV9110-02CN14LF
AV9110-01CS14LF, AV9110-02CS14LF
Example:
Pattern Number(2 or 3 digit number for parts with ROM code patterns)
Package Type
S=SOIC
N=DIP (plastic)
10
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
AV9110
Revision History
Rev.
G
Page #
10
11
Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.
Alternative Proxies: