M27C1001

1 Mbit (128Kb x8) UV EPROM and OTP EPROM

5V 10% SUPPLY VOLTAGE in READ

OPERATION

ACCESS TIME: 35ns

LOW POWER CONSUMPTION:

32

32

Active Current 30mA at 5Mhz

Standby Current 100A

PROGRAMMING VOLTAGE: 12.75V 0.25V

PROGRAMMING TIME: 100s/word

ELECTRONIC SIGNATURE

FDIP32W (F)

PDIP32 (B)

Manufacturer Code: 20h

Device Code: 05h
DESCRIPTION
The M27C1001 is a 1 Mbit EPROM offered in the
two ranges UV (ultra violet erase) and OTP (one
time programmable). It is ideally suited for microprocessor systems requiring large programs and
is organized as 131,072 words of 8 bits.
The FDIP32W (window ceramic frit-seal package)
and the LCCC32W (leadless chip carrier package)
have a transparent lids which allow the user to expose the chip to ultraviolet light to erase the bit pattern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed
only one time and erasure is not required, the
M27C1001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.

LCCC32W (L)

PLCC32 (C)

TSOP32 (N)
8 x 20 mm

Figure 1. Logic Diagram

VCC

VPP

17

A0-A16

Q0-Q7

M27C1001

E
G

VSS
AI00710B

June 2002

1/17

M27C1001
Figure 2A. DIP Connections

Figure 2B. LCC Connections

A12
A15
A16
VPP
VCC
P
NC

VCC
P
NC
A14
A13
A8
A9
A11
G
A10
E
Q7
Q6
Q5
Q4
Q3

1 32
A7
A6
A5
A4
A3
A2
A1
A0
Q0

M27C1001

25

A14
A13
A8
A9
A11
G
A10
E
Q7

VSS
Q3
Q4
Q5
Q6

17
Q1
Q2

32
1
31
2
30
3
29
4
28
5
27
6
26
7
25
8
M27C1001
24
9
23
10
22
11
21
12
20
13
19
14
18
15
17
16

VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
VSS

AI00712

AI00711

Figure 2C. TSOP Connections

A11
A9
A8
A13
A14
NC
P
VCC
VPP
A16
A15
A12
A7
A6
A5
A4

8
9

16

Table 1. Signal Names

32

M27C1001
(Normal)

25
24

17
AI01151B

2/17

G
A10
E
Q7
Q6
Q5
Q4
Q3
VSS
Q2
Q1
Q0
A0
A1
A2
A3

A0-A16

Address Inputs

Q0-Q7

Data Outputs

Chip Enable

Output Enable

Program

VPP

Program Supply

VCC

Supply Voltage

VSS

Ground

NC

Not Connected Internally

M27C1001
Table 2. Absolute Maximum Ratings (1)
Symbol

Parameter

Value

Unit

Ambient Operating Temperature (3)

40 to 125

TBIAS

Temperature Under Bias

50 to 125

TSTG

Storage Temperature

65 to 150

VIO (2)

Input or Output Voltage (except A9)

2 to 7

Supply Voltage

2 to 7

2 to 13.5

2 to 14

TA

VCC
VA9 (2)

A9 Voltage

VPP

Program Supply Voltage

Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum DC voltage on Input or Output is 0.5V with possible undershoot to 2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes

E

A9

VPP

Q7-Q0

Read

VIL

VIL

VCC or VSS

Data Out

Output Disable

VIL

VIH

VCC or VSS

Hi-Z

Program

VIL

VIH

VIL Pulse

VPP

Data In

Verify

VIL

VIL

VIH

VPP

Data Out

Program Inhibit

VIH

VPP

Hi-Z

Standby

VIH

VCC or VSS

Hi-Z

Electronic Signature

VIL

VIL

VIH

VID

VCC

Codes

Mode

Note: X = VIH or VIL, VID = 12V 0.5V.

Table 4. Electronic Signature

Identifier

A0

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Hex Data

Manufacturers Code

VIL

20h

Device Code

VIH

05h

3/17

M27C1001
Table 5. AC Measurement Conditions
High Speed

Standard

Input Rise and Fall Times

10ns

20ns

Input Pulse Voltages

0 to 3V

0.4V to 2.4V

1.5V

0.8V and 2V

Input and Output Timing Ref. Voltages

Figure 3. AC Testing Input Output Waveform

Figure 4. AC Testing Load Circuit

1.3V

High Speed
1N914

3V
1.5V

3.3k

0V
DEVICE
UNDER
TEST

Standard
2.4V

OUT
CL

2.0V
0.8V

0.4V

AI01822

CL = 30pF for High Speed

CL = 100pF for Standard
CL includes JIG capacitance

AI01823B

Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz)

Symbol
CIN
COUT

Parameter
Input Capacitance
Output Capacitance

Test Condition

Min

Max

Unit

VIN = 0V

pF

VOUT = 0V

12

pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION
The operating modes of the M27C1001 are listed
in the Operating Modes table. A single power supply is required in the read mode. All inputs are TTL
levels except for VPP and 12V on A9 for Electronic
Signature.
Read Mode
The M27C1001 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. Chip Enable (E) is the power
control and should be used for device selection.
Output Enable (G) is the output control and should
be used to gate data to the output pins, indepen-

4/17

dent of device selection. Assuming that the addresses are stable, the address access time
(tAVQV) is equal to the delay from E to output
(tELQV). Data is available at the output after a delay
of tGLQV from the falling edge of G, assuming that
E has been low and the addresses have been stable for at least tAVQV-tGLQV.
Standby Mode
The M27C1001 has a standby mode which reduces the supply current from 30mA to 100A. The
M27C1001 is placed in the standby mode by applying a CMOS high signal to the E input. When in
the standby mode, the outputs are in a high impedance state, independent of the G input.

M27C1001
Table 7. Read Mode DC Characteristics (1)
(TA = 0 to 70C, 40 to 85C or 40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC)
Symbol

Parameter

Test Condition

Min

Max

Unit

0V VIN VCC

10

0V VOUT VCC

10

E = VIL, G = VIL,
IOUT = 0mA, f = 5MHz

30

mA

E = VIH

mA

E > VCC 0.2V

100

VPP = VCC

10

ILI

Input Leakage Current

ILO

Output Leakage Current

ICC

Supply Current

ICC1

Supply Current (Standby) TTL

ICC2

Supply Current (Standby) CMOS

IPP

Program Current

VIL

Input Low Voltage

0.3

0.8

VIH (2)

Input High Voltage

VCC + 1

VOL

Output Low Voltage

0.4

VOH

IOL = 2.1mA

Output High Voltage TTL

IOH = 400A

2.4

Output High Voltage CMOS

IOH = 100A

VCC 0.7V

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70C, 40 to 85C or 40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC)
M27C1001
Symbol

Alt

Parameter

Test Condition

-35 (3)
Min

tAVQV

tACC

Address Valid to
Output Valid

tELQV

tCE

tGLQV

Max

-45
Min

-60

Max

Min

Unit

-70

Max

Min

Max

E = VIL, G = VIL

35

45

60

70

ns

Chip Enable Low to

Output Valid

G = VIL

35

45

60

70

ns

tOE

Output Enable Low

to Output Valid

E = VIL

25

25

30

35

ns

tEHQZ (2)

tDF

Chip Enable High to

Output Hi-Z

G = VIL

25

25

30

30

ns

tGHQZ (2)

tDF

Output Enable High

to Output Hi-Z

E = VIL

25

25

30

30

ns

tAXQX

tOH

Address Transition
to Output Transition

E = VIL, G = VIL

ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.

Two Line Output Control

Because EPROMs are usually used in larger
memory arrays, this product features a 2 line control function which accommodates the use of multiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the primary device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselected memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
5/17

M27C1001
Table 8B. Read Mode AC Characteristics (1)
(TA = 0 to 70C, 40 to 85C or 40 to 125C; VCC = 5V 5% or 5V 10%; VPP = VCC)
M27C1001
Symbol

Alt

Parameter

Test Condition

-80
Min

tAVQV

tACC

tELQV

tCE

tGLQV

Address Valid to
Output Valid

-90

Max

Min

-12/-15/
-20/-25

-10

Max

Min

Max

Min

Unit

Max

E = VIL, G = VIL

80

90

100

120

ns

Chip Enable Low to

Output Valid

G = VIL

80

90

100

120

ns

tOE

Output Enable Low

to Output Valid

E = VIL

40

45

50

60

ns

tEHQZ (2)

tDF

Chip Enable High to

Output Hi-Z

G = VIL

30

30

30

40

ns

tGHQZ (2)

tDF

Output Enable High

to Output Hi-Z

E = VIL

30

30

30

40

ns

tAXQX

tOH

Address Transition
to Output Transition

E = VIL, G = VIL

ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A16

VALID
tAVQV

VALID
tAXQX

E
tGLQV

tEHQZ

G
tELQV
Q0-Q7

tGHQZ
Hi-Z

AI00713B

System Considerations
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
devices. The supply current, ICC, has three segments that are of interest to the system designer:
the standby current level, the active current level,
and transient current peaks that are produced by
the falling and rising edges of E. The magnitude of
the transient current peaks is dependent on the
capacitive and inductive loading of the device at
the output. The associated transient voltage peaks
can be suppressed by complying with the two line

6/17

output control and by properly selected decoupling

capacitors. It is recommended that a 0.1F ceramic capacitor be used on every device between VCC
and VSS. This should be a high frequency capacitor of low inherent inductance and should be
placed as close to the device as possible. In addition, a 4.7F bulk electrolytic capacitor should be
used between VCC and VSS for every eight devices. The bulk capacitor should be located near the
power supply connection point. The purpose of the
bulk capacitor is to overcome the voltage drop
caused by the inductive effects of PCB traces.

M27C1001
Table 9. Programming Mode DC Characteristics (1)
(TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol

Parameter

Test Condition

ILI

Input Leakage Current

VIL VIN VIH

ICC

Supply Current

IPP

Program Current

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage TTL

VID

A9 Voltage

Min

Max

Unit

10

50

mA

50

mA

0.3

0.8

VCC + 0.5

0.4

E = VIL

IOL = 2.1mA
IOH = 400A

2.4

11.5

12.5

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

Table 10. Programming Mode AC Characteristics (1)

(TA = 25 C; VCC = 6.25V 0.25V; VPP = 12.75V 0.25V)
Symbol

Alt

Parameter

Test Condition

Min

Max

tAVPL

tAS

Address Valid to Program Low

tQVPL

tDS

Input Valid to Program Low

tVPHPL

tVPS

VPP High to Program Low

tVCHPL

tVCS

VCC High to Program Low

tELPL

tCES

Chip Enable Low to Program Low

tPLPH

tPW

Program Pulse Width

95

tPHQX

tDH

Program High to Input Transition

tQXGL

tOES

Input Transition to Output Enable Low

tGLQV

tOE

Output Enable Low to Output Valid

tGHQZ (2)

tDFP

Output Enable High to Output Hi-Z

tGHAX

tAH

Output Enable High to Address

Transition

105

Unit

100

ns

130

ns
ns

Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
2. Sampled only, not 100% tested.

Programming
When delivered (and after each erasure for UV
EPROM), all bits of the M27C1001 are in the '1'
state. Data is introduced by selectively programming '0's into the desired bit locations. Although
only '0's will be programmed, both '1's and '0's can
be present in the data word. The only way to
change a '0' to a '1' is by die exposition to ultravio-

let light (UV EPROM). The M27C1001 is in the

programming mode when VPP input is at 12.75V,
E is at VIL and P is pulsed to VIL. The data to be
programmed is applied to 8 bits in parallel to the
data output pins. The levels required for the address and data inputs are TTL. VCC is specified to
be 6.25V 0.25V.

7/17

M27C1001
Figure 6. Programming and Verify Modes AC Waveforms
VALID

A0-A16
tAVPL
Q0-Q7

DATA IN
tQVPL

DATA OUT
tPHQX

VPP
tVPHPL

tGLQV

tGHQZ

VCC
tVCHPL

tGHAX

E
tELPL
P
tPLPH

tQXGL

PROGRAM

VERIFY
AI00714

Figure 7. Programming Flowchart

VCC = 6.25V, VPP = 12.75V

n=0

P = 100s Pulse
NO
++n
= 25
YES

FAIL

NO

VERIFY

++ Addr

YES
Last
Addr

NO

YES
CHECK ALL BYTES
1st: VCC = 6V
2nd: VCC = 4.2V
AI00715C

8/17

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the
whole array to be programmed, with a guaranteed
margin, in a typical time of 13 seconds. Programming with PRESTO II involves in applying a sequence of 100s program pulses to each byte until
a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE
circuit is automatically activated in order to guarantee that each cell is programmed with enough
margin. No overprogram pulse is applied since the
verify in MARGIN MODE provides necessary margin to each programmed cell.
Program Inhibit
Programming of multiple M27C1001s in parallel
with different data is also easily accomplished. Except for E, all like inputs including G of the parallel
M27C1001 may be common. A TTL low level
pulse applied to a M27C1001's P input, with E low
and VPP at 12.75V, will program that M27C1001.
A high level E input inhibits the other M27C1001s
from being programmed.
Program Verify
A verify (read) should be performed on the programmed bits to determine that they were correctly programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.

M27C1001
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25C 5C ambient temperature range that is required when programming the M27C1001. To activate the ES
mode, the programming equipment must force
11.5V to 12.5V on address line A9 of the
M27C1001, with VPP = VCC = 5V. Two identifier
bytes may then be sequenced from the device outputs by toggling address line A0 from VIL to VIH. All
other address lines must be held at VIL during
Electronic Signature mode.
Byte 0 (A0 = VIL) represents the manufacturer
code and byte 1 (A0 = VIH) the device identifier
code. For the STMicroelectronics M27C1001,
these two identifier bytes are given in Table 4 and
can be read-out on outputs Q7 to Q0.

ERASURE OPERATION (applies to UV EPROM)

The erasure characteristics of the M27C1001 is
such that erasure begins when the cells are exposed to light with wavelengths shorter than approximately 4000 . It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 range. Research
shows that constant exposure to room level fluorescent lighting could erase a typical M27C1001 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27C1001 is to be exposed to
these types of lighting conditions for extended periods of time, it is suggested that opaque labels be
put over the M27C1001 window to prevent unintentional erasure. The recommended erasure procedure for the M27C1001 is exposure to short
wave ultraviolet light which has a wavelength of
2537 . The integrated dose (i.e. UV intensity x
exposure time) for erasure should be a minimum
of 15 W-sec/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp with 12000 W/cm2 power rating.
The M27C1001 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.

9/17

M27C1001
Table 11. Ordering Information Scheme
Example:

M27C1001

-35

TR

Device Type
M27
Supply Voltage
C = 5V
Device Function
1001 = 1 Mbit (128Kb x8)
Speed
-35 (1) = 35 ns
-45 = 45 ns
-60 = 60 ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns
-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-25 = 250 ns
VCC Tolerance
blank = 10%
X = 5%
Package
F = FDIP32W
B = PDIP32
L = LCCC32W
C = PLCC32
N = TSOP32: 8 x 20 mm
Temperature Range
1 = 0 to 70 C
3 = 40 to 125 C
6 = 40 to 85 C
Options
X = Additional Burn-in
TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.

10/17

M27C1001
Table 12. Revision History
Date

Revision Details

September 1998

First Issue

24-Jan-2000

35ns speed class addes (Table 8A, 11)

20-Sep-2000

AN620 Reference removed

04-Jun-2002

PLCC32 Package mechanical data and drawing clarified (Table 16 and Figure 11)
TSOP32 Package mechanical data clarified (Table 17)

11/17

M27C1001
Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
Symbol

millimeters
Typ

inches

Min

Max

Typ

Min

5.72

Max
0.225

A1

0.51

1.40

0.020

0.055

A2

3.91

4.57

0.154

0.180

A3

3.89

4.50

0.153

0.177

0.41

0.56

0.016

0.022

B1

1.45

0.23

0.30

0.009

0.012

41.73

42.04

1.643

1.655

1.500

0.600

D2

38.10

15.24

E1

13.06

13.36

0.057

0.514

0.526

2.54

0.100

eA

14.99

0.590

eB

16.18

18.03

0.637

0.710

3.18

1.52

2.49

11

32

7.11

0.125
0.060

0.098

11

0.280

32

Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Package Outline

A2

A3
A1
B1

A
L

eA

D2

eB

D
S
N

E1

1
FDIPW-a

Drawing is not to scale.

12/17

M27C1001
Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
millimeters

inches

Symbol
Typ

Min

Max

A1

Min

Max

5.08

0.200

0.38

0.015

A2

3.56

4.06

0.140

0.160

0.38

0.51

0.015

0.020

0.20

0.30

0.008

0.012

41.78

42.04

1.645

1.655

B1

1.52

Typ

0.060

D2

38.10

1.500

15.24

0.600

13.59

13.84

0.535

0.545

E1
e1

2.54

0.100

eA

15.24

0.600

eB

15.24

17.78

0.600

0.700

3.18

3.43

0.125

0.135

1.78

2.03

0.070

0.080

10

10

32

32

Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline

A2
A1
B1

A
L

e1

eA

D2

eB

D
S
N

E1

1
PDIP

Drawing is not to scale.

13/17

M27C1001
Table 15. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Mechanical Data
millimeters

inches

Symbol
Typ

Min

Max

Typ

Min

Max

2.28

0.090

0.51

0.71

0.020

0.028

11.23

11.63

0.442

0.458

13.72

14.22

0.540

0.560

0.39

0.015

1.27

e1

0.050

e2

7.62

0.300

e3

10.16

0.400

1.02

0.040

0.51

0.020

1.14

1.40

0.045

0.055

L1

1.96

2.36

0.077

0.093

10.50

10.80

0.413

0.425

K1

8.03

8.23

0.316

0.324

32

32

Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Outline

e2
D

j x 45o

e
N

L1
K

e3

e1
B

K1
A

LCCCW-a

Drawing is not to scale.

14/17

h x 45o

M27C1001
Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters
Symbol

Typ

inches

Min

Max

3.18

A1

Min

Max

3.56

0.125

0.140

1.53

2.41

0.060

0.095

A2

0.38

0.015

0.33

0.53

0.013

0.021

B1

0.66

0.81

0.026

CP

Typ

0.032

0.10

0.004

12.32

12.57

0.485

0.495

D1

11.35

11.51

0.447

0.453

D2

4.78

5.66

0.188

0.223

D3

7.62

0.300

14.86

15.11

0.585

0.595

E1

13.89

14.05

0.547

0.553

E2

6.05

6.93

0.238

0.273

E3

10.16

0.400

1.27

0.050

0.00

0.13

0.000

0.005

F
N

32

0.89

32

0.035

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline

D
D1

A1
A2

1 N

B1
E2
E3

E1 E

0.51 (.020)

E2

1.14 (.045)
A

D3
R

D2

CP

D2
PLCC-A

Drawing is not to scale.

15/17

M27C1001
Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
millimeters
Symbol

Typ

inches

Min

Max

Typ

Min

1.200

0.0472

A1

0.050

0.150

0.0020

0.0059

A2

0.950

1.050

0.0374

0.0413

0.170

0.250

0.0067

0.0098

0.100

0.210

0.0039

0.0083

CP

0.100

0.0039

19.800

20.200

0.7795

0.7953

D1

18.300

18.500

0.7205

0.7283

7.900

8.100

0.3110

0.3189

0.500

0.700

0.0197

0.0276

32

0.500

0.0197

32

Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2
1

e
E
B
N/2

D1

A
CP

DIE

C
TSOP-a

Drawing is not to scale.

16/17

Max

A1

M27C1001

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