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1. What are the things you have done in DFT?

2. What is the difference between Async and Sync reset? Verilog codes for both?

3. What is boundary scan? Why do we do it?

4. What are the instructions in used in boundary scan?

5. Explain the instructions in detail for boundary scan?

6. What are the boundary scan mandatory instructions?

7. How does the TAP fsm works?

8. The instruction codes for the mandatory instruction?

9. Minimum number of bits for instruction?

10. The bypass register is one bit so how can you give 2 bits of instruction?

11. On what edge does TAP works? On what edge does tdo work?

12. Initially in which state will TAP fsm be?

13. How many pulses are required to reset the TAP fsm?

14. If I am in update state how many pulses are required for the reset?

15. Explain about boundary scan cell and how it works?

16. What are the other instruction in boundary scan?

17. What will be the default values of inputs to TAP?

18. How should be the reset if present in TAP?

19. What is scan?

20. What are the inputs for scan?

21. On what netlist we perform scan?

22. What do we do in scan?

23. What is controllability and observability?

24. What is chain balancing?

25. What scan style have you used?

26. Explain the scan cell and its working?

27. On what basis, do you decide scan chain?

28. What is compression?

29. Architecture of compression? How is works?

30. How do you decide compression ratio?

31. On what basis, compression ratio is decided?

32. Will there be any issue if I increase the compression ratio?

33. What is ATPG?

34. What are the inputs for ATPG?

35. Explain ATPG flow?

36. How do u check drc in ATPG?

37. What do you check in “Verify test structure”?

38. What are the different Fault models?

39. Why do you use transition fault model?

40. Difference between stuck at and transition?

41. What is LOC and LOS?

42. Advantages of LOS and disadvantages of LOS?

43. What is lockup latch?

44. Where do we use lockup latch?

45. Errors you get in “Build Model”?

46. What is scan chain test?

47. What is logic test?

48. Why should you use “Build model” when you have “Build Fault Model”?

49. What is OCC? What is its purpose?

50. Where do we use OCC? Explain with timing diagrams?

51. What are violations in Verify test structure?

52. What is importance of “commit test”?

53. What is the “Write vectors” how does it differ with “commit tests”?

54. Explain scan flow and Atpg flow with tool commands?

55. How do you trigger OCC?

56. What is test coverage and fault coverage?

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1. What is scan insertion?

2. What is OCC? Without OCC can we generate two pulses (alternative)

3. Explain slow to fall transition faults in circuit.

4. Once we got 100% scan? Why we are facing again DRC’S in ATPG?

5. Scan operation with diagram

6. DFT violations

7. Why DFT is required?

8. Without DFT is there any technique to use?

9. Explain compression architecture? What is compression ratio

10. How can you decide the number of scan channels?

11. What are the inputs for scan compression? And which technique is used and Why?

12. Explain clock skew ? How it can be controlled?

13. What is multicycle, critical and invalid paths?

14. What is lockup latch? What rule does it follow in scan?

15. Explain occ and opcg and their signIficance?

16. Draw D-flipflop and D- latch timing diagrams

17. Draw synchronous and asynchronous d- flip flop timing diagrams.

18. What is the difference between synchronous reset and asynchronous reset d-flip flop

19. In D-flipflop at What pin the asynchronous signal will connect?

20. Why at-speed clock is not used in shIft?

21. How to detect faults in scan chain?

22. What are the inputs for ATPG?

23. Explain D-algorithm with example?

24. Why DFT? What do you understand by DFT?

25. What is scan design? Which design have you used? And Why?

26. Explain scan insertion steps and flow?

27. How can you solve the clock skew problem while shIfting?

28. Why ATPG? ATPG flow?

29. Explain build model, build test mode, verIfy test structures and build fault model?

30. What are the issues you faced in scan insertion and ATPG?

31. Initially If you have 30% fault coverage, How you will improve for 99%

32. Explain LOC and LOS?

33. difference between stuck at and transition faults?

34. What are the inputs for simulation?

35. How you will do simulation? What you observed in simulation?

36. What are the types of simulation?

37. How to decide the number of scan chains?

38. Why we need to do shIfting in scan chain?

39. at What stage the loaded values will go to the combinational logic?

40. If compression is failed? How you will find it?

41. where the compression fit into the process?

42. How can you decide the compression ratio?

43. Explain the sr-flip flop?

44. What is the difference between latch and a flip flop?

45. What is latency?

46. Which tools are used for ATPG, scan, simulation?

47. What is chain balancing?

48. What is a logic test and scan chain test in ATPG?

49. What is scan reordering?

50. What is scan stitching?

51. How the lockup latch are connected in the scan chain?

52. What is clock skew?

53. What is setup and hold time?

54. What is glitches? How to overcome these glitches?

55. How to fix setup and hold time violations?

56. What is clock gaters?

57. What is the purpose of compression? Explain its use?

58. Why jtag? Explain its architecture?

59. Explain the boundary scan cells 1, 2, 4?

60. Explain the use of occ?

61. Why ATE limit higher frequencies?

62. Explain D- algorithm with example?

63. How scan chain works? Explain the modes of operation?

64. What type of pattern generation is ATPG?

65. What are the inputs and outputs of scan compression?

66. Is DFT has any impact on technology shrinking?

67. What is delay? Types of delay test?

68. What is transition delay testing?

69. What is path delay testing?

70. Why stuck at fault coverage is more than transition faut coverage?

71. What is transparent latch? How we loose coverage from them?

72. How to decide the sequential ATPG and Combinational ATPG?

73. What is the difference between verIfication and testing?

74. Explain DFT flow?

75. Are the faults on the resets of the flops are detected? How?

76. What is full scan design and partial scan design? And their difference?

77. Why scan chain patterns fail?

78. How tap fsm works?

79. How you will initialize the tap fsm?

80. What are the data registers in jtag?

81. What is bridging fault?

82. What is iddq fault?

83. Implement xor using 2*1 mux?

84. What is controllability and observability?

85. How can you convert rtl file to gate level netlist?

86. How can you convert normal flop to scan flop? Why is it necessary?

87. can reset pin be used as clock?

88. Explain clock driving data?

89. who takes the responsibility of converting flop to scan flop?

90. Explain design rule checks?

91. How to improve coverage analysis?

92. Why cant we use functional patterns as test patterns to detect the faults?

93. What is bypass register?

94. How you will fix the combinational feedback loop?

95. where you will find the bus contention problems?

96. How you will fix the asynchronous rule violation?

97. can we fix the asynchronous rule violation without using mux ?

98. can we fix the asynchronous rule violation for active high reset ?

99. What are the uses of boundary scan cells?

100. What are the uses of bc-7?

101. What is the fsm used in tap?

102. How many scan clocks are used in scan?

103. What is scan chain shIfting? Why we need to shIft and Why we need to capture? What do you
do in capture?

104. states in tap controller? Why data registers come before instruction register?

105. In TAP, If TMS is not toggling What happens?

106. What is test coverage and fault coverage? Its difference and which is mostly considered?

107. How did you increase your test coverage in ATPG and What are the dIfferent violations?

108. How transition faults are detected?

109. What is at-speed testing?

110. How many at-speed clocks can be generated ?

111. What is launch and capture? What do you do during launch and capture?

112. Explain mandatory instructions?

113. What is undetectable faults. How to detect faults and is test point insertion is enough to make
it controllable?

114. which approach is used for scan insertion?

115. What is adhoc approach? Explain with one example?

116. How you can reduce the test time using DFT?

117. If the compression ratio is increased, What are the issues?

118. What are the ouput files for scan and ATPG?

119. What is ATE? What it does?

120. What are test procedure files?

121. Explain cross coupled gates scan design rules?

122. What is serial and parallel simulation? Explain its difference?

123. What are the inputs for serial and parallel simulation?

124. How do you place test points after scan stitching?

125. What are the issues you faced when your design is not controllable and observable?

126. What is test mode? Explain?

127. Explain scan methodology?

128. What is scan frequency?

129. What is the tester memory capacity in your design?

130. What is lfsr?

131. What is masking logic? Its purpose?

132. How many flops are used in your project? ( complete project analysis)

133. What if I cannot able to provide capture pulse? What are the issues?

134. Explain the commands related to tcl file?

135. Why scan chain contain first negedge scan flop then posedge scan flop?

136. Is lockup latch DFT friendly?

137. What is fault collapsing, equivalence and dominance?

138. How many test patterns you have generated in your project?

139. Types of fault models?

140. How can you decide the number of test patterns in your design?

141. Why DFT require? Can we achieve DFT goals by any other method?

142. Where DFT part fit in ASIC design flow?

143. What is yield and dppm? Its difference?

144. How to detect stuck at faults? Explain with diagram?

145. What could be the possible reasons for scan chain failures during gate level simulation?

146. Can we improve the capture cycles?

147. What is sequential depth?

148. How do you test at-speed faults for inter clock domains?

149. What is integrated clock gating?

150. How ATPG pattern are useful to accelerate burn-in testing?

151. What is meant by scan chain pattern? Why it require?

152. What is the difference between vector and pattern?

153. which scan style is preferred for scan insertion?

154. What are the dIfferent untestable faults?

155. How to fix black box violation?

156. What are the reasons for scan chain broken?

157. How to debug faults in fault simulation?

158. Explain complete test procedure for fault simulation?

159. Explain sample and preload instruction?

160. Applications of boundary scan?

161. What is the importance of sequential depth?

162. How to decide capture cycles and shift cycles?

163. Why we test transition faults at at-speed?

164. What is terminal lockup latch?

165. What are redundant faults?

166. What is compression ratio? where do compressed scan chains come from?

167. What is the difference between LOC and LOS? Which is mostly used?

168. Is there any need of pll when functional frequency equals to scan frequency?

169. What is the format for test vectors?

170. Why scan clock is slow frequency? What if we give high frequency for scan chains?

171. What is shadow logic?

172. Why multi clock domains is used? Does it have any problem in design?

173. What logic we see in test point insertion?

174. What is named capture procedures?

175. How iddq test vectors are different from stuck at test?

176. Explain the decompression logic?

177. why reset is optional in jtag? When reset state occurs?

178. Explain architecture for compression?

179. why we do scan chain balancing?

180. Explain tap controller working? On what edge tap works?

181. what is the minimum bits for instruction?

182. Advantages and disadvantages of LOC and LOS?

183. What are the tools used for scan, ATPG, simulation? What is the library file name?

184. What did you do in simulation? Explain the procedure? Difference between serial and parallel
loading?

185. Difference between normal mode, functional mode and scan enable?

186. Tell me stuck at faults other than sa1 and sa0?

187. what is the difference between gate level faults and transistion level faults?
188. Why you need burn-in test?

189. what do you know about cell aware test?

190. why you need to test critical paths?

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Scan Insertion:

1).Explain scan insertion steps?

2).what are the basic things that needs to taken care for Scan Insertion?
3).what are the DRC Violations that u have faced during Scan Insertion and how did you fix
those ?
4).what is test point Insertion? Can you tell and explain one TestPoint Insertion scenario?
5).Some Questions on design complexity like what was the gate and flops count of yours
recent project?
6).Explain Decompression logic?
7).what is sdc file and what does it contains?
8).what is the use of clock gaters in design?
9).Draw the internal diagram of clock gating cell?
10).what is use of latch in clock gating cell?
11).How glitches can be remove through latch?
12).Draw the muxed flip flop and explain?
13).Take three scan flop and stitch it and explain the scan operation?
14).How you will decide the number of scan chains for your core?
15).what is lockup latch and why we use it?
16).what are Manufactured defects?
17).what is clock latency?
18).will latency effect data shifting in scan chain?
19).consider two flop of .2sec and 0.3 sec latency how do you connect the flops in scan
chain?
20).write the RTL coding for an asynchronous and a synchronous Flip-flop?
21).Implement a 2 by 1 Mux through gates?
22).How you will decide the compression ratio for the core?
23).what all information you will ask from designer for smooth scan insertion?
24).what all ctls you read while scan insertion?
25).Draw and explain the Structure of the compressor and decompressor circuit?
26).why we don't go for higher compression ratio like 90-100%?
27).How many scan clocks you had for your core?
28).which one is better having single or multiple scan clock?
29).what all things you need to take care while/before inserting on chip clock controller
circuit?
30).In which path we insert the lockkup latch, data or clock path?
31).How you will resolve the combinational feedback loop issue in design if present?
32).why we don't connect the capture flop's clock to the lockup latch?
33).why we use flop trays in design?
34).what is the purpose of DFT?
35).why we need scan? or why we convert normal D flip flops to scan flops in design?
36).what work around you can do if you don't have scan equivalent for some flops in design
while scan insertion?
ATPG:

37).Did you worked on Coverage Analysis? How did you improved your Coverage?
38).what are the ATPG Untestable faults?
39).How much test coverage you got in your last project?
40).what are the input files required for scan insertion and ATPG and what all output files we
get after completing scan insertion and ATPG?
41).what is Stuck at fault?
42).How many faults sites are there for a 2 input AND Gate?
43).what is the difference between transition and path delay fault model?
44).what the SPF/test procedure file contains?
45).what are the different types of fault classes?
46).what is fault collapsing?
47).For a given fault coverage the number of patterns for TFT is more than the patterns
generated for Stuck-at-faults. Why so?
48).How the 2 pulses are generated for transition faults?
49).can you draw the on chip clock controller structure diagram?
50).what all DRCs you faced during ATPG?
51).what is the difference between launch on capture(LOC) and launch on shift(LOS)?
52).which one is widely used in industry? which one is better LOS or LOC?
53).How you will improve transition faults test coverage?
54).why we do IDDQ testing?
55).what is pseudorandom pattern and why it called pseudorandom?
56).Have you ever seen condition statements in spf and how they work?
57).If we have cover all transition faults along a path(critical) already then should we check
the path delay also for that path?
58).what is the test coverage and fault coverage?
59).what is redundant fault explain with example?
60).what are parallel patterns how they work explain with the help of a scan chain?
61).what are the DRCs that can result in low test coverage?
62).what are blocked and unused faults?
63).How the test data valume and tester time reduction happens with compression?
64).what are advantages of modular atpg?
65).How DFT vectors are different from Functional vectors?
66).why we measure PO(primary output) before capture clock?
67).How the IDDQ test vectors is different from stuck at test vectors?
68).How increasing sequential depth helps in improving test coverage?

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========================

1. How do you implement DFT for a design have lot of Analog blocks? How to improve
coverage?
Ans: add feed-back, and need to control the analog input pins from digital core.

2. How do you test at-speed faults for inter clock domains?

Ans: try to have only one clock domain during scan.
3. What are the typical steps to improve coverage when our coverage target is not achieved?
Ans: analyze which sub-block has a low coverage, generaly add feed-back in scan mode, or
test point.

4. Steps to fix broken scan chain issues during ATPG? Step by step procedure to find the
issue?
Ans: check the scan mode is properly enable, the reset is stable state during shift, and the
clock is visible by all scan element during the shift.

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• What is LSSD and Mux-DFF?

• Draw a logic ciruit to detect a rising edge in an input signal.
• Explain how scan works.
• What are Launch Off Capture, Launch Off Shift ?
• What are mealey and moore state machines? advantages and
disadvantages.
• Explain boundary scan and tap controller.
• Design rule checks in ATPG (SCAN DRCs)
• Mismatch debug in ATPG.
• What is EDT logic and how does it work?
• How do the chains connect in EDTbypass mode? Compression ratio?
• How does the tester time reduce in EDT?
• Can you put just 1 flop in EDT mode chains and reduce the tester time to
just 1 shift??
• Patterns count increases if chain length is reduced. Y??
• What is LOC, LOS? How do they work? Waveforms??
• What is DFT ? what are its adv and disadv?
• Why delay increases if u use mux DFF?
• What happens to setup time of the DFF in Mux DFF??
• Some comb logic is given.. is that fully controllable and observable ??
• Some Sequential ckt.. Controllable and observable ?? what do you do to
make it become so??
• Parallel pattern mismatches? How did u debug?
• Lock up latch use?
• Positive and negative edge triggered flops.. how will u connect in a chain?
• JTAG TAP?
• Explain EDT logic. Decompressor, Compactor.
• Masking logic, Mask shift and hold regs.
• Compression ratio, EDT control signals – EDT update, EDT clock
• Fault aliasing, Masking bits generation – coverage effects.
• 2x1 MUX using NAND gates.
• Generate a Clock div by 2, with 25% duty cycle.
• To detect a fault in a circuit, what are the input test vectors to be given?
 • All Test Patterns for an 2-input AND gate (optimal set).
• Sequence detector, whole circuit.
• Setup time, Hold time problems.
• LOC, LOS differences.
• Scan chain diagnosis – serial pattern failing on Silicon, How do you
detect?
• ATPG DRC violations?
• Simulation mismatches debug.
• JTAG – Instructions – intest, extest, preload/sample.
• LOC, LOS – main difference.
• Scan chain connections, mux-DFF. (How is a scan chain is connected?)

• What is the need to do Timing simulations of ATPG patterns, even after

the timing is analysed completely?
• What is needed between two power domains, in the DFT perspective?
(level shifters?)
• Two different clock domains are there. How do you target the at-speed
faults?
• How do you improve fault coverage?
• What are the issues you've seen in simulations? (design bugs)
• Why do we need OCC?
• Why do we need EDT?
• How do you test multicycle paths at-speed?
• What happens if you don't specify any NCPs?
• What are EDT aborted faults?
• What is the significance of DFT?
• why atspeed coverage is low than S@ coverage?
• why is target coverage 90% at intel? and 99% at marvell?
• What is that hindering you from achieving more coverage?
• what are the issues you've faced in pattern simulations?
• AND gate - optimal input pattern set to detect all S@ faults.
• how to swap two numbers in C (using a single line of code)
• 2**300, 3**200 - which one is bigger?
• explain EDT logic.
• Simulation mismatches you have seen. how did you debug?
• LOC - LOS adv and disadv.
• EDTbypass is passing. EDT chain patterns are failing. What could be the
reasons?
• (lockup latches not present between edtclock, shiftclock.)
• Two subchips are there. Shifting power is huge. HOw to reduce power
dissipation?
• What are the options you have, without affecting coverage and test time?
(HW or SW options)
 • Setup vioations are there in your design. Which patterns would fail? (s@
or @speed?)
• Hold vioations are there. Which patterns would fail?
• -ve, +ve flops are connected, +ve, -ve flops are connected without lockup
latch.
• Which one is better in terms of setup and hold timing?
• Why do we need a lockup latch at all? what happens if we dont use it?
• Two flops will have the same values during shift. Whats the effect of it?
• JTAG : how do you connect tdi, tdo, tms, trst, from board level TAP to all
chips on the board.
• explain an algorithm for MBIST.
• Where do we use parallel testbench? Whats the use of parallel
simulations?
• TEstpoint? why do we need them?
• If you have simulations failures, what are the things you would look at?
• (setup, libs, clocks, what else?)
• In synthesis, if area is not meeting the target, what would you do?
• If some flops in two clock domains are failing, (S@ patterns), and those
failures are expected.
• HOw would you make them pass them on silicon? (no design changes are
allowed.)
• Atspeed coverage is always less than STUCK-at coverage. Why?
• P1500? are you aware of it?

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• What is the significance of scan-compression/EDT during ATPG?

To decrease the TDV and TAT
• What is the reason for increase in pattern count for compressed mode?
Because the chain lenght is small,more number of chains exist.More number of control bits to
identify faults in EDT.
• The actual compression achieved will be less than the specified compression factor.
Why?
Because of extra cycles(initialization cycles) in EDT.
• Deciding factors of scan design?
Number of channels on tester, memory available on channel and number of scan pins.
• Scan length, Scan chains, hierarchical scan concept?
• How scan chains are handled from a 3rd party IP in the chip?
By using "add subchain command"
• Use of LOCKUP latch?
a) When two clock domains exist , b) When one domain with different edges trigger the flops
,
c) When clock skew is more than half cycle of hold time.
• Difference between LOS and LOC?
Look for the basic differences in the guide.Other difference is that in LOS,there is a chance of
testing unrequired functional paths because of last shift is done when SE=1.
• Scan considerations required for At-speed test?
a) OCC that supports and generate 2 pulses for capture cycle.
b) Free running functional clocks.
• What are advantages of LOS and disadvantages when compared to LOC?
• How do you avoid limitations of LOS?
a) Consider SE as clock, b) Pipeline scan enable.
• How do we manage chain balancing and what is the requirement?
• Timing issues specific to scan chain clock domain mixing?
Hold issues.Use lockup latch to avoid them.Clock skew to be decreased.
• How to avoid hold issues when scan chain is stitched from +ve edge to –ve edge flop?
Use lockup latch.
• How asynchronous and synchronous resets are handled for scan?
Bypassing those resets with top reset.
• How tri-states are handled during scan?
That results in contention issues.Only one enable has to be activated at a time.
Configure the direction of a pad in scan mode.
• How bidirectional ports are handled during scan?
Configure bidi pads to a particular direction.Make it as output.
3.MBIST:
• Type of faults in memory to be detected?
SAF, AF, Couplinf faults,Bridging faults.
• How does a stuck @ fault is tested in memory cell location?
In memories, for example 8x1 RAM, write all 0's in 8 locations,then read 0's from bottom.
If it does not read 0 in that location we can say it is stuck at 1 and there is a failure.
• What is the consideration for at-speed faults to be detected for memory?
• Considerations for membist logic to be shared with multiple memories?
Ram size, type of memory, clock frequency, placement of memory.
• Sequence of 13N algorithm?
• Basic blocks present in BIST logic?
Data generator, address generator, bypass logic, scrambler and descrambler.
• Why BIST is preferred than a logic scan test?Why memories are not considered while in
ATPG?
• Diagnostics criteria for memories?
• What is the concept of repairable memories and how it is done?
• What are the faults specific to Multi-port memories?Port-Isolation Algorithm?
• How repairable information is fed out to repair the memory?
• How sharing of multiple memories is decided?
• Do we need to do a STA separately for MBIST mode? If so why?
Yes, because the controllers doesn't come into picture when STA is done in functional mode.
• What is the criterion for clock controllability for Memories during BIST?
Memory clock should be top clock, controller clock and memory clock should be same.
• How do you avoid setup time violations for at-speed MBIST?
• How hold violations are fixed for MBIST mode?
• How the placement considerations are determined with respect to memories?
4.ATPG:
• Concept of controllability and observability?
• What is the need for fault testing?
To check the testability of the design.
• Why functional tests are not sufficient for fault tests?
Functional tests are done to test the logic whereas DFT is done for testing manufacturing
defects.
• How a logical stuck-at fault is detected?
• Basic sequence of fault detection?
• Difference between combinational and sequential ATPG?
Combinational ATPG -> Single capture clock.
Sequential ATPG -> Multiple capture clock.
• Classes of fault types?
AU, DI, DS, UC, UO
For at-speed :- 0-1 transition, 1-0 transition faults.
• How to improve fault coverage or how do you analyze the fault coverage in the initial
runs?
By checking controllability and observability in the design and clearin the DRC's.
• What is the timing fixes that we need to do first (shift or capture)?
Shift. If there is any failure in capture we can mask but if shift sims fail we can do nothing.
• How a transition fault is detected in ATPG? Explain how launch and capture of a fault is
done and detected?
Initialization
Launch
Capture
** Why at-speed coverage is less compared to stuck-at?
Inter-clock domain testing is not possible in at-speed. In-to-Reg and Reg-to-Out paths are not
covered.
** Why scan shift testing cannot be done at higher frequency?
Because of Pads may not support high frequency and power consumption is more.
• Special considerations required for OCC type of transition fault detection?
• Why do we need path delay though sufficient transition coverage is achieved?
• What is the significance of SDD patterns over transition delay patterns?
• What is the concept of on-path and off-path during detection of paths?
• What is concept of reconvergence of paths during path-delay testing?
• How bridging faults are detected?
• Considerations for bridging faults?
• Special controllability requirements for IDDQ faults?
• How do we decide IDDQ strobe?
• Numbers of IDDQ strobes generally require?
• Why does an IDDQ pattern take lot of time for test, though pattern count is very small?
• How CGC faults are tested?
5.SIMUALTIONS:
• What kind of simulations do we generally need to do?
Chain serial and serial capture.
• Why do zero-delay/Unit delay simulations fail though timing simulations are passing?
Simulator issues.
• Problems generally encountered during ATPG simulations?
Hold issues.
• What is the need of simulations though STA is clean?
• How does synchronizing paths are handled

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