Module Lesson

8 40
Testing of Embedded Built-In-Self-Test (BIST)
System for Embedded Systems
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Instructional Objectives and the test responses are evaluated by a output response compactor. In the most common type
of BIST, test responses are compacted in output response compactor to form (fault) signatures.
After going through this lesson the student would be able to The response signatures are compared with reference golden signatures generated or stored on-
chip, and the error signal indicates whether chip is good or faulty.
x Explain the meaning of the term ‘Built-in Self-Test (BIST)’ Four primary parameters must be considered in developing a BIST methodology for embedded
x Identify the main components of BIST functionality systems; these correspond with the design parameters for on-line testing techniques discussed in
earlier chapter [2].
x Describe the various methods of test pattern generation for designing embedded systems
with BIST ƒ Fault coverage: This is the fraction of faults of interest that can be exposed by the test
x Define what is a Signature Analysis Register and describe some methods to designing patterns produced by pattern generator and detected by output response monitor. In
such units presence of input bit stream errors there is a chance that the computed signature matches
the golden signature, and the circuit is reported as fault free. This undesirable property is
x Explain what is a Built-in Logic Block Observer (BILBO) and describe how to use this called masking or aliasing.
block for designing BIST ƒ Test set size: This is the number of test patterns produced by the test generator, and is
closely linked to fault coverage: generally, large test sets imply high fault coverage.
Built-In-Self-Test (BIST) for Embedded Systems ƒ Hardware overhead: The extra hardware required for BIST is considered to be overhead.
In most embedded systems, high hardware overhead is not acceptable.
1. Introduction ƒ Performance overhead: This refers to the impact of BIST hardware on normal circuit
performance such as its worst-case (critical) path delays. Overhead of this type is
sometimes more important than hardware overhead.
BIST is a design-for-testability technique that places the testing functions physically with the
circuit under test (CUT), as illustrated in Figure 40.1 [1]. The basic BIST architecture requires
the addition of three hardware blocks to a digital circuit: a test pattern generator, a response Issues for BIST
analyzer, and a test controller. The test pattern generator generates the test patterns for the CUT.
Examples of pattern generators are a ROM with stored patterns, a counter, and a linear feedback ƒ Area Overhead: Additional active area due to test controller, pattern generator, response
shift register (LFSR). A typical response analyzer is a comparator with stored responses or an evaluator and testing of BIST hardware.
LFSR used as a signature analyzer. It compacts and analyzes the test responses to determine ƒ Pin Overhead: At least 1 additional pin is needed to activate BIST operation. Input MUX
correctness of the CUT. A test control block is necessary to activate the test and analyze the adds extra pin overheads.
responses. However, in general, several test-related functions can be executed through a test ƒ Performance overhead: Extra path delays are added due to BIST.
controller circuit. ƒ Yield loss increases due to increased chip area.
ƒ Design effort and time increases due to design BIST.
Test ƒ The BIST hardware complexity increases when the BIST hardware is made testable.
Test Controller
ROM Benefits of BIST
Reference
Signature ƒ It reduces testing and maintenance cost, as it requires simpler and less expensive ATE.
M ƒ BIST significantly reduces cost of automatic test pattern generation (ATPG).
Hard ware Output
pattern generator U CUT Comparator ƒ It reduces storage and maintenance of test patterns.
Response
X Compactor ƒ It can test many units in parallel.
ƒ It takes shorter test application times.
PO ƒ It can test at functional system speed.
Good/Faulty
Signature BIST can be used for non-concurrent, on-line testing of the logic and memory parts of a system
[2]. It can readily be configured for event-triggered testing, in which case, the BIST control can
Fig. 40.1 A Typical BIST Architecture be tied to the system reset so that testing occurs during system start-up or shutdown. BIST can
As shown in Figure 40.1, the wires from primary inputs (PIs) to MUX and wires from circuit also be designed for periodic testing with low fault latency. This requires incorporating a testing
output to primary outputs (POs) cannot be tested by BIST. In normal operation, the CUT process into the CUT that guarantees the detection of all target faults within a fixed time.
receives its inputs from other modules and performs the function for which it was designed. On-line BIST is usually implemented with the twin goals of complete fault coverage and low
During test mode, a test pattern generator circuit applies a sequence of test patterns to the CUT, fault latency. Hence, the test generation (TG) and response monitor (RM) are generally designed

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to guarantee coverage of specific fault models, minimum hardware overhead, and reasonable set 2.2 Exhaustive patterns
size. These goals are met by different techniques in different parts of the system.
TG and RM are often implemented by simple, counter-like circuits, especially linear-feedback Exhaustive pattern BIST eliminates the test generation process and has very high fault coverage.
shift registers (LFSRs) [3]. The LFSR is simply a shift register formed from standard flip-flops, To test an n-input block of combinational logic, it applies all possible 2n-input patterns to the
with the outputs of selected flip-flops being fed back (modulo-2) to the shift register’s inputs. block. Even with high clock speeds, the time required to apply the patterns may make exhaustive
When used as a TG, an LFSR is set to cycle rapidly through a large number of its states. These pattern BIST impractical for a circuit with n>20.
states, whose choice and order depend on the design parameters of the LFSR, define the test
patterns. In this mode of operation, an LFSR is seen as a source of (pseudo) random tests that
are, in principle, applicable to any fault and circuit types. An LFSR can also serve as an RM by
counting (in a special sense) the responses produced by the tests. An LFSR RM’s final contents DQ1 DQ2 DQ3
after applying a sequence of test responses forms a fault signature, which can be compared to a
known or generated good signature, to see if a fault is present. Ensuring that the fault coverage is
sufficiently high and the number of tests is sufficiently low are the main problems with random
BIST methods. Two general approaches have been proposed to preserve the cost advantages of
LFSRs while making the generated test sequence much shorter. Test points can be inserted in the Clock
CUT to improve controllability and observability; however, they can also result in performance
loss. Alternatively, some determinism can be introduced into the generated test sequence, for
Reset Q1
example, by inserting specific “seed” tests that are known to detect hard faults. Q2 Q3

A typical BIST architecture using LFSR is shown in Figure 40.2 [4]. Since the output patterns of Fig. 40.3 Exhaustive pattern generator
the LFSR are time-shifted and repeated, they become correlated; this reduces the effectiveness of
the fault detection. Therefore a phase shifter (a network of XOR gates) is often used to 2.3 Pseudo-exhaustive patterns
decorrelate the output patterns of the LFSR. The response of the CUT is usually compacted by a
multiple input shift register (MISR) to a small signature, which is compared with a known fault- In pseudo-exhaustive pattern generation, the circuit is partitioned into several smaller sub-
free signature to determine whether the CUT is faulty. circuits based on the output cones of influence, possibly overlapping blocks with fewer than n
inputs. Then all possible test patterns are exhaustively applied to each sub-circuit. The main goal
of pseudo-exhaustive test is to obtain the same fault coverage as the exhaustive testing and, at the
Scan chain 1 (/bits) same time, minimize the testing time. Since close to 100% fault coverage is guaranteed, there is
no need for fault simulation for exhaustive testing and pseudo-exhaustive testing. However,
LFSR Phase Scan chain 2 (/bits) MISR such a method requires extra design effort to partition the circuits into pseudo-exhaustive testable
.
shifter . sub-circuits. Moreover, the delivery of test patterns and test responses is also a major
. .
. consideration. The added hardware may also increase the overhead and decrease the
. performance.
Scan chain n (/bits)

Fig. 40.2 A generic BIST architecture based on an LFSR, an MISR, and a phase shifter
X1
Five-Bit
X2 2
Binary h
2. BIST Test Pattern Generation Techniques Counter X3 6
1 3
0 for Counter 1 2-Bit X4
2.1 Stored patterns 1 for Counter 2
2-1 X5
MUX
1
X6 4
Five-Bit f
An automatic test pattern generation (ATPG) and fault simulation technique is used to generate Binary X7 7
the test patterns. A good test pattern set is stored in a ROM on the chip. When BIST is activated, Counter X8 5
test patterns are applied to the CUT and the responses are compared with the corresponding 2
stored patterns. Although stored-pattern BIST can provide excellent fault coverage, it has limited
applicability due to its high area overhead.
Fig. 40.4 Pseudo-exhaustive pattern generator

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Circuit partitioning for pseudo-exhaustive pattern generation can be done by cone segmentation
as shown in Figure 40.4. Here, a cone is defined as the fan-ins of an output pin. If the size of the
largest cone in K, the patterns must have the property to guarantee that the patterns applied to
any K inputs must contain all possible combinations. In Figure 40.4, the total circuit is divided
into two cones based on the cones of influence. For cone 1 the PO h is influenced by X1, X2, X3,
hn-1 hn-2 h2 h1
X4 and X5 while PO f is influenced by inputs X4, X5, X6, X7 and X8. Therefore the total test
pattern needed for exhaustive testing of cone 1 and cone 2 is (25 +25) = 64. But the original D Q D Q D Q D Q
n-1 n-2
circuit with 8 inputs requires 28 = 256 test patterns exhaustive test. x x x 1
Xn-1 Xn-2 X1 X0
2.4 Pseudo-Random Pattern Generation Clock
A string of 0’s and 1’s is called a pseudo-random binary sequence when the bits appear to be Fig. 40.6 n-stage LFSR implementation with actual digital circuit
random in the local sense, but they are in someway repeatable. The linear feedback shift register
(LFSR) pattern generator is most commonly used for pseudo-random pattern generation. In 2.5 Pattern Generation by Counter
general, this requires more patterns than deterministic ATPG, but less than the exhaustive test. In
contrast with other methods, pseudo-random pattern BIST may require a long test time and In a BIST pattern generator based on a folding counter, the properties of the folding counter are
necessitate evaluation of fault coverage by fault simulation. This pattern type, however, has the exploited to find the seeds needed to cover the given set of deterministic patterns. Width
potential for lower hardware and performance overheads and less design effort than the compression is combined with reseeding to reduce the hardware overhead. In a two-dimensional
preceding methods. In pseudorandom test patterns, each bit has an approximately equal test data compression technique an LFSR and a folding counter are combined for scan-based
probability of being a 0 or a 1. The number of patterns applied is typically of the order of 103 to BIST. LFSR reseeding is used to reduce the number of bits to be stored for each pattern
107 and is related to the circuit's testability and the fault coverage required. (horizontal compression) and folding counter reseeding is used to reduce the number of patterns
(vertical compression).
Linear feedback shift register reseeding [5] is an example of a BIST technique that is based on
controlling the LFSR state. LFSR reseeding may be static, that is LFSR stops generating patterns
while loading seeds, or dynamic, that is, test generation and seed loading can proceed 2.6 Weighted Pseudo-random Pattern Generation
simultaneously. The length of the seed can be either equal to the size of the LFSR (full
reseeding) or less than the LFSR (partial reseeding). In [5], a dynamic reseeding technique that Bit-flipping [9], bit-fixing, and weighted random BIST [1,8] are example of techniques that rely
allows partial reseeding is proposed to encode test vectors. A set of linear equations is solved to on altering the patterns generated by LFSR to embed deterministic test cubes. A hybrid between
obtain the seeds, and test vectors are ordered to facilitate the solution of this set of linear pseudorandom and stored-pattern BIST, weighted pseudorandom pattern BIST is effective for
equations. dealing with hard-to-detect faults. In a pseudorandom test, each input bit has a probability of 1/2
of being either a 0 or a 1. In a weighted pseudorandom test, the probabilities, or input weights,
can differ. The essence of weighted pseudorandom testing is to bias the probabilities of the input
bits so that the tests needed for hard-to-detect faults are more likely to occur. One approach uses
software that determines a single or multiple weight set based on a probabilistic analysis of the
hn-1 hn-2 h2 h1 hard-to detect faults. Another approach uses a heuristic-based initial weight set followed by
additional weight sets produced with the help of an ATPG system. The weights are either
D FF D FF D FF D FF realized by logic or stored in on-chip ROM. With these techniques, researchers obtained fault
coverage over 98% for 10 designs, which is the same as the coverage of deterministic test
Xn-1 Xn-2 X1 X0
vectors.
Fig. 40.5 Standard Linear Feedback Shift Register
In hybrid BIST method based on weighted pseudorandom testing, a weight of 0, 1, or ȝ
Figure 40.5 shows a standard, external exclusive-OR linear feedback shift register. There are n (unbiased) is assigned to each scan chain in CUT. The weight sets are compressed and stored on
flip-flops (Xn-1,……X0) and this is called n-stage LFSR. It can be a near-exhaustive test pattern the tester. During test application, an on-chip lookup table is used to decompress the data from
generator as it cycles through 2n-1 states excluding all 0 states. This is known as a maximal the tester and generate weight sets. In order to reduce the hardware overhead, scan cells are
length LFSR. Figure 40.6 shows the implementation of a n-stage LFSR with actual digital carefully reordered and a special ATPG approach is used to generate suitable test cubes.
circuit. [1]

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 0 0
DQ DQ DQ DQ DQ DQ DQ DQ Fca Fca Fca Fca Fca Fca
X7 X6 X5 X4 X3 X2 X1 X0

D DD D D D D
Q QQ Q Q Q Q

Weight W1 1/16 1/8 1/4 1/2

select W2 1 of 4 MUX (a) CA with null boundary conditions

Inversion
Fig. 40.7 Weighted pseudo-random pattern generator
Fca Fca Fca Fca Fca Fca

LFSR 0 D DD D D D D
0 Q QQ Q Q Q Q
123 193 61 114 228 92 25
(b) CA with null cyclic boundary conditions
Fig. 40.9 The structure of cellular automata
D D D D D D D
Q Q Q Q Q Q Q In addition to an LFSR, a straightforward way to compress the test response data and produce a
fault signature is to use an FSM or an accumulator. However, the FSM hardware overhead and
accumulator aliasing are difficult parameters to control. Keeping the hardware overhead
1/8 3/4 1/2 7/8 1/2 0.8 0.6 0.8 0.4 0.5 0.3 0.3 acceptably low and reducing aliasing are the main difficulty in RM design.
(a) (b)

Fig. 40.8 weighted pseudorandom patterns.

2.9 Comparison of Test Generation Strategies

Figure 40.7 shows a weighted pseudo-random pattern generator implemented with Implementing a BIST strategy, the main issues are fault coverage, hardware overhead, test time
programmable probabilities of generating zeros and ones at the PIs. As we know, LFSR overhead, and design effort. These four issues have very complicated relationship. Table 1
generates pattern with equal probability of 1s and 0s. As shown in Figure 40.8 (a), if a 3-input summarizes the characteristics of the test strategies mentioned earlier based on the four issues.
AND gate is used, the probability of 1s becomes 0.125. If a 2-input OR gate is used, the Table 7.1 Comparison of different test strategies
probability becomes 0.75. Second, one can use cellular automata to produce patterns of desired
weights as shown in Figure 40.8(b). Test Generation Fault Hardware Test Time Design
Methodology Coverage Overhead Overhead Effort
2.7 Cellular Automata for Pattern Generation Stored Pattern High High Short Large
Cellular automata are excellent for pattern generation, because they have a better randomness Exhaustive High Low Long Small
distribution than LFSRs. There is no shift induced bit value correlation. A cellular automaton is a Pseudo-exhaustive High High Medium Large
collection of cells with regular connections. Each pattern generator cell has few logic gates, a
flip-flop and is connected only to its local neighbors. If Ci is the state of the current CA cell, Ci+1 Pseudo-random Low Low Long Small
and Ci-1 are the states of its neighboring cells. The next state of cell Ci is determined by (Ci-1, Ci , Weighted Pseudo-random Medium Medium Long Medium
and Ci+1). The cell is replicated to produce cellular automaton. The two commonly used CA
structures are shown in Figure 40.9. 3. BIST Response Compression/Compaction Techniques
During BIST, large amount of data in CUT responses are applied to Response Monitor (RM).
For example, if we consider a circuit of 200 outputs and if we want to generate 5 million random

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patterns, then the CUT response to RM will be 1 billion bits. This is not manageable in practice. 3.1 Ones Count
So it is necessary to compact this enormous amount of circuit responses to a manageable size
that can be stored on the chip. The response analyzer compresses a very long test response into a The number of ones in the CUT output response is counted. In this method the number of ones is
single word. Such a word is called a signature. The signature is then compared with the prestored the signature. It requires a simple counter to accomplish the goal. Figure 40.10 shows the test
golden signature obtained from the fault-free responses using the same compression mechanism. structure of ones count for a single output CUT. For multiple output ones, a counter for each
If the signature matches the golden copy, the CUT is regarded fault-free. Otherwise, it is faulty. output or one output at a time with the same input sequence can be used. Input test sequence can
There are different response analysis methods such as ones count, transition count, syndrome be permuted without changing the count.
count, and signature analysis.
Compression: A reversible process used to reduce the size of the response. It is difficult in hard
ware.
Test
Compaction: An irreversible (lossy) process used to reduce the size of the response. CUT
Pattern
a) Parity compression: It computes the parity of a bit stream.
b) Syndrome: It counts the number of 1’s in the bit stream. Clock Counter
c) Transition count: It counts the number of times 0ĺ1 and 1ĺ0 condition occur in the
bit stream. Fig. 40.10 Ones count compression circuit structure
d) Cyclic Redundancy Check (CRC): It is also called signature. It computes CRC check
word on the bit stream.
For N-bit test length with r ones the masking probability is shown as follows:
Signature analysis – Compact good machine response into good machine signature. Actual §N·
Number of masking sequences = ¨ ¸  1
signature generated during testing, and compared with good machine signature. r © ¹
Aliasing: Compression is like a function that maps a large input space (the response) into a small 2N possible output sequences with only one fault free.
output space (signature). It is a many-to-one mapping. Errors may occur in the in the input bit
stream. Therefore, a faulty response may have the signature that matches the to the golden § N·
signature and the circuit is reported as the fault-free one. Such a situation is referred as the ¨ ¸
© r ¹ # S N 1 2
P(M )  
 2N 1
aliasing or masking. The aliasing probability is the possibility that a faulty response is treated as The masking probabilities:
fault-free. It is defined as follows:
Let us assume that the possible input patterns are uniformly distributed over the possible mapped It has low masking probability for very small and very large r. It always detects odd number of
signature values. There are 2m input patterns, 2r signatures and 2n-r input patterns map into given errors and it may detect even number of errors.
signature. Then the aliasing or masking probability

P(M)=
Number of erroneos input that map into the golden signature 3.2 Transition Count
Number of faulty input responses
It is very similar to ones count technique. In this method the number of transitions in the CUT
2 m-r -1 response, zero to one and/or one to zero is counted. Figure 40.11 shows a test structure of
=
2 m -1 transition counting. It has simple hardware DFF with EXOR to detect a transition and counter to
2 m-r count number of transitions. It has less aliasing probability than ones counting. Test sequences
| m for large m cannot be permuted. Permutation of input sequences will change the number of transitions. On
2 the other hand, one can reorder the test sequence to maximize or minimize the transitions, hence,
1 minimize the aliasing probability.
= r
2
The aliasing probability is the major considerations in response analysis. Due to the n-to-1
mapping property of the compression, it is unlikely to do diagnosis after compression. Therefore,
the diagnosis resoluation is very poor after compression. In addition to the aliasing probability,
hardware overhead and hardware compatibility are also important issues. Here, hardware
compatibility is referred to how well the BIST hardware can be incorporated in the CUT or DFT.

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 The originally design of syndrome test applies exhaustive patterns. Hence, the syndrome is
DFF S K / 2 n , where n is the number of inputs and K is the number of minterms. A circuit is
Test syndrome testable if all single stuck-at faults are syndrome detectable. The interesting part of
CUT
Pattern syndrome testing is that any function can be designed as being syndrome testable.

3.4 LFSR Structure

Clock Counter
ƒ External and internal type LFSR is used. Both types use D type flip-flop and exclusive-
Fig. 40.11 Transition count compression circuit structure OR logic as shown in Figure 40.13.
ƒ In external type LFSR, XOR gates are placed outside the shift path. It is also called type 1
For N-bit test length with r transitions the masking probability is shown as follows: LFSR [1].
For the test length of N, there are N-1 transitions. ƒ In internal type LFSRs, also called type 2 LFSR, XOR gates are placed in between the
flip-flops.
§N·
Number of masking sequences = ¨ ¸  1
©r¹ (a) External Type (b) Internal Type
§ N  1·
Hence, ¨ ¸ is the number of sequences that has r transitions.
© r ¹ D3 D2 D1 D0 D3 D2 D1 D0
Since the first output can be either one or zero, therefore, the total number must be multiplied by
§ N  1· Fig. 40.13 Two types of LFSR
2. Therefore total number of sequences with same transition counts : 2 ¨ ¸ . Again, only one
© r ¹
of them is fault-free. One of the most important properties of LFSRs is their recurrence relationship. The recurrence
relation guarantees that the states of a LFSR are repeated in a certain order. For a given sequence
§ N 1· of numbers a0, a1, a2,…………an,…….. We can define a generating function:
2¨ ¸ 1 G(x) = a0 + a1x + a2x2 + …………+ amxm + ……
© 2 ¹
# S N
1 2 D
P(M) ¦a
 2N 1
Masking probabilities: = m xm
m 0

^am ` ^a0 , a1 , a2 ,......`

3.3 Syndrome Testing where ai 1or 0 depending on the out put stage and time ti .
Syndrome is defined as the probability of ones of the CUT output response. The syndrome is 1/8 The initial states are a-n, a-n+1,…….,a-2, a-1. The recurrent relation defining {am}is
n
for a 3-input AND gate and 7/8 for a 3-input OR gate if the inputs has equal probability of ones
and zeros. Figure 40.12 shows a BIST circuit structure for the syndrome count. It is very similar
am ¦c a
i 1
i m i

to ones count and transition count. The difference is that the final count is divided by the number where ci 0, means output is not fed back
of patterns being applied. The most distinguished feature of syndrome testing is that the
syndrome is independent of the implementation. It is solely determined by its function of the 1, otherwise
circuit.

random
test CUT
pattern

Clock Syndrome Counter

Counter
Syndrome
Fig. 40.12 Syndrome testing circuit structure
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 D n ƒ Any divisor polynomial G(x) with two or more non-zero coefficients will detect all
G  x ¦¦c a
m 0 i 1
i m i xm single-bit errors.
n D

¦c x ¦a
i 1
i
i

m 0
m i xm 3.6 Multiple-Input Signature Register (MISR)
D ƒ The problem with ordinary LFSR response compacter is too much hardware overhead if
n
ª mº
¦c x
i 1
i
i
« a i x  ....  a1 x  ¦ am x »
¬
i 1

m 0 ¼ ƒ
one of these is put on each primary output (PO).
Multiole-input signature register (MISR) is the solution that compacts all outputs into one
LFSR. It works because LFSR is linear and obeys superposition principle.
¦ c x a 
n
1
i
i
i x  ....  a1 x
i
ƒ All responses are superimposed in one LFSR. The final remainder is XOR sum of
G  x i 1
n
remainders of polynomial divisions of each PO by the characteristic polynomial.
1  ¦ ci x i Golden
i 1 signature
G(x) has been expressed in terms of the initial state and the feedback coefficients. The m
n
denominator of the polynomial G(x), f  x  1  ¦ ci x i is called the characteristic polynomial of
L C M
i 1
F U I Signature
. .
the LFSR. S T S Analyzer
. .
R R
. .
3.5 LFSR for Response Compaction: Signature Analysis
Si(x)
ƒ It uses cyclic redundancy check code (CRCC) generator (LFSR) for response compacter Test Response
ƒ In this method, data bits from circuit Pos to be compacted as a decreasing order patterns Ri(x)
coefficient polynomial
ƒ CRCC divides the PO polynomial by its characteristic polynomial that leaves remainder Fig. 40.15 Multiple input signature register
of division in LFSR. LFSR must be initialized to seed value (usually 0) before testing.
Figure 40.15 illustrates a m-stage MISR. After test cycle i, the test responses are stable on CUT
ƒ After testing, signature in LFSR is compared to known good machine signature
outputs, but the shifting clock has not yet been applied.
For an output sequence of length N, there is a total of 2N-1 faulty sequence. Let the input Ri(x)= (m-1)th polynomial representing the test responses after test cycle i.
sequence is represented as P(x) as P(x)=Q(X)G(x)+R(x). G(x) is the characteristic polynomial; Si(x)=polynomial representing the state of the MISR after test cycle i.
Q(x) is the quotient; and R(x) is the remainder or signature. For those aliasing faulty sequence, Ri  x  ri , m 1 x m 1  ri ,m  2 x m  2  ........  ri ,1 x  ri ,0
the remainder R(x) will be the same as the fault-free one. Since, P(x) is of order N and G(x) is of
Si  x  Si , m 1 x m 1  Si ,m  2 x m  2  ........  Si ,1 x  Si ,0
order r, hence Q(x) has an order of N-r. Hence, there are 2N-r possible Q(x) or P(x). One of them
is fault-free. Therefore, the aliasing probability is shown as follows: Si 1  x  ª¬ Ri  x   xSi  x  º¼ mod G  x 
2N r 1 r G  x  is the characteristic polynomial
P(M ) # 2 for large N. Masking probabilities is independent of input sequence.
2N 1 Assume initial state of MISR is 0. So,
Figure 40.14 illustrates a modular LFSR as a response compactor. S0  x  0
Characteristics Polynomial x5 + x3 + x + 1 S1  x  ¬ª R0  x   xS0  x  ¼º mod G  x  R0  x 
S2  x  ª¬ R1  x   xS1  x  º¼ mod G  x  ª¬ R1  x   R0  x  º¼ mod G  x 
01010001 D Q D Q D Q D Q D Q
x3 .
1 x x2 x4
.
CLOCK Sn  x  ¬ª x R0  x   x R1  x   .......  xRn  2  x   Rn 1  x  ¼º mod G  x 
n 1 n2

X0 X1 X3 X4 This is the signature left in MISR after n patterns are applied. Let us consider a n-bit response
X2
compactor with m-bit error polynomial. Then the error polynomial is of (m+n-2) degree that
Fig. 40.14 Modular LFSR as a response compactor
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gives (2m+n-1-1) non-zero values. G(x) has 2n-1-1 nonzero multiples that result m polynomials of B1 D1 D2 Dn-1 Dn
degree <=m+n-2.
2n1  1 B2
P( M )
Probability of masking 2m n 1  1
1 MUX
| m S1 0 DQ DQ DQ D Q SO
2 Clock 1 C C C C

3.7 Logic BIST Architecture Q1 Q2 Qn-1 Qn

Fig. 40.17 BILBO Example
ƒ Test-per-clock system
x More hardware, less test time.
x BILBO: Built in logic bloc observer
Four different modes of BILBO operation
ƒ Test-per-scan system. (a) Scan-in-Scan-out: shift register
x Less hardware, more test time. (b) Normal register mode: PIPO register
x STUMPS: Self-Test using a MISR and Parallel Shift register. (c) Pattern generator mode: LFSR
ƒ Circular self-test path (d) Response compactor mode: MISR
x Lowest hardware, lowest fault coverage.
3.7.3 BILBO Usage for multi-CUT structure [1]
3.7.1 Test-Per-Clock BIST
As shown in Figure 40.18, in this BILBO structure, multiple modules can be tested
Two different test-per-clock BIST structures are shown in Figure 40.16. For every test clock, simultaneously. The total operation is done in two phase as stated below.
LFSR generates a test vector and Signature Analyzer (MISR) compresses a response vector. In
every clock period some new set of faults is tested. This system requires more hardware. It takes B B
less test time. It can be used for exhaustive test, pseudo-exhaustive test, pseudorandom testing, L C I C I C M
F U L U L U I
and weight pseudorandom testing. T T T S
S B B
R A O B O C R
LFSR 1 2
LFSR Shift Register
(a) Example test configuration.

Fig. 40.18 Circuit configured with BILBO

CUT CUT
Phase 1
In this mode of operation BILBO1 operates in MISR mode and BILBO2 operates in LFSR
MISR MISR mode. CUT A and CUT C are tested in parallel.
Phase 2
Fig. 40.16 Test-Per-Clock BIST structure In this of operation BILBO1 operates in LFSR mode and BILBO2 operates in MISR mode. Only
CUT B is tested in this mode of operation.
3.7.2 Built-in Logic Block Observer (BILBO)[1]
3.7.4 Test-Per-Scan BIST
Built-in logic block observation is a well known approach for pipelined architecture. It adds
some extra hardware to the existing registers (D flip-flop, pattern generator, response Instead of using LFSR and MISR for every input/output pins, this approach combine
compacter, & scan chain) to make them multifunctional. All FFs are reset to 0. The circuit LFSR/MISR with shift register to minimize the hardware overhead. Figure 40.19 shows the basic
diagram of a BILBO module is shown in Figure 40.17. The BILBO has two control signals (B1 circuit structure of a test-per-scan BIST. In BIST mode, LFSR generates test vectors and shifted
and B2). to the inputs of the CUT via scan register. At the same time, the response are scanned in and
compressed by the LFSR. Due to the use of scan chain for the delivery of test patterns and

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responses, the test speed is much slower than the test-per-clock approach. The clocks required 4. BIST for Structured Circuits
for a test cycle is the maximal of the scan stages of input and output scan registers. Also fall in
this category include CEBS, LOCST, and STUMP. Structured design techniques are the keys to the high integration of VLSI circuits. The structured
circuits include read only memories (ROM), random access memories (RAM), programmable
SI SI
LFSR Scan Register SRI LFSR Scan Register SRI logic array (PLA), and many others. In this section, we would like to focus on PLAs because
they are tightly coupled with the logic circuits. While, memories are usually categorized as
different category. Due to the regularity of the structure and the simplicity of the design, PLAs
are commonly used in digital systems. PLAs are efficient and effective for the implementation of
CUT CUT arbitrary logic functions, combinational or sequential. Therefore, in this section, we would like to
discuss the BIST for PLAs.
SO SO A PLA is conceptually a two level AND-OR structure realization of Boolean function. Figure
MISR Scan Register SRO MISR Scan Register SRO 40.21 shows a general structure of a PLA. A PLA typically consists of three parts, input
decoders, the AND plane, the OR plane, and the output buffer. The input decoders are usually
implemented as single-bit decoders which produce the direct and the complement form of inputs.
(a) Simple system (b) Alternative system
The AND plane is used to generate all the product terms. The OR plane sum the required product
Fig. 40.19 Basic test-per-scan structure terms to form the output bits. In the physical implementation, they are implemented as NAND-
NAND or NOR-NOR structure.
3.7.5 Self-Testing Using MISR and Parallel Shift register
sequence generator (STUMP)
The architecture of the self-testing using MISR and parallel SRSG (STUMP) is shown in AND Plane OR Plane
product
Figure 40.20. Instead of using only one scan chain, it uses multiple scan chains to minimize the First NOR Plane lines Second NOR Plane
.
test time. Since the scan chains may have different lengths, the LFSR runs for N cycles (the
.
length of the longest scan chain) to load all the chains. For such a design, the internal type LFSR
is preferred. If the external type is used, the difference between two LFSR output bits is only the ... ...
time shift. Hence, the correlation between two scan chains can be very high. Input Decoders Output Buffers
... ...
Pseudo-Random Test Pattern Generator PLA Inputs PLA Outputs
Fig. 40.21 A general structure of a PLA.

Input Phase Shifting Network As mentioned earlier in the fault model section, PLAs has the following faults, stuck-at faults,
bridging faults, and crosspoint faults. Test generation for PLAs is more difficult than that for the
conventional logic. This is because that PLAs have more complicated fault models. Further, a
SR SR typical PLA may have as many as 50 inputs, 67 inputs, and 190 product terms [10-11].
SR1 CUT SR2 n-1 CUT n Functional testing of such PLAs can be a difficult task. PLAs often contain unintentional and
unidentifiable redundancy which might cause fault masking. Further more, PLAs are often
embedded in the logic which complicates the test application and response observation.
MISR Therefore, many people proposed the use of BIST to handle the test of PLAs.

Fig. 40.20 STUMPS test-per-scan testing system 5. BIST Applications

Test Procedure of STUMP Manufactures are increasingly employing BIST in real products. Examples of such applications
1. Scan in patterns from LFSR to all scan chain. are given to illustrate the use of BIST in semiconductor, communications, and computer
2. Switch to normal function mode and apply one clock. industrial.
3. Scan out chains into MISR.
4. Overlap steps 1 and 3.
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5.1 Exhaustive Test in the Intel 80386 [12] [5] C. V. Krishna, A. Jalas, and N. A. Tauba, “Test vector encoding using partial LFSR
reseeding”, in Proceeding of the International Test Conference, pp. 885-893, 2001.
Intel 80386 has BIST logic for the exhaustive test of three control PLAs and three control [6] J. Rajski, J. Tyszer, and N. Zacharia, “Test data decompression for multiple scan designs
ROMs. For PLAs, the exhaustive patterns are generated by LFSRs embedded in the input with boundary scan”, IEEE Transactions on Computers, 47, pp. 1188-1200, 1998.
registers. For ROMs, the patterns are generated by the microprogram counter which is part of the [7] N. A. Tauba and E.J.MaCluskey, “Altering a pseudo-random bit sequence for scan
normal logic. The largest PLA has 19 input bits. Hence, the test length is 512K clock cycles. The based”, in Proceedings of International Test Conference, 1996, pp. 167-175.
test responses are compressed by MISRs at the outputs. The contents of MISRs are continuously [8] S. Wang, “Low hardware overhead scan based 3-weight weighted random BIST”, in
shifted out to an LFSR. At the end of testing, the contents of LFSRs are compared. Proceedings of International Test Conference, 2001, pp. 868-877.
[9] H. –J. Wunderlich and G.Kiefer, “Bit-flipping BIST”, in Proceedings of International
Conference on Computer-Aided Design, 1996, pp. 337-343.
5.2 Pseudorandom Test in the IBM RISC/6000 [13] [10] C.Y. Liu, K.K Saluja, and J.S. Ypadhyaya, “BIST-PLA: A Built-in Self-Test Design of
Large Programmable Logic Arrays,” Proc. 24th Design Automation Conf., June 1987, pp.
The RISC/6000 has extensive BIST structure to cover the entire system. In accord with 385-391.
their tradition, RISC/6000 has full serial scan. Hence, the BIST it uses is the pseudorandom [11] C.Y.Liu and K.K.Saluja, “Built -In Self-Test Techniques for Programmable logic
testing in the form of STUMPS. For embedded RAMs, it performs self-test and delay testing. For Arrays,” in VLSI Fault Modeling and Testing Techniques, G. W. Zobrist,ed., Ablex
the BIST, it has a on chip processor (COP) on each chip. In COP, there are an LFSR for pattern Publishing, Norwood, N.J.,1993.
generation, a MISR for response compression, and a counter for address counting in RAM bist. [12] P. Gelsinger, “Design and Test of the 80386,” IEEE Design & Test of Computers, Vol. 4,
The COP counts for less than 3% of the chip area. No. 3, June 1987, pp.42-50.
[13] I.M. Ratiu and H.B. Bakouglu, “Pseudorandom Built-In Self-Test Methodology and
5.3 Embedded Cache Memories BIST of MC68060 [14] implementation for the IBM RISC System/6000 Processor,” IBM J. Research and
Development, Vol. 34. 1990, pp.78-84.
MC68060 has two test approaches for embedded memories. First it has adhoc direct memory [14] A.L. Crouch, M. Pressly, J. Circello, “Testability Features of the MC68060
access for manufacturing testing because it has the only memory approach that meets all the Microprocessor,” Proc. Int’l Test Conf., 1994, pp. 60-69.
design goals. The adhoc direct memory acess uses additional logic to make address, data in, data [15] J. Broseghini and D.H. Lenhert, “An ALU-Based Programmable MISR/Pseudorandom
out, and control line for each memory accessible through package pins. An additional set of Generator for a MC68HC11 Family Self-Test,” Proc. Int’l Test Conf., 1993, pp. 349-358.
control signals selects which memory is activated. The approach makes each memory visible
through the chip pins as though it is a stand-alone memory array. For the burn-in test, it builds Problems
the BIST hardware around the adhoc test logic. The two-scheme approach is used because it
meets the burn-in requirements with little additional logic. 1. What is Built-In-Self-Test? Discuss the issues and benefits of BIST. Describe BIST
architecture and its operation.
5.4 ALU Based Programmable MISR of MC68HC11 [15] 2. Excluding the circuit under test, what are the four basic components of BIST and what
function does each component perform?
Broseghini and Lenhert implemented an ALU-Based self-test system on a MC68HC11 Family 3. Which two BIST components are necessary for system-level testing and why?
microcontroller. A fully programmable pseudorandom pattern generator and MISR are used to 4. What are the different techniques for test pattern generation?
reduce test length and aliasing probabilities. They added microcodes to configure ALU into a 5. Discuss exhaustive and pseudo-exhaustive pattern generation. Give an example to show
LFSR or MISR. It transforms the adder into a LFSR by forcing the carry input to 0. With such a that pseudo-exhaustive testing requires less number of test pattern than exhaustive
feature, the hardware overhead is minimized. The overhead is only 25% as compare to the testing.
implementation by dedicated hardware. 6. What is pseudorandom pattern generation? What is an LFSR? Describe pattern
generation using LFSR.
References 7. Make a comparison of different test strategies based on fault coverage, hardware
overhead, test time overhead and design effort.
8. An LFSR based signature register compresses an n-bit input pattern into an m-bit
[1] M. L. Bushnell and V. D Agarwal, “Essentials of Electronic Testing” Kluwer academic signature. Derive an expression for the probability of aliasing. Clearly state any
Publishers, Norwell, MA, 2000. assumptions you make.
[2] H. Al-Asaad, B. T. Murray, and J. P. Hayes, “Online BIST for embedded systems” IEEE 9. Design a weighted pseudo-random pattern generator with programmable weights 1/2, 1/4,
Design & Test of Computers, Volume 15, Issue 4, Oct.-Dec. 1998 Page(s): 17 – 24 11/32 and 1/16.
[3] M. Abramovici, M.A. Breuer, AND A.D. Friedman, “Digital Systems Testing and 10. Prove that the number of 1’s in an m-sequence differs from the number of 0’s by one.
Testable Design”, IEEE Press 1990.
[4] R. Zurawski, “Embedded Systems Handbook”, Taylor & Francis, 2005.
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11. Consider a LFSR based pattern generator where the feedback network is a single XOR
gate before the first stage. If the number of (feedback) inputs to the XOR is odd, is it
possible for the LFSR to generate maximal length sequence? Justify or contradict.
12. Show the schematic diagram of a 4-bit BILBO register.
13. A given data path has p number of n-bit registers. For having BIST capability, suppose
a% of the registers are converted to BILBO. Estimate the percentage overhead in the
registers in terms of extra hardware. All gates may be assumed to have unit cost in your
calculation.
14. It is said that by adding some extra hardware, a combinational circuit can be made
syndrome testable for single stuck-at faults. Illustrate the process for a circuit realizing
the Boolean function f = AB + B’C.
15. Define the following:
a) Compression
b) Compaction
c) Signature analysis
d) Aliasing or masking
16. Describe different response compaction techniques.
17. What are different types of LFSR? What is modular LFSR? What is characteristic
polynomial?
18. Implement a standard LFSR for the characteristic polynomial f(x) = x8+x7+x2+1.
19. Given the polynomial P(x)=x4+x2+x+1:
a. Design an external feedback LSFR with characteristic polynomial P(x).
b. Starting this LFSR in the all 1s state, determine the sequence produced.
c. Is this a maximal length LFSR?
d. Is the characteristic polynomial primitive?
20. Describe how LFSR is used in signature analysis for response compaction.
21. For an internal feedback Signature Analysis Register (SAR) with characteristic
polynomial P(x)=x6+x2+1:
a) Draw a logic diagram for the complete register.
b) Determine the resultant signature that would be obtained for the following serial
sequence of output responses produced by a known good CUT assuming the SAR
is initialized to the all 0s state. Give the binary value of the resultant signature as
it would be contained in the SAR in your logic diagram above.
101001010010 ĸ time
22. What is MISR? Give architecture of an m-stage MISR and derive its signature. What is
the masking probability of MISR?
23. Describe with example and diagram what are test-per-clock system and test-per-scan
system. What is the difference between them?
24. What is BILBO? Describe BILBO architecture and its operation?
25. Describe how BILBO is implemented in digital circuits?
26. Describe STUMPS testing system and its test procedure.
27. Give some examples of practical BIST application in industry.

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