Multi-output PDP Scan Driver IC

Naoki Shimizu
Hideto Kobayashi

1. Introduction Fig.1 PDP module drive circuit

Over the past several years, driven by advances in

Address driver IC

Address driver IC

Address driver IC

Address driver IC

Address driver IC

Address driver IC
PDP (plasma display panel) and LCD (liquid crystal
display) TV technology, flat-screen TVs have rapidly
become popular in the market for home-use televisions.
The market had previously been divided among large-
screen PDP TVs and small-screen LCD TVs, but LCD
TVs have recently entered the large-screen market,
Scan driver IC
and competition with PDP TVs is intensifying. Also,

Sustain circuit
with the increase in terrestrial digital broadcasts, and Scan driver IC
the greater popularity of such products as game devices
and DVDs (digital versatile disks), there is demand for Scan driver IC
PDP
not only larger screen displays, but also for higher pic-
ture quality, lower cost and lower power consumption.
Scan driver IC
The peripheral circuitry accounts for a large per-
centage of the cost of PDPs, and requests are intensify-
ing, year after year, for lower cost driver ICs for driving
the PDPs. Since the driver ICs also control the emis- by such discharge excite fluorescent material in each
sion of light from the panel, the driver IC performance cell, causing light to be emitted.
directly affects the PDP performance. Consequently, Figure 1 shows the configuration of a PDP module.
lower cost and higher performance are continuously re- Scan driver ICs drive horizontal electrodes in the pan-
quested of the multiple driver ICs used in a panel. el, and simultaneously control all the discharge cells
There are two types of PDP driver ICs, scan driver within the panel. The number of ICs used varies ac-
ICs that select scan lines and address driver ICs that cording to the type of the panel. Typically, a HD (high
select data. Fuji Electric is developing both of these definition) panel contains at least 720 vertical pixels
types of IC drivers. This paper introduces a 96-bit scan which configure the screen, and uses 12 conventional
driver IC developed with the aim of increasing bright- scan driver ICs which has 64 outputs. Also, panels
ness and reducing cost. having 1,920 1,080 pixels for displaying the intricate
detail of a high vision broadcast are known as full-HD
2. Features of PDP Scan Driver ICs panels. A panel that supports full-HD (having at least
1,080 vertical pixels) must use 18 conventional scan
A PDP is constructed from a rare gas mixture of driver ICs which has 64 outputs.
Ne, Xe, or the like, encapsulated between two overlap-
ping glass panels on which are formed an electrode ma- 3. PDP Scan Driver IC Technology
trix consisting of a horizontal arrangement of sustain
electrodes, for emitting, and a vertical arrangement of 3.1 Device process technology
address electrodes, for selectively addressing display Scan driver ICs use the SOI (silicon on insulator)
data. The intersections of the address electrodes and method of dielectric isolation technology. Because the
sustain electrodes demarcate a single PDP cell. isolated device area can be made small without any
The cell to be displayed is selected by opposing restrictions on the device, this method is optimal in
discharges between the address electrodes and the terms of cost and performance for scan driver ICs that
sustain electrodes, and surface discharge is performed feature a high breakdown voltage, large current and
among the sustain electrodes. The UV rays generated multiple outputs. In a multi-output scan driver IC, the

Multi-output PDP Scan Driver IC 85

output circuit area occupies 50 % or more of the entire cell flows a large current through N1 (IGBT) and per-
chip area, and therefore in order to reduce cost, the forms a preliminary discharge. At this time, a voltage
most effective means for reducing the IC chip area is to of approximately 70 V is applied to the address driver
reduce the output circuit area. Thus, a scan driver IC ICs, and for each scan line, a current of at least 1 A
which requires a large current flow uses an IGBT (in- flows to a scan driver IC.
sulated gate bipolar transistors) capable of a large cur- (3) Sustain period
rent flow even in a small area, instead of a MOS (metal In the sustain period, a voltage of approximately
oxide semiconductor). Fuji Electrics newly developed 180 V is applied alternately to the sustain circuit, and
scan driver ICs have a higher breakdown voltage than the repeated application of pulses causes cells selected
conventional scan driver ICs, and are equipped with a during the address period to sustain their discharge.
low ON-resistance SOI-IGBT device. The lower ON-re- The discharge current is supplied from both N1 (IGBT)
sistance makes it possible to reduce the amount of heat and D1 (diode), and a gradated display is implemented
generated during operation, and the higher breakdown according to the number of repeated discharges.
voltage supports higher brightness.
3.3 Smart gate control (SGC) technology
3.2 Circuit technology A problem associated with IGBTs is that if a large
Figure 2 shows the main operation and output current is output continuously, latch-up may occur and
stage circuit of a scan driver IC. A PDP uses a reset cause the device to become damaged. In particular, in
period, an address period, and a sustain period to dis- order to reduce cost, if a device is shrunk and the cur-
play a single screen. The main operation of the scan rent density increased, then the device becomes sus-
driver IC consists of address and sustain operations, ceptible to damage. One conceivable cause would be
and is described simply below. an abnormal discharge due to an overload short-circuit
(1) Reset period condition or abnormal operation such as in the case of
In the reset period, a pulse of approximately 350 V short-circuited output terminals. Modifying a device so
is applied so that wall charge can be generated stably that there will be no damage when an abnormal opera-
during the address period. The applied voltage causes tion occurs results in a larger device area and higher
a priming discharge to occur, and wall charge to be re- cost. Therefore, a SGC (smart gate control) circuit, ca-
moved. pable of outputting a large current during a discharge
(2) Address period period when current is needed and limiting the current
In the address period, cells are selected or non- during a discharge period when current is unneces-
selected according to a combination of address driver sary, was designed and used in practical applications(1).
IC pulses and scan driver IC pulses. When a cell is se- Since the SGC operation is controlled synchronously
lected, N1 (IGBT) turns ON, and when de-selected, N2 with a clock signal, the control circuits can be shared
(IGBT) turns ON and outputs a waveform. A selected for a multi-output device and the control circuits can
be miniaturized.
Fig.2 Scan driver IC operation Figure 3 shows waveforms in the case where adja-

Scan driver IC Fig.3 Short-circuit waveforms between adjacent output termi-

nals
Scan driver IC

Scan driver IC
Short-circuit waveform between
adjacent output terminals
Sustain driver IC

Address period Sustain period

Short-circuit output waveform
Current flow during
N2 (IGBT) address period
Level
shifter Current flow during
sustain period Short-circuit current
(without SGC)

Protection circuit
(with SGC)
N1 (IGBT)
Short-circuit current
SGC Protection circuit
D1 (Diode) (with SGC)
(with SGC)

86 Vol. 53 No. 3 FUJI ELECTRIC REVIEW

cent output terminals have been short-circuited. Dur- circuits, and a 96-bit output circuit. So that the output
ing a short-circuit condition in the case where SGC circuit can charge and discharge the discharge cells in
technology is not utilized, current will continue to flow the panel, a totem pole output circuit configured from
and the heat generated as a result of the increased two devices having a high breakdown voltage is used
duration of the short-circuit and the rise in voltage will in the output circuit. In order to prevent malfunction,
cause damage. However, in cases where SGC technol- Schmitt circuits are connected to the shift register
ogy is utilized, the current flow is stopped after a fixed input terminals, with the exception of the A/B signal
time has elapsed, and therefore if the short-circuit terminal that determines the direction of the shift
has a long duration, damage will not occur even if register. Also, the logic output is a trailing edge output
the voltage rises up to a certain level, and therefore, with respect to the clock signal.
the current density of the device can be increased to
reduce the device size. The SGC makes it possible to 4.3 Comparison with a conventional IC
extend the time until short-circuit damage occurs, and Figure 5 compares the chip size of a conventional
by switching the device OFF before the occurrence of
short-circuit damage, a short-circuit will not cause any Fig.4 FD3298F block diagram
damage to occur.

OC1
4. Application to a PDP Scan Driver IC (FD3298F)
OC2

As PDP TVs achieve larger screen sizes, higher res-

olution and lower cost, driver ICs are being requested LE
VDH
to have higher breakdown voltage, larger current and

Selector
CLK
DO1
lower cost. In response to these requests, and focusing to
CLK LE DO48
on multi-output capability, Fuji Electric has increased DA DATA Q1 Q1 L1
GND
the breakdown voltage without increasing the device Q2
Q3
Q2
Q3
size to develop a 96-bit scan driver IC that enables the
number of scan driver ICs used to be reduced, from 12 96-bit shift register
CLR CLR
(previously) to 8, in a HD panel as shown in Table 1.

96-bit latch
Also, in a full-HD panel, cost reductions can be realized
by reducing the number of ICs used from 18 64-bit ICs
to 12 96-bit ICs. Fuji Electrics 96-bit scan driver IC, A/B A/B VDH
FD3298F, is introduced below.

Selector
DO49
to
DO96
4.1 Features DB DATA Q96 Q96 L96
GND
Main features of the FD3298F are listed below.
(1) 96-bit bi-directional shift register (with 15 MHz
clear function) VDL GND VDH VDH

(2) 180 V absolute maximum rating (supply voltage

for output), 7 V absolute maximum rating (supply
voltage for logic) Fig.5 Die size comparison of FD3298F and conventional scan
(3) Power output supply voltage: 30 V to 150 V driver IC
(4) 5 V supply for logic
(5) Driver output current: 0.4 A/ +1.4 A (source /sink)
(6) Diode output current: 1.4 A/ +1.2 A (source / sink)
(7) 128-pin TQFP with exposed pad (E-PAD)

4.2 Circuit configuration

Figure 4 shows a block diagram of the FD3298F.
The circuit is configured from a 96-bit bi-directional
shift register circuit, a 96-bit latch circuit, data select

Table 1 Number of scan driver ICs used

Scan lines 64ch IC 96ch IC

Resolution
use number use number
SD (VGA) 480 8 6
Conventional Area ratio : 1.0 FD3298F Area ratio : 1.42
HD (XGA) over 720 12 8 scan driver IC Ratio of outputs : 1.0 Ratio of outputs : 1.5
Full HD 1,080 18 12

Multi-output PDP Scan Driver IC 87

Fig.6 External appearance of FD3298F and conventional Figure 6 shows the external appearance of the
packages package. The conventional IC package uses a TQFP
100-pin (E-PAD) package, but since the FD3298F has
a 96-bit output, the FD3298F uses a TQFP 128-pin (E-
PAD) package. The increase in the number of output
bits creates a problem of more heat generated, but by
reducing the ON-resistance to a value lower than that
of the conventional scan driver IC, the generation of
heat during operation is reduced, and by increasing the
number of E-PADs and pins, heat is dissipated more ef-
ficiently from the package.

5. Conclusion

Fuji Electrics PDP scan driver IC, FD3298F, which

was developed with the aim to achieve higher break-
Conventional scan driver IC FD3298F down voltage and lower cost has been introduced.
TQFP 100-pin TQFP 128-pin Fuji Electric intends to continue to develop device
technology, circuit technology and process technol-
ogy for scan driver ICs in response to marketplace and
scan driver IC and the FD3298F. The chip size of the panel manufacturers requests.
FD3298F is 1.42 times that of a conventional 64-bit
scan driver IC, but the number of bits is 1.5 times Reference
greater, and since the number of chips used will de- (1) Kobayashi, H. et al. PDP Scan Driver IC with Smart
crease, the cost will lower than in the case of conven- Gate Controlled IGBTs. IDW04. PDP3-3.
tional scan driver ICs.

88 Vol. 53 No. 3 FUJI ELECTRIC REVIEW