Pic 18 F 46 K 40
Pic 18 F 46 K 40
Pic 18 F 46 K 40
Temperature Indicator
Windowed Watchdog
8-bit TMR with HLT
Zero-Cross Detect
Computation (ch)
Data Sheet Index
CCP/10-bit PWM
Data EEPROM
16-bit Timers
Comparators
Data SRAM
5-bit DAC
EUSART
Debug(1)
I/O Pins
I2C/SPI
(bytes)
(bytes)
(bytes)
Timer
CWG
PPS
Device
Note: For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
VPP/MCLR/RE3 1 28 RB7/ICSPDAT
RA0 2 27 RB6/ICSPCLK
RA1 3 26 RB5
RA2 4 25 RB4
RA3 5 24 RB3
PIC18(L)F2xK40
RA4 6 23 RB2
RA5 7 22 RB1
VSS 8 21 RB0
RA7 9 20 VDD
RA6 10 19 VSS
RC0 11 18 RC7
RC1 12 17 RC6
RC2 13 16 RC5
RC3 14 15 RC4
RB6/ICSPCLK
RB7/ICSPDAT
RA0
RB5
RB4
RA1
28 27 26 25 24 23 22
RA2 1 21 RB3
RA3 2 20 RB2
RA4 3 19 RB1
RA5 4 PIC18(L)F2xK40 18 RB0
VSS 5 17 VDD
RA7 6 16 VSS
RA6 7 15 RC7
8 9 10 11 12 13 14
RC5
RC0
RC6
RC2
RC3
RC4
RC1
40-pin PDIP
VPP/MCLR/RE3 1 40 RB7/ICSPDAT
RA0 2 39 RB6/ICSPCLK
RA1 3 38 RB5
RA2 4 37 RB4
RA3 5 36 RB3
RA4 6 35 RB2
RA5 7 34 RB1
PIC18(L)F4xK40
RE0 8 33 RB0
RE1 9 32 VDD
RE2 10 31 VSS
VDD 11 30 RD7
VSS 12 29 RD6
RA7 13 28 RD5
RA6 14 27 RD4
RC0 15 26 RC7
RC1 16 25 RC6
RC2 17 24 RC5
RC3 18 23 RC4
RD0 19 22 RD3
RD1 20 21 RD2
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
40 39 38 37 36 35 34 33 32 31
RC7 1
RD4 2 30 RC0
RD5 3 29 RA6
RD6 4 28 RA7
RD7 5 27 VSS
VSS 6 PIC18(L)F4xK40 26 VDD
VDD 7 25 RE2
RB0 8 24 RE1
RB1 9 23 RE0
RB2 22 RA5
10
21 RA4
11 12 13 14 15 16 17 18 19 20
RB3
RA1
RA2
RA3
RB4
RB5
VPP/MCLR/RE3
RA0
ICSPCLK/RB6
ICSPDAT/RB7
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
RC0
43
42
41
40
39
37
36
35
34
44
38
RC7 1 33 RA6
RD4 2 32 RA7
RD5 3 31 NC
RD6 4 30 VSS
RD7 5 29 NC
VSS 6 PIC18(L)F4xK40 28 VDD
VDD 7 27 RE2
NC 8 26 RE1
RB0 9 25 RE0
RB1 10 24 RA5
RB2 11 23 RA4
22
21
12
13
14
15
16
17
18
19
20
ICSPCLK/RB6
RB3
RB4
RB5
RA0
RA2
ICSPDAT/RB7
VPP/MCLR/RE3
RA1
NC
RA3
Note 1: See Table 2 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to VSS, however it must not be the
only VSS connection to the device.
44-pin TQFP
RC5
RC6
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
44 43 42 41 40 39 38 37 36 35 34
RC7 1 33 NC
RD4 2 32 RC0
RD5 3 31 RA6
4 30 RA7
RD6
RD7 5 29 VSS
6 PIC18(L)F4xK40 28 VDD
VSS
VDD 7 27 RE2
RB0 8 26 RE1
RB1 9 25 RE0
RB2 10 24 RA5
23 RA4
RB3 11
12 13 14 15 16 17 18 19 20 21 22
RA2
RA3
RB4
RB5
ICSPDAT/RB7
VPP/MCLR/RE3
AN0/RA0
ICSPCLK/RB6
AN1/RA1
NC
NC
28-Pin (U)QFN
Comparator
Reference
Interrupt
EUSART
Pull-up
Timers
MSSP
Basic
CWG
DSM
CCP
ZCD
A/D
I/O(2)
PIC18(L)F26/45/46K40
RA6 10 7 ANA6 IOCA6 Y CLKOUT
OSC2
RA7 9 6 ANA7 IOCA7 Y OSC1
CLKIN
RB0 21 18 ANB0 C2IN1+ CWG1(1) ZCDIN IOCB0 SS2(1) Y
INT0(1)
RB1 22 19 ANB1 C1IN3- IOCB1 SCK2(1) Y
C2IN3- INT1(1) SCL2(3,4)
RB2 23 20 ANB2 IOCB2 SDI2(1) Y
INT2(1) SDA2(3,4)
RB3 24 21 ANB3 C1IN2- IOCB3 Y
C2IN2-
RB4 25 22 ANB4 T5G(1) IOCB4 Y
(1)
RB5 26 23 ANB5 T1G IOCB5 Y
DS40001816C-page 7
28-Pin (U)QFN
Comparator
Reference
Interrupt
EUSART
Pull-up
Timers
MSSP
Basic
CWG
DSM
CCP
ZCD
A/D
I/O(2)
PIC18(L)F26/45/46K40
RE3 1 26 IOCE3 Y VPP/MCLR
VSS 19 16 VSS
VDD 20 17 VDD
VSS 8 5 VSS
OUT(2) ADGRDA C1OUT TMR0 CCP1 CWG1A TX1/CK1(3) DSM SDO1
ADGRDB C2OUT CCP2 CWG1B DT1(3) SCK1
PWM3 CWG1C TX2/CK2(3) SDO2
PWM4 CWG1D DT2(3) SCK2
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1).
2: All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be
standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
DS40001816C-page 8
2016 Microchip Technology Inc.
40-Pin UQFN
44-Pin TQFP
Comparator
40-Pin PDIP
44-Pin QFN
Reference
Interrupt
EUSART
Pull-up
Timers
MSSP
Basic
CWG
DSM
CCP
ZCD
A/D
I/O(2)
PIC18(L)F26/45/46K40
RB1 34 9 10 9 ANB1 C1IN3- IOCB1 SCK2(1) Y
C2IN3- INT1(1) SCL2(3,4)
RB2 35 10 11 10 ANB2 IOCB2 SDI2(1) Y
INT2(1) SDA2(3,4)
RB3 36 11 12 11 ANB3 C1IN2- IOCB3 Y
C2IN2-
RB4 37 12 14 14 ANB4 T5G(1) IOCB4 Y
RB5 38 13 15 15 ANB5 T1G(1) IOCB5 Y
RB6 39 14 16 16 ANB6 IOCB6 CK2(1) Y ICSPCLK
RB7 40 15 17 17 ANB7 DAC1OUT2 T6AIN(1) IOCB7 RX2/DT2(1) Y ICSPDAT
RC0 15 30 34 32 ANC0 T1CKI(1) IOCC0 Y SOSCO
T3CKI(1)
(1)
T3G
DS40001816C-page 9
40-Pin UQFN
44-Pin TQFP
Comparator
40-Pin PDIP
44-Pin QFN
Reference
Interrupt
EUSART
Pull-up
Timers
MSSP
Basic
CWG
DSM
CCP
ZCD
A/D
I/O(2)
PIC18(L)F26/45/46K40
RE0 8 23 25 25 ANE0 Y
RE1 9 24 26 26 ANE1 Y
RE2 10 25 27 27 ANE2 Y
RE3 1 16 18 18 IOCE3 Y VPP/MCLR
VSS 12 6 6 6 VSS
VDD 11 7 7 7 VDD
VDD 32 26 28 28 VDD
VSS 31 27 30 29 VSS
OUT(2) ADGRDA C1OUT TMR0 CCP1 CWG1A TX1/ DSM SDO1 OUT(2)
ADGRDB C2OUT CCP2 CWG1B CK1(3) SCK1
PWM3 CWG1C DT1(3) SDO2
PWM4 CWG1D TX2/ SCK2
CK2(3)
DT2(3)
DS40001816C-page 10
Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers (Register 17-1).
2: All pin outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers.
3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections.
4: These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be
standard TTL/ST as selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
PIC18(L)F26/45/46K40
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with PIC18(L)F26/45/46K40 Microcontrollers ............................................................................ 18
3.0 Device Configuration .................................................................................................................................................................. 21
4.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 34
5.0 Reference Clock Output Module ................................................................................................................................................ 53
6.0 Power-Saving Operation Modes ................................................................................................................................................ 58
7.0 Peripheral Module Disable (PMD).............................................................................................................................................. 66
8.0 Resets ........................................................................................................................................................................................ 73
9.0 Windowed Watchdog Timer (WWDT) ........................................................................................................................................ 82
10.0 Memory Organization ................................................................................................................................................................. 91
11.0 Nonvolatile Memory (NVM) Control.......................................................................................................................................... 123
12.0 8x8 Hardware Multiplier............................................................................................................................................................ 147
13.0 Cyclic Redundancy Check (CRC) Module with Memory Scanner............................................................................................ 149
14.0 Interrupts .................................................................................................................................................................................. 166
15.0 I/O Ports ................................................................................................................................................................................... 196
16.0 Interrupt-on-Change ................................................................................................................................................................. 208
17.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 212
18.0 Timer0 Module ......................................................................................................................................................................... 220
19.0 Timer1/3/5 Module with Gate Control....................................................................................................................................... 226
20.0 Timer2/4/6 Module ................................................................................................................................................................... 242
21.0 Capture/Compare/PWM Module .............................................................................................................................................. 263
22.0 Pulse-Width Modulation (PWM ) .............................................................................................................................................. 277
23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 285
24.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 291
25.0 Data Signal Modulator (DSM) Module...................................................................................................................................... 318
26.0 Master Synchronous Serial Port Module ................................................................................................................................. 329
27.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 386
28.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 417
29.0 Temperature Indicator Module ................................................................................................................................................. 419
30.0 5-Bit Digital-to-Analog Converter (DAC) Module...................................................................................................................... 421
31.0 Analog-to-Digital Converter with Computation (ADC2) Module ............................................................................................... 425
32.0 Comparator Module.................................................................................................................................................................. 461
33.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 471
34.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 478
35.0 Instruction Set Summary .......................................................................................................................................................... 480
36.0 Development Support............................................................................................................................................................... 530
37.0 Electrical Specifications............................................................................................................................................................ 534
38.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 564
39.0 Packaging Information.............................................................................................................................................................. 565
Appendix A: Revision History............................................................................................................................................................. 589
Appendix B: Device Differences ........................................................................................................................................................ 590
The Microchip Website ...................................................................................................................................................................... 591
Customer Change Notification Service .............................................................................................................................................. 591
Customer Support .............................................................................................................................................................................. 591
Product Identification System ............................................................................................................................................................ 592
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Website; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Data Bus<8>
Table Pointer<21>
8 8 Data Latch
inc/dec logic
Data Memory
21 PCLATU PCLATH
20 Address Latch PORTA
PCU PCH PCL RA<7:0>
Program Counter 12
Data Address<12>
31-Level Stack
Address Latch 4 12 4
BSR FSR0 Access
Program Memory STKPTR Bank
(8/16/32/64 Kbytes) FSR1
PORTB
FSR2 12
Data Latch RB<7:0>
inc/dec
8 logic
Table Latch
8
Instruction State machine
Decode and control signals
Control
PRODH PRODL
PORTD
8x8 Multiply RD<7:0>
3 8
BITOP W
8 8 8
OSC1(2) Internal
Oscillator Power-up
Timer 8 8
Block PORTE
OSC2(2) Oscillator ALU<8>
LFINTOSC Start-up Timer RE<2:0>
SOSCI Oscillator Power-on 8 RE3(1)
Reset
64 MHz
SOSCO Oscillator Watchdog
Timer
Precision FVR
Single-Supply Brown-out Band Gap
MCLR(1) Reset
Programming Reference
In-Circuit Fail-Safe
Debugger Clock Monitor
FVR
Comparators CCP1 PWM3 MSSP1 EUSART1 ADC FVR
ECWG DSM PMD
DAC C1/C2 CCP2 PWM4 MSSP2 EUSART2 10-bit
Vss
R2
MCLR minimum, thereby reducing PCB trace
C1 inductance.
R1
R2
MCLR
PIC18(L)F2x/4xK40
JP
C1
Use a grounded copper pour around the oscillator cir- DEVICE PINS
cuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to the
MCU ground. Do not run any signal traces or power
Primary OSC1
traces inside the ground pour. Also, if using a two-sided Oscillator
board, avoid any traces on the other side of the board C1 ` OSC2
where the crystal is placed.
C2 GND
Layout suggestions are shown in Figure 2-3. In-line `
packages may be handled with a single-sided layout
SOSCO
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to com- SOSCI
Secondary Oscillator
pletely surround the pins and components. A suitable (SOSC)
solution is to tie the broken guard sections to a mirrored Crystal `
ground layer. In all cases, the guard trace(s) must be
returned to ground.
SOSC: C1 SOSC: C2
In planning the applications routing and I/O assign-
ments, ensure that adjacent port pins, and other
signals in close proximity to the oscillator, are benign
(i.e., free of high frequencies, short rise and fall times, Fine-Pitch (Dual-Sided) Layouts:
and other similar noise). Top Layer Copper Pour
(tied to ground)
For additional information and design guidance on
oscillator circuits, please refer to these Microchip
Application Notes, available at the corporate website Bottom Layer
Copper Pour
(www.microchip.com): (tied to ground)
AN826, Crystal Oscillator Basics and Crystal
Selection for rfPIC and PICmicro Devices OSCO
OSCI
DEVICE PINS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
PIC18LF2x/4xK40 device:
11 = Brown-out Reset Voltage (VBOR) set to 1.90V
10 = Brown-out Reset Voltage (VBOR) set to 2.45V
01 = Brown-out Reset Voltage (VBOR) set to 2.7V
00 = Brown-out Reset Voltage (VBOR) set to 2.85V
Note 1: The higher voltage setting is recommended for operation at or above 16 MHz.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
WDTPS at POR
Software Control
WDTCPS Typical Time Out
Value Divider Ratio of WDTPS?
(FIN = 31 kHz)
11111 01011 1:65536 216 2s Yes
10011 10011
... ... 1:32 25 1 ms No
11110 11110
10010 10010 1:8388608 223 256s
10001 10001 1:4194304 222 128s
21
10000 10000 1:2097152 2 64s
01111 01111 1:1048576 220 32s
01110 01110 1:524299 219 16s
01101 01101 1:262144 218 8s
01100 01100 1:131072 217 4s
01011 01011 1:65536 216 2s
15
01010 01010 1:32768 2 1s
01001 01001 1:16384 214 512 ms No
01000 01000 1:8192 213 256 ms
00111 00111 1:4096 212 128 ms
11
00110 00110 1:2048 2 64 ms
00101 00101 1:1024 210 32 ms
9
00100 00100 1:512 2 16 ms
00011 00011 1:256 28 8 ms
00010 00010 1:128 27 4 ms
00001 00001 1:64 26 2 ms
5
00000 00000 1:32 2 1 ms
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Refer to Table 10-2 for details on implementation of the individual WRT bits.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Refer to Table 10-2 for details on implementation of the individual EBTR bits.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 1
-n = Value for blank device 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Default/
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Unprogrammed
Value
30 0000h CONFIG1L RSTOSC2 RSTOSC1 RSTOSC0 FEXTOSC2 FEXTOSC1 FEXTOSC0 1111 1111
30 0001h CONFIG1H FCMEN CSWEN CLKOUTEN 1111 1111
30 0002h CONFIG2L BOREN1 BOREN0 LPBOREN PWRTE MCLRE 1111 1111
30 0003h CONFIG2H XINST DEBUG STVREN PPS1WAY ZCD BORV1 BORV0 1111 1111
30 0004h CONFIG3L WDTE<1:0> WDTCPS<4:0> 1111 1111
30 0005h CONFIG3H WDTCCS<2:0> WDTCWS<2:0> 1111 1111
30 0006h CONFIG4L WRT7 WRT6 WRT5 WRT4 WRT3 WRT2 WRT1 WRT0 1111 1111
30 0007h CONFIG4H LVP SCANE WRTD WRTB WRTC 1111 1111
30 0008h CONFIG5L CPD CP 1111 1111
30 000Ah CONFIG6L EBTR7 EBTR6 EBTR5 EBTR4 EBTR3 EBTR2 EBTR1 EBTR0 1111 1111
30 000Bh CONFIG6H EBTRB 1111 1111
Preliminary
PIC18(L)F26/45/46K40
DS40001816C-page 30
PIC18(L)F26/45/46K40
3.3 Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory are controlled independently. Internal
access to the program memory is unaffected by any
code protection setting.
3.5 User ID
Eight words in the memory space (200000h-200000Fh)
are designated as ID locations where the user can
store checksum or other code identification numbers.
These locations are readable and writable during
normal execution. See Section 11.2 User ID, Device
ID and Configuration Word Access for more
information on accessing these memory locations. For
more information on checksum calculation, see the
PIC18(L)F2X/4XK40 Memory Programming
Specification (DS40001772).
R R R R R R R R
DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0
bit 7 bit 0
Legend:
R = Readable bit 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Device Device ID
PIC18F26K40 6980h
PIC18F45K40 6940h
PIC18F46K40 6920h
PIC18LF26K40 6A60h
PIC18LF45K40 6A20h
PIC18LF46K40 6A00h
R R R R R R R R
MJRREV<1:0> MNRREV<5:0>
bit 7 bit 0
Legend:
R = Readable bit 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Rev. 10-000208D
5/10/2016
CLKIN/OSC1
External
Oscillator
(EXTOSC)
CLKOUT/OSC2
CDIV<4:0>
4x PLL
COSC<2:0>
SOSCIN/SOSCI
Secondary 512
Oscillator 1001
256
(SOSC) 111 1000
128 Sleep
SOSCO 010 0111 System Clock
64
100 0110
Post Divider
LFINTOSC
Preliminary
32
101 0101
31 kHz 16
110 0100 SYSCMD Peripheral Clock
Oscillator
8
Reserved 011 0011
PIC18(L)F26/45/46K40
4
Reserved 001 0010 Sleep
2
HFINTOSC Reserved 000 0001 Idle
1
0000
FRQ<3:0>
1,2,4,8,12,16,32,48,64
MHz
Oscillator
LFINTOSC is used to
FSCM
monitor system clock
MFINTOSC
To Peripherals
31.25 kHz and 500 kHz To Peripherals
DS40001816C-page 35
Oscillator To Peripherals
To Peripherals
PIC18(L)F26/45/46K40
4.2 Register Definitions: Oscillator Control
REGISTER 4-1: OSCCON1: OSCILLATOR CONTROL REGISTER1
U-0 R/W-f/f R/W-f/f R/W-f/f R/W-q/q R/W-q/q R/W-q/q R/W-q/q
NOSC<2:0> NDIV<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared f = determined by fuse setting
q = Reset value is determined by hardware
Note 1: The default value (f/f) is determined by the RSTOSC Configuration bits. See Table 4-1below.
2: If NOSC is written with a reserved value (Table 4-2), the operation is ignored and neither NOSC nor NDIV is
written.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Reset value is determined by hardware
Note 1: The POR value is the value present when user code execution begins.
2: The Reset value (q/q) is the same as the NOSC/NDIV bits.
Note 1: EXTOSC configured by the FEXTOSC bits of Configuration Word 1 (Register 3-1).
2: HFINTOSC frequency is set with the HFFRQ bits of the OSCFRQ register (Register 4-5).
3: EXTOSC must meet the PLL specifications (Table 37-9).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Note 1: If CSWHOLD = 0, the user may not see this bit set because, when the oscillator becomes ready there
may be a delay of one instruction clock before this bit is set. The clock switch occurs in the next instruction
cycle and this bit is cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Reset value is determined by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Reset value is determined by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
The External Clock (EC) mode allows an externally HS Oscillator mode selects the highest gain setting of the
generated logic level signal to be the system clock internal inverter-amplifier. HS mode current consumption
source. When operating in this mode, an external clock is the highest of the three modes. This mode is best
source is connected to the OSC1 input. suited for resonators that require a high drive setting
OSC2/CLKOUT is available for general purpose I/O or (above 8 MHz).
CLKOUT. Figure 4-2 shows the pin connections for EC Figure 4-3 and Figure 4-4 show typical circuits for
mode. quartz crystal and ceramic resonators, respectively.
PIC MCU
OSC1/CLKIN
C1 To Internal
Logic
4.3.2.5 ADCRC
The ADCRC is an oscillator dedicated to the ADC2
module. The ADCRC oscillator can be manually
enabled using the ADOEN bit of the OSCEN register.
The ADCRC runs at a fixed frequency of 600 kHz.
ADCRC is automatically enabled if it is selected as the
clock source for the ADC2 module.
OSC #1 OSC #2
ORDY
NOTE 2
NOSCR
NOTE 1
CSWIF
USER
CSWHOLD CLEAR
Note 1: CSWIF is asserted coincident with NOSCR; interrupt is serviced at OSC#2 speed.
2: The assertion of NOSCR is hidden from the user because it appears only for the duration of the switch.
OSC #1 OSC #2
ORDY
NOSCR
NOTE 1
CSWIF
USER
CSWHOLD CLEAR
Note 1: CSWIF is asserted coincident with NOSCR, and may be cleared before or after clearing CSWHOLD = 0.
OSC #1
ORDY
NOTE 2
NOSCR
NOTE 1
CSWIF
CSWHOLD
Note 1: CSWIF may be cleared before or after rewriting OSCCON1; CSWIF is not automatically cleared.
2: ORDY = 0 if OSCCON1 does not match OSCCON2; a new switch will begin.
LFINTOSC
64 R Q
Oscillator
31 kHz 488 Hz
(~32 s) (~2 ms)
Sample Clock
System Oscillator
Clock Failure
Output
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
Rev. 10-000261B
5/11/2016
CLKRDIV<2:0>
CLKREN Counter Reset
128
Reference Clock Divider 111
See 64 CLKRDC<1:0>
110
CLKRCLK 32
Register 101
16 CLKR
100
8 Duty Cycle PPS
011
4
010
2
001 To Peripherals
CLKREN 000
CLKRCLK<3:0>
Rev. 10-000264B
5/25/2016
P1 P2
CLKRCLK
CLKREN
CLKR Output
CLKRDIV<2:0> = 001
CLKRDC<1:0> = 10
Duty Cycle
(50%)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2
/
W 3 3 3 3 3 3 3 3 3 3 3 3 3
4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
CPU Clock
Interrupt
Here
(ROI = 1)
Note 1: Multi-cycle instructions are executed to completion before fetching 0004h.
2: If the pre-fetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will resume execution at full speed.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
CLKOUT(2) TOST(3)
GIE bit
(INTCON reg.) Processor in
Sleep
Instruction Flow
PC PC PC + 1 PC + 2 PC + 2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = Sleep
Instruction Sleep Inst(PC + 1) Forced NOP Forced NOP
Executed Inst(PC - 1) Inst(0004h)
6.2.3 LOW-POWER SLEEP MODE 6.2.3.1 Sleep Current vs. Wake-up Time
The PIC18F2x/4xK40 device family contains an In the default operating mode, the LDO and reference
internal Low Dropout (LDO) voltage regulator, which circuitry remain in the normal configuration while in
allows the device I/O pins to operate at voltages up to Sleep. The device is able to exit Sleep mode quickly
5.5V while the internal device logic operates at a lower since all circuits remain active. In Low-Power Sleep
voltage. The LDO and its associated reference circuitry mode, when waking-up from Sleep, an extra delay time
must remain active when the device is in Sleep mode. is required for these circuits to return to the normal
The PIC18F2x/4xK40 devices allows the user to configuration and stabilize.
optimize the operating current in Sleep, depending on The Low-Power Sleep mode is beneficial for
the application requirements. applications that stay in Sleep mode for long periods of
time. The Normal mode is beneficial for applications
Low-Power Sleep mode can be selected by setting the
that need to wake from Sleep quickly and frequently.
VREGPM bit of the VREGCON register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other
Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Note 1: When ROI = 1 or DOE = 1, DOZEN is changed by hardware interrupt entry and/or exit.
2: Entering ICD overrides DOZEN, returning the CPU to full execution speed; this bit is not affected.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Note 1: Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked
by FOSC/4 are not affected.
2: Subject to SCANE bit in CONFIG4H.
3: When enabling NVM, a delay of up to 1 s may be required before accessing data.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Stack Underflow
Stack Overflow
VPP/MCLR MCLRE
WWDT Time-out/
Window voilation Device
Reset
Power-on
Reset
VDD
Brown-out
R
Reset(1) Power-up
Timer
LFINTOSC PWRTE
LPBOR
Reset
BOR
BOR Event
REARM POR
Event To PCON
indicator bit
POR
LPBOR
POR Event
LPBOR Event
Reset
logic
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
HC = Bit is cleared by hardware HS = Bit is set by hardware
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
VBOR
VDD
VBOR
Internal
Reset TPWRT(1)
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
CLKIN
FOSC
WWDT
Armed
WDT
Window
Violation
Window Closed
Window
Comparator
CLRWDT Sizes
WINDOW
RESET
Reserved 111
Reserved 110
Reserved 101
R
Reserved 100 18-bit Prescale
Reserved 011 Counter
E
626& 010
MFINTOSC/16 001
LFINTOSC 000
CS
PS
R
5-bit Overflow
WDT Time-out
WDT Counter Latch
WDTE<1:0> = 01
SEN
WDTE<1:0> = 11
WDTE<1:0> = 10
Sleep
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Note 1: If WDTCCS <2:0> in CONFIG3H = 111, the Reset value of WDTCS<2:0> is 000.
2: The Reset value of WINDOW<2:0> is determined by the value of WDTCWS<2:0> in the CONFIG3H
register.
3: If WDTCCS<2:0> in CONFIG3H 111, these bits are read-only.
4: If WDTCWS<2:0> in CONFIG3H 111, these bits are read-only.
REGISTER 9-3: WDTPSL: WWDT PRESCALE SELECT LOW BYTE REGISTER (READ-ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal
operation.
REGISTER 9-4: WDTPSH: WWDT PRESCALE SELECT HIGH BYTE REGISTER (READ-ONLY)
R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0
PSCNT<15:8>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal
operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The 18-bit WDT prescale value, PSCNT<17:0> includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT<17:0> is intended for debug operations and should be read during normal
operation.
CLRWDT Instruction
(or other WDT reset)
Window Period
Note 1 Stack (31 levels) Stack (31 levels) Stack (31 levels) Stack (31 levels) Note 1
00 0000h Reset Vector Reset Vector Reset Vector Reset Vector 00 0000h
00 0008h Interrupt Vector High Interrupt Vector High Interrupt Vector High Interrupt Vector High 00 0008h
00 0018h Interrupt Vector Low Interrupt Vector Low Interrupt Vector Low Interrupt Vector Low 00 0018h
00 001Ah 00 001Ah
User Flash Memory
(8KW)
00 3FFFh User Flash Memory 00 3FFFh
00 4000h (16KW) 00 4000h
User Flash Memory
(32KW)
00 7FFFh PFM Flash Memory 00 7FFFh
00 8000h (64KW) 00 8000h
00 FFFFh 00 FFFFh
Not present(1)
01 0000h 01 0000h
Not present(1)
01 FFFFh 01 FFFFh
Not present(1)
02 0000h 02 0000h
Not present(1)
1F FFFFh 1F FFFFh
20 0000h 20 0000h
User IDs (8 Words)
20 000Fh 20 000Fh
20 0010h 20 0010h
Reserved
2F FFFFh 2F FFFFh
30 0000h 30 0000h
Configuration Words (6 Words)
30 000Bh 30 000Bh
30 000Ch 30 000Ch
Reserved
30 FFFFh 30 FFFFh
31 0000h DataEEByte0 31 0000h
DataEEByte0
31 00FFh DataEEByte255
Unimplemented
DataEEByte1023
31 03FFh 31 03FFh
31 0400h 31 0400h
Reserved
3F FFFBh 3F FFFBh
3F FFFCh 3F FFFCh
Revision ID (1 Word)(2)
3F FFFDh 3F FFFDh
3F FFFEh 3F FFFEh
Device ID (1 Word)(2)
3F FFFFh 3F FFFFh
Note 1: The addresses do not roll over. The region is read as 0.
2: Device/Revision IDs are hard-coded in silicon.
00 4000h Block 2
4 KW
00 5FFFh CP, WRT2, EBTR2 Block 1 Block 1
8 KW 8 KW
00 6000h Block 3 CP, WRT1, EBTR1 CP, WRT1, EBTR1
4 KW
00 7FFFh CP, WRT3, EBTR3
01 C000h Block 7
8 KW
01 FFFFh CP, WRT7, EBTR7
30 0000h
6 Words
CONFIG
WRTC
30 000Bh
31 0000h 256 Words
Data 31 00FFh CPD, WRTD 1 KW
EEPROM 31 0100h CPD, WRTD
Unimplemented
31 03FFh
11111
11110
Top-of-Stack Registers 11101 Stack Pointer
10.1.2.2 Return Stack Pointer (STKPTR) If STVREN is cleared, the STKUNF bit will be set, but
no Reset will occur.
The STKPTR register (Register 10-1) contains the
Stack Pointer value. The STKOVF (Stack Overflow) When STVREN = 0, STKUNF will be set but no Reset
Status bit and the STKUNF (Stack Underflow) Status bit will occur.
can be accessed using the PCON0 register. The value
of the Stack Pointer can be 0 through 31. On Reset, the
Stack Pointer value will be zero. The user may read and Note: Returning a value of zero to the PC on an
write the Stack Pointer value. This feature can be used underflow has the effect of vectoring the
by a Real-Time Operating System (RTOS) for stack program to the Reset vector, where the
maintenance. After the PC is pushed onto the stack 32 stack conditions can be verified and
times (without popping any values off the stack), the appropriate actions can be taken. This is
STKOVF bit is set. The STKOVF bit is cleared by soft- not the same as a Reset, as the contents
ware or by a POR. The action that takes place when the of the SFRs are not affected.
stack becomes full depends on the state of the
STVREN (Stack Overflow Reset Enable) Configuration 10.1.2.3 PUSH and POP Instructions
bit. (Refer to Section 3.1 Configuration Words for Since the Top-of-Stack is readable and writable, the
a description of the device Configuration bits.) ability to push values onto the stack and pull values off
If STVREN is set (default), a Reset will be generated the stack without disturbing normal program execution
and a Stack Overflow will be indicated by the STKOVF is a desirable feature. The PIC18 instruction set
bit when the 32nd push is initiated. This includes CALL includes two instructions, PUSH and POP, that permit
and CALLW instructions, as well as stacking the return the TOS to be manipulated under software control.
address during an interrupt response. The STKOVF bit TOSU, TOSH and TOSL can be modified to place data
will remain set and the Stack Pointer will be set to zero. or a return address on the stack.
If STVREN is cleared, the STKOVF bit will be set on the The PUSH instruction places the current PC value onto
32nd push and the Stack Pointer will remain at 31 but the stack. This increments the Stack Pointer and loads
no Reset will occur. Any additional pushes will the current PC value onto the stack.
overwrite the 31st push but the STKPTR will remain at The POP instruction discards the current TOS by
31. decrementing the Stack Pointer. The previous value
Setting STKOVF = 1 in software will change the bit, but pushed onto the stack then becomes the TOS value.
will not generate a Reset.
The STKUNF bit is set when a stack pop returns a
value of zero. The STKUNF bit is cleared by software
or by POR. The action that takes place when the stack
becomes full depends on the state of the STVREN
(Stack Overflow Reset Enable) Configuration bit.
(Refer to Section 3.1 Configuration Words for a
description of the device Configuration bits.)
If STVREN is set (default) and the stack has been
popped enough times to unload the stack, the next pop
will return a value of zero to the PC, it will set the
STKUNF bit and a Reset will be generated. This
condition can be generated by the RETURN, RETLW and
RETFIE instructions.
Legend:
R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
10.2.1 STACK OVERFLOW AND Example 10-1 shows a source code example that uses
UNDERFLOW RESETS the fast register stack during a subroutine call and
return.
Device Resets on Stack Overflow and Stack Underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a Full EXAMPLE 10-1: FAST REGISTER STACK
or Underflow condition will set the appropriate STKOVF CODE EXAMPLE
or STKUNF bit and then cause a device Reset. When CALL SUB1, FAST ;STATUS, WREG, BSR
STVREN is cleared, a Full or Underflow condition will ;SAVED IN FAST REGISTER
set the appropriate STKOVF or STKUNF bit but not ;STACK
cause a device Reset. The STKOVF or STKUNF bits
are cleared by the user software or a Power-on Reset.
SUB1
10.2.2 FAST REGISTER STACK
A fast register stack is provided for the Status, WREG RETURN, FAST ;RESTORE VALUES SAVED
and BSR registers, to provide a fast return option for ;IN FAST REGISTER STACK
interrupts. The stack for each register is only one level
deep and is neither readable nor writable. It is loaded
with the current value of the corresponding register
when the processor vectors for an interrupt. All inter-
rupt sources will push values into the stack registers.
The values in the registers are then loaded back into
their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low priority interrupts. If a high priority interrupt occurs
while servicing a low priority interrupt, the stack register
values stored by the low priority interrupt will be
overwritten. In these cases, users must save the key
registers by software during a low priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no
interrupts are used, the fast register stack can be used
to restore the STATUS, WREG and BSR registers at
the end of a subroutine call. To use the fast register
stack for a subroutine call, a CALL label, FAST
instruction must be executed to save the STATUS,
WREG and BSR registers to the fast register stack. A
RETURN, FAST instruction is then executed to restore
these registers from the fast register stack.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
Q3 Phase
Clock
Q4
PC PC PC + 2 PC + 4
OSC2/CLKOUT
(RC mode)
Execute INST (PC 2)
Fetch INST (PC) Execute INST (PC)
Fetch INST (PC + 2) Execute INST (PC + 2)
Fetch INST (PC + 4)
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is flushed from the pipeline while the new instruction is being fetched and then executed.
00h 400h
Virtual Bank
0100
Banks
GPR GPR Access RAM 00h
4 to 7
5Fh
PIC18(L)F26/45/46K40
0111
SFR 60h
FFh 7FFh
Unimplemented FFh
00h 800h
1000
Banks
Unimplemented GPR
8 to 13
1101
FFh DFFh
00h Unimplemented(1) Unimplemented(1) GPR(1) E00h
Bank 14 1110
FFh SFR(1) SFR(1) SFR(1) EFFh
00h F00h
F5Fh
Bank 15 1111 SFR SFR SFR
F60h
DS40001816C-page 101
FFh FFFh
Note 1: It depends on the number of SFRs. Refer to Table 10-3 and Table 10-4.
PIC18(L)F26/45/46K40
FIGURE 10-5: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
Bank 3
through
Bank 13
FFh
E00h
00h
Bank 14
F00h FFh
00h
Bank 15
FFFh FFh
Note 1: The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to
the registers of the Access Bank.
2: The MOVFF instruction embeds the entire 12-bit address in the instruction.
FF1h Unimplemented
FF0h Unimplemented
FEFh INDF0 Uses contents of FSR0 to address data memory value of FSR0 not changed (not a physical register) --------
FEEh POSTINC0 Uses contents of FSR0 to address data memory value of FSR0 post-incremented (not a physical register) --------
FEDh POSTDEC0 Uses contents of FSR0 to address data memory value of FSR0 post-decremented (not a physical register) --------
FECh PREINC0 Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register) --------
FEBh PLUSW0 Uses contents of FSR0 to address data memory value of FSR0 pre-incremented (not a physical register) value of --------
FSR0 offset by W
FEAh FSR0H Indirect Data Memory Address Pointer 0 High ----xxxx
FE7h INDF1 Uses contents of FSR0 to address data memory value of FSR1 not changed (not a physical register) --------
FE6h POSTINC1 Uses contents of FSR0 to address data memory value of FSR1 post-incremented (not a physical register) --------
FE5h POSTDEC1 Uses contents of FSR0 to address data memory value of FSR1 post-decremented (not a physical register) --------
FE4h PREINC1 Uses contents of FSR0 to address data memory value of FSR1 pre-incremented (not a physical register) --------
FE3h PLUSW1 Uses contents of FSR0 to address data memory value of FSR1 pre-incremented (not a physical register) value of --------
FSR0 offset by W
Legend: x = unknown, u = unchanged, = unimplemented, q = value depends on condition
Note 1: Not available on LF devices.
2: Not available on PIC18(L)F26K40 (28-pin variants).
3: Not available on PIC18(L)F45K40 devices.
FDFh INDF2 Uses contents of FSR0 to address data memory value of FSR2 not changed (not a physical register) --------
FDEh POSTINC2 Uses contents of FSR0 to address data memory value of FSR2 post-incremented (not a physical register) --------
FDDh POSTDEC2 Uses contents of FSR0 to address data memory value of FSR2 post-decremented (not a physical register) --------
FDCh PREINC2 Uses contents of FSR0 to address data memory value of FSR2 pre-incremented (not a physical register) --------
FDBh PLUSW2 Uses contents of FSR0 to address data memory value of FSR2 pre-incremented (not a physical register) value of --------
FSR0 offset by W
FDAh FSR2H Indirect Data Memory Address Pointer 2 High ----xxxx
FD7h PCON0 STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR 0011110q
FD4h TMR0H Holding Register for the Most Significant Byte of the 16-bit TMR0 Register 11111111
FD3h TMR0L Holding Register for the Least Significant Byte of the 16-bit TMR0 Register 00000000
FCEh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register 00000000
FCDh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register 00000000
FC8h TMR3H Holding Register for the Most Significant Byte of the 16-bit TMR3 Register 00000000
FC7h TMR3L Holding Register for the Least Significant Byte of the 16-bit TMR3 Register 00000000
FC2h TMR5H Holding Register for the Most Significant Byte of the 16-bit TMR5 Register 00000000
FC1h TMR5L Holding Register for the Least Significant Byte of the 16-bit TMR5 Register 00000000
FBBh T2TMR Holding Register for the 8-bit TMR2 Register 00000000
FB5h T4TMR Holding Register for the 8-bit TMR4 Register 00000000
FAFh T6TMR Holding Register for the 8-bit TMR6 Register 00000000
F9Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 00000010
F9Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 00000000
F98h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 00000000
F97h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 00000000
F90h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxxxxxx
F8Fh PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxxxxxx
F8Eh PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxxxxxx
F8Dh PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxxxxxx
F8Bh TRISD(2) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 11111111
F8Ah TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 11111111
F89h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 11111111
F88h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 11111111
(2) (2)
F87h LATE LATE2 LATE1 LATE0 -----xxx
(2)
F86h LATD LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxxxxxx
F85h LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxxxxxx
F84h LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxxxxxx
F83h LATA LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxxxxxx
F48h CWG1STR OVRD OVRC OVRB OVRA STRD STRC STRB STRA 00000000
F26h ANSELD(2) ANSELD7 ANSELD6 ANSELD5 ANSELD4 ANSELD3 ANSELD2 ANSELD1 ANSELD0 11111111
(2)
F25h WPUD WPUD7 WPUD6 WPUD5 WPUD4 WPUD3 WPUD2 WPUD1 WPUD0 00000000
(2)
F24h ODCOND ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 00000000
F23h SLRCOND(2) SLRD7 SLRD6 SLRD5 SLRD4 SLRD3 SLRD2 SLRD1 SLRD0 11111111
F22h INLVLD(2) INLVLD7 INLVLD6 INLVLD5 INLVLD4 INLVLD3 INLVLD2 INLVLD1 INLVLD0 10000000
F21h ANSELC ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 11111111
F20h WPUC WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 00000000
F1Fh ODCONC ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 00000000
F1Eh SLRCONC SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 11111111
F1Dh INLVLC INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 11111111
F1Ch IOCCP IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 00000000
F1Bh IOCCN IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 00000000
F1Ah IOCCF IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 00000000
F19h ANSELB ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 11111111
F18h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 00000000
F17h ODCONB ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 00000000
F16h SLRCONB SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 11111111
F15h INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 11111111
F14h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 00000000
F13h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 00000000
F12h IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 00000000
F11h ANSELA ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 11111111
F10h WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 00000000
F0Fh ODCONA ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 00000000
F0Eh SLRCONA SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 11111111
F0Dh INLVLA INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 11111111
F0Ch IOCAP IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 00000000
F0Bh IOCAN IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 00000000
F0Ah IOCAF IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 00000000
(2)
F09h RE2PPS RE2PPS<4:0> ---00000
EE2h PMD1 TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD -0000000
EE1h PMD0 SYSCMD FVRMD HLVDMD CRCMD SCANMD NVMMD CLKRMD IOCMD 00x00000
EDBh OSCSTAT EXTOR HFOR MFOR LFOR SOR ADOR PLLR qqqqqq-q
ECDh PIR3 RC2IF TX2IF RC1IF TX1IF BCL2IF SSP2IF BCL1IF SSP1IF 00000000
EC5h PIE3 RC2IE TX2IE RC1IE TX1IE BCL2IE SSP2IE BCL1IE SSP1IE 00000000
EBDh IPR3 RC2IP TX2IP RC1IP TX1IP BCL2IP SSP2IP BCL1IP SSP1IP 11111111
E9Eh TX2STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 00000010
E9Dh RC2STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 00000000
E98h SSP2CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 00000000
E97h SSP2CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 00000000
E8Ch
Unimplemented
E7Eh
Legend: x = unknown, u = unchanged, = unimplemented, q = value depends on condition
Note 1: Not available on LF devices.
2: Not available on PIC18(L)F26K40 (28-pin variants).
3: Not available on PIC18(L)F45K40 devices.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
000h
When a = 0 and f 60h:
060h
The instruction executes in
Direct Forced mode. f is inter- Bank 0
BSR
When a = 1 (all values of f): 000h 00000000
FIGURE 10-8: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING
Example Situation:
ADDWF f, d, a 000h
FSR2H:FSR2L = 120h
Bank 0
Locations in the region
from the FSR2 pointer 100h
(120h) to the pointer plus Bank 1
120h
05Fh (17Fh) are mapped Window
17Fh 00h
to the bottom of the
Bank 1
Access RAM (000h-05Fh). 200h Bank 1 Window
Special File Registers at 5Fh
60h
F60h through FFFh are
mapped to 60h through Bank 2
FFh, as usual. SFRs
through
Bank 0 addresses below Bank 14
5Fh can still be addressed FFh
by using the BSR. Access Bank
F00h
Bank 15
F60h
SFRs
FFFh
Data Memory
00 0000h
User Flash Memory Read/
Read 10 (3)
(PFM) Write(1)
01 FFFFh
20 0000h
Read/
User IDs(2) No Access x1 (3)
Write
20 000Fh
20 0010h
Reserved No Access (3)
2F FFFFh
30 0000h
Read/
Configuration No Access x1 (3)
Write
30 000Bh
30 000Ch
Reserved No Access (3)
30 FFFFh
31 0000h
User Data Memory Read/
No Access 00 (3)
(Data EEPROM) Write
31 03FFh
32 0000h
Reserved No Access (3)
3F FFFBh
3F FFFCh
Revision ID/
No Access x1 Read (3)
Device ID
3F FFFFh
Program Memory
Table Pointer(1)
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Program Memory
(TBLPTR)
Program Memory
(TBLPTR<MSBs>)
Note 1: During table writes the Table Pointer does not point directly to program memory. The LSBs of TBLPRTL
actually point to an address within the write block holding registers. The MSBs of the Table Pointer deter-
mine where the write block will eventually be written. The process for writing the holding registers to the
program memory array is discussed in Section 11.1.6 Writing to Program Flash Memory.
TABLE 11-3: TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Example Operation on Table Pointer
TBLRD*
TBLPTR is not modified
TBLWT*
TBLRD*+
TBLPTR is incremented after the read/write
TBLWT*+
TBLRD*-
TBLPTR is decremented after the read/write
TBLWT*-
TBLRD+*
TBLPTR is incremented before the read/write
TBLWT+*
Program Memory
Start
Read Operation
Select PFM
(NVMREG<1:0> = 0x10)
End
Read Operation
Note 1: Sequence begins when NVMCON2 is written; steps 1-4 must occur in the cycle-accurate order
shown. If the timing of the steps 1 to 4 is corrupted by an interrupt or a debugger Halt, the action
will not take place.
2: Opcodes shown are illustrative; any instruction that has the indicated effect may be used.
TABLAT
Write Register
8 8 8 8
Program Memory
Note 1: Refer to Table 11-3 for number of holding registers (e.g., YY = 3F for 64 holding registers).
Rev. 10-000049B
12/4/2015
Start
Write Operation
Determine number of
words to be written into Load the value to write
PFM. The number of TABLAT
words cannot exceed the
number of words per row
(word_cnt)
Disable Interrupts
Select Write Operation (GIE = 0)
(FREE = 0)
CPU stalls while Write
operation completes
(2 ms typical)
Load Write Latches Only Unlock Sequence(1)
Enable Write/Erase
Operation (WREN = 1) No delay when writing to Re-enable Interrupts
PFM Latches (GIE = 1)
Disable Write/Erase
Operation (WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
Increment Address
TBLPTR++
TABLE 11-4: USER ID, DEV/REV ID AND CONFIGURATION WORD ACCESS (NVMREG<1:0> = X1)
Address Function Read Access Write Access
20 0000h-20 000Fh User IDs Yes Yes
3F FFFCh-3F FFFFh Revision ID/Device ID Yes No
30 0000h-30 000Bh Configuration Words 1-6 Yes Yes
//The following 4 lines of code are not needed if the part doesn't have NVMADRH register
INCF NVMADRH, F ; Decrement address high byte
MOVLW 0x03 ; Move 0x03 to working register
CPFSGT NVMADRH ; Compare address high byte with working register
BRA Loop ; Skip if greater than working register
; Else go back to erase loop
Legend:
R = Readable bit W = Writable bit HC = Bit is cleared by hardware
x = Bit is unknown -n = Value at POR S = Bit can be set by software, but not cleared
0 = Bit is cleared 1 = Bit is set U = Unimplemented bit, read as 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
x = Bit is unknown 0 = Bit is cleared 1 = Bit is set
-n = Value at POR
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
x = Bit is unknown 0 = Bit is cleared 1 = Bit is set
-n = Value at POR
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
x = Bit is unknown 0 = Bit is cleared 1 = Bit is set
-n = Value at POR
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
x = Bit is unknown 0 = Bit is cleared 1 = Bit is set
-n = Value at POR
bit 7-0 NVMDAT<7:0>: The value of the data memory word returned from NVMADR after a Read command,
or the data written by a Write command.
12.2 Operation
Example 12-1 shows the instruction sequence for an
8x8 unsigned multiplication. Only one instruction is
required when one of the arguments is already loaded in
the WREG register.
Example 12-2 shows the sequence to do an 8x8 signed
multiplication. To account for the sign bits of the
arguments, each arguments Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Note 1: Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content.
2: This bit is cleared when LADR > HADR (and a data cycle is not occurring).
3: If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.
4: BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.
5: See Table 13-2 for more detailed information.
6: An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls over. An
invalid address can also occur if the value in the Scan Low address registers points to a location that is not
mapped in the memory map of the device.
7: CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to Section 13.9 Program Memory
Scan Configuration.
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access;
registers should only be read or written while SCANGO = 0 (SCANCON0 register).
2: While SCANGO = 1 (SCANCON0 register), writing to this register is ignored.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Registers SCANHADRU/H/L form a 22-bit value but are not guarded for atomic or asynchronous access;
registers should only be read or written while SCANGO = 0 (SCANCON0 register).
2: While SCANGO = 1 (SCANCON0 register), writing to this register is ignored.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
1111-1001 = Reserved
1000 = TMR6_postscaled
0111 = TMR5_output
0110 = TMR4_postscaled
0101 = TMR3_output
0100 = TMR2_postscaled
0011 = TMR1_output
0010 = TMR0_output
0001 = CLKREF_output
0000 = LFINTOSC
CRC-16-ANSI
x16 + x15 + x2 + 1 (17 bits)
Standard 16-bit representation = 0x8005
CRCXORH = 0b10000000
CRCXORL = 0b0000010- (1)
Data Sequence:
0x55, 0x66, 0x77, 0x88
DLEN = 0b0111
PLEN = 0b1111
Rev. 10-000207A
Linear Feedback Shift Register for CRC-16-ANSI 5/27/2014
x16 + x15 + x2 + 1
Data in
Augmentation Mode ON
Data in
Augmentation Mode OFF
13.5 CRC Data Sources The CRC module can be seeded with an initial value by
setting the CRCACC<15:0> registers to the
Data can be input to the CRC module in two ways: appropriate value before beginning the CRC.
- User data using the CRCDATA registers
(CRCDATH and CRCDATL) 13.5.1 CRC FROM USER DATA
- Flash using the Program Memory Scanner To use the CRC module on data input from the user, the
To set the number of bits of data, up to 16 bits, the user must write the data to the CRCDAT registers. The
DLEN bits of CRCCON1 must be set accordingly. Only data from the CRCDAT registers will be latched into the
data bits in CRCDATA registers up to DLEN will be shift registers on any write to the CRCDATL register.
used, other data bits in CRCDATA registers will be
13.5.2 CRC FROM FLASH
ignored.
To use the CRC module on data located in Flash
Data is moved into the CRCSHIFT as an intermediate
memory, the user can initialize the Program Memory
to calculate the check value located in the CRCACC
Scanner as defined in Section 13.9, Program Memory
registers.
Scan Configuration.
The SHIFTM bit is used to determine the bit order of the
data being shifted into the accumulator. If SHIFTM is
not set, the data will be shifted in MSb first (Big Endian).
The value of DLEN will determine the MSb. If SHIFTM
bit is set, the data will be shifted into the accumulator in
reversed order, LSb first (Little Endian).
Rev. 10-000010B
5/4/2016
Wake-up if in
Idle or Sleep
PIR0 modes
PIE0
IPR0
PIR1 Interrupt to
PIE1 CPU Vector at
IPR1 Location 0008h
PIR2
PIE2 GIEH/GIE
IPR2
IPEN
IPEN
GIEL/PEIE
PIRx IPEN
PIEx
IPRx
PIR1
PIE1
IPR1
PIR2
PIE2
IPR2
PIR0 Interrupt to
PIE0 CPU Vector at
IPR0 Location 0018h
PIRx GIEH/GIE
PIEx
IPRx GIEL/PEIE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: Interrupts are not disabled by the PEIE bit in the INTCON register.
2: IOCIF is a read-only bit, to clear the interrupt condition, all bits in the IOCF register must be cleared.
3: The external interrupt GPIO pin is selected by the INTPPS register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The CSWIF interrupt will not wake the system from Sleep. The system will sleep until another interrupt
causes the wake-up.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend: IE
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: PIR0 interrupts are not disabled by the PEIE bit in the INTCON register. are not disabled by the PEIE bit
in the INTCON register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
PORTE
PORTB
PORTC
PORTD
PORTA
Read LATx
TRISx
Device
D Q
15.3.4 INTERRUPT-ON-CHANGE
The interrupt-on-change feature is available only on the
RE3 pin for all devices. For further details refer to
Section 14.11 Interrupt-on-Change.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Note 1: Writes to PORTx are actually written to the corresponding LATx register.
Reads from PORTx register return actual I/O pin values.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
1 = Bit is set 0 = Bit is cleared x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
IOCANx D Q
R Q4Q1
edge
detect
RAx
to data bus
data bus = S
IOCAFx
IOCAPx D Q
0 or 1
D Q
R
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1 Q1 Q1
Q2 Q2 Q2
Q3 Q3 Q3
Q4 Q4 Q4
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS - Bit is set in hardware
RA0PPS
abcPPS
RA0
RA0
Peripheral abc
RxyPPS
Rxy
Peripheral xyz
RE2PPS
RD7(1)
xyzPPS
RE2(1)
; Enable Interrupts
BSF INTCON,GIE
Legend:
R = Readable bit W = Writable bit -n/n = Value at POR and BOR/Value at all other Resets
u = Bit is unchanged x = Bit is unknown q = value depends on peripheral
1 = Bit is set U = Unimplemented bit, m = value depends on default location for that input
0 = Bit is cleared read as 0
Note 1: The Reset value m of this register is determined by device default locations for that input.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Device Configuration
RxyPPS<4:0> Pin Rxy Output Source
PIC18(L)F26K40 PIC18(L)F45/46K40
5b1 0111 ADGRDB A C A C
5b1 0110 ADGRDA A C A C
5b1 0101 DSM A C A D
5b1 0100 CLKR B C B C
5b1 0011 TMR0 B C B C
5b1 0010 MSSP2 (SDO/SDA) B C B D
5b1 0001 MSSP2 (SCK/SCL) B C B D
5b1 0000 MSSP1 (SDO/SDA) B C B C
5b0 1111 MSSP1 (SCK/SCL) B C B C
5b0 1110 CMP2 A C A E
5b0 1101 CMP1 A C A D
5b0 1100 EUSART2 (RX) B C B D
5b0 1011 EUSART2 (TX) B C B D
5b0 1010 EUSART1 (RX) B C B C
5b0 1001 EUSART1 (TX) B C B C
5b0 1000 PWM4 A C A C
5b0 0111 PWM3 A C A D
5b0 0110 CCP2 B C B C
5b0 0101 CCP1 B C B C
5b0 0100 CWG1D B C B D
5b0 0011 CWG1C B C B D
5b0 0010 CWG1B B C B D
5b0 0001 CWG1A B C B C
5b0 0000 LATxy A B C A B C D E
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Reserved 111
Reserved 110 T0_match
Peripherals
SOSC 101 T0CKPS<3:0> TMR0
LFINTOSC 100 body T0OUTPS<3:0> T0IF
Prescaler 1
HFINTOSC 011 IN OUT Postscaler T0_out
SYNC 0
FOSC/4 010
PPS 001 FOSC/4 T016BIT TMR0
T0ASYNC D Q PPS
000
T0CKIPPS CK Q RxyPPS
T0CS<2:0>
8-bit TMR0 Body Diagram (T016BIT = 0) 16-bit TMR0 Body Diagram (T016BIT = 1)
Read TMR0L
COMPARATOR OUT
Write TMR0L
T0_match 8
8 TMR0H
TMR0 High
Byte
Latch 8
Enable
TMR0H
8
Internal Data Bus
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
4
TxGPPS
TxGSPM
PPS 0000
1
0 Single Pulse D Q TxGVAL
NOTE (5) 0
1111
1 Acq. Control
Q1
D Q
TxGPOL TxGGO/DONE
CK Q
TMRxON Interrupt
set bit
R
TxGTM det TMRxGIF
TMRxGE
set flag bit
TMRxIF
TMRxON
EN
(2) To Comparators (6)
TMRx
Tx_overflow Synchronized Clock Input
TMRxH TMRxL Q D 0
1
TxCLK
TxSYNC
TMRxCLK<3:0>
4
TxCKIPPS
(1)
PPS 0000
Prescaler
Synchronize(3)
1,2,4,8
Note (4) det
1111
2
Fosc/2
TxCKPS<1:0> Internal Sleep
Clock Input
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared u = unchanged
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared u = unchanged
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared u = unchanged
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Timer1/3/5 Gate Toggle mode is enabled by setting the 19.8.5 TIMER1/3/5 GATE VALUE STATUS
GTM bit of the TxGCON register. When the GTM bit is
cleared, the flip-flop is cleared and held clear. This is When Timer1/3/5 Gate Value Status is utilized, it is
necessary in order to control which edge is measured. possible to read the most current level of the gate
control value. The value is stored in the GVAL bit in the
Note: Enabling Toggle mode at the same time TxGCON register. The GVAL bit is valid even when the
as changing the gate polarity may result in Timer1/3/5 gate is not enabled (GE bit is cleared).
indeterminate operation.
19.8.6 TIMER1/3/5 GATE EVENT
INTERRUPT
When Timer1/3/5 Gate Event Interrupt is enabled, it is
possible to generate an interrupt upon the completion
of a gate event. When the falling edge of GVAL occurs,
the TMRxGIF flag bit in the PIR5 register will be set. If
the TMRxGIE bit in the PIE5 register is set, then an
interrupt will be recognized.
The TMRxGIF flag bit operates even when the
Timer1/3/5 gate is not enabled (GE bit is cleared).
For more information on selecting high or low priority
status for the Timer1/3/5 Gate Event Interrupt see Sec-
tion 14.0 Interrupts.
TxCKI = 1
when TMRx
Enabled
TxCKI = 0
when TMRx
Enabled
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
TMRxGE
TxGPOL
TxGTM
TxTxG_IN
TxCKI
TxGVAL
TMRxGE
TxGPOL
TxGSPM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
Cleared by
TMRxGIF Cleared by software Set by hardware on software
falling edge of TxGVAL
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by hardware on
TxGGO/ Set by software falling edge of TxGVAL
DONE Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TxCLK <3:0>
TXINPPS
TXIN PPS 0000
See TMRx_clk
TxCLKCON
Register
1111
TxINPPS
TxIN PPS TxMODE<4:0> MODE<3>
enable MODE<4:3>=01
Clear ON
MODE<4:1>=1011 D Q
TxCPOL
TMRx_clk Prescaler 0
R
TMRx
Set flag bit
3 Sync 1 TMRxIF
4
TxON Sync
(2 Clocks)
1
PRx TxOUTPS<3:0>
0
TxCSYNC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Note 1: In certain modes, the TxON bit will be auto-cleared by hardware. See Section 20.5.1 One-Shot Mode.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: Setting this bit ensures that reading TMRx will return a valid data value.
2: When this bit is 1, Timer2 cannot operate in Sleep mode.
3: CKPOL should not be changed while ON = 1.
4: Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
5: When this bit is set then the timer operation will be delayed by two TMRx input clocks after the ON bit is set.
6: Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without
affecting the value of TMRx).
7: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.
Note 1: When TMRx = PRx, the next clock clears TMRx, regardless of the operating mode.
2: In all operating modes, TxON = 0 stops the counter without affecting the value of TMRx
3: In edge-triggered one-shot and monostable modes (not SW Start mode), the triggered-start mechanism is reset and
rearmed (prepared for next start) if TxON becomes 0 (zero); the counter will not restart until an input edge occurs.
4: When TMRx = PRx, the next clock clears TxON.
5: When TMRx = PRx, TxON is not cleared.
6: Both TxON and TMRx_ers are subject to clock sync delays.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
CKPS 0b010
PRx 1
OUTPS 0b0001
TMRx_clk
TMRx 0 1 0 1 0 1 0
TMRx_postscaled
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.
MODE 0b00000
TMRx_clk
ON
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
MODE 0b00001
TMRx_clk
TMRx_ers
PRx 5
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
MODE 0b00100
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
MODE 0b00111
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
MODE 0b01000
TMRx_clk
PRx 5
ON
TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions
executed by the CPU to set or clear the ON bit of TxCON. CPU
execution is asynchronous to the timer clock input.
MODE 0b01001
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2
TMRx_out
TMRx_postscaled
PWM Duty
3
Cycle
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
MODE 0b01100
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0
TMRx_postscaled
Preliminary
PWM Duty
3
Cycle
PIC18(L)F26/45/46K40
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40001816C-page 259
PIC18(L)F26/45/46K40
20.6.8 LEVEL TRIGGERED HARDWARE
LIMIT ONE-SHOT MODES
In Level Triggered One-Shot mode the timer count is
reset on the external signal level and starts counting
when the external signal level relinquishes the Reset.
Reset levels are selected as follows:
High Reset level (MODE<4:0> = 01110)
Low Reset level (MODE<4:0> = 01111)
When the timer count matches the PRx period count
then the timer is reset and the ON bit is cleared. When
the ON bit is cleared by either a PRx match or by soft-
ware control a new external signal edge is required
after the ON bit is set to start the counter.
When Level Triggered Reset One-Shot mode is used in
conjunction with the CCP PWM operation the PWM
drive goes active with the external signal edge that
starts the timer. The PWM drive goes inactive when the
timer count equals the CCPRx pulse-width count. The
PWM drive does not go active when the timer count
clears at the PRx period count match.
MODE 0b1110
TMRx_clk
PRx 5
ON
TMRx_ers
TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0
TMRx_postscaled
Preliminary
PWM Duty
3
Cycle
PIC18(L)F26/45/46K40
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
DS40001816C-page 261
PIC18(L)F26/45/46K40
TABLE 20-3: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
CCPTMRS P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> 266
INTCON GIE/GIEH PEIE/GIEL IPEN INT2EDG INT1EDG INT0EDG 169
PIE4 TMR6IE TMR5IE TMR4IE TMR3IE TMR2IE TMR1IE 182
PIR4 TMR6IF TMR5IF TMR4IF TMR3IF TMR2IF TMR1IF 174
IPR4 TMR6IP TMR5IP TMR4IP TMR3IP TMR2IP TMR1IP 190
PMD1 TMR6MD TMR5MD TMR4MD TMR3MD TMR2MD TMR1MD TMR0MD 68
PR2 Timer2 Module Period Register 250*
TMR2 Holding Register for the 8-bit TMR2 Register 250*
T2CON ON CKPS<2:0> OUTPS<3:0> 245
T2CLKCON CS<2:0> 248
T2RST RSEL<3:0> 249
T2HLT PSYNC CPOL CSYNC MODE<4:0> 246
PR4 Timer4 Module Period Register 250*
TMR4 Holding Register for the 8-bit TMR4 Register 250*
T4CON ON CKPS<2:0> OUTPS<3:0> 245
T4CLKCON CS<2:0> 248
T4RST RSEL<3:0> 249
T4HLT PSYNC CPOL CSYNC MODE<4:0> 246
PR6 Timer6 Module Period Register 250*
TMR6 Holding Register for the 8-bit TMR6 Register 250*
T6CON ON CKPS<2:0> OUTPS<3:0> 245
T6CLKCON CS<2:0> 248
T6RST RSEL<3:0> 249
T6HLT PSYNC CPOL CSYNC MODE<4:0> 246
T2INPPS T2INPPS<4:0> 215
T4INPPS T4INPPS<4:0> 215
T6INPPS T6INPPS<4:0> 215
Legend: = unimplemented location, read as 0. Shaded cells are not used for Timer2 module.
* Page provides register information.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The set and clear operations of the Compare mode are reset by setting MODE = 4b0000 or EN = 0.
2: When MODE = 0001 or 1011, then the timer associated with the CCP module is cleared. TMR1 is the
default selection for the CCP module, so it is used for indication purpose only.
Operating
MODE Operation Set CCPxIF
Mode
11xx PWM PWM operation Yes
1011 Pulse output; clear TMR1(2) Yes
1010 Pulse output Yes
Compare
1001 Clear output(1) Yes
1000 Set output(1) Yes
0111 Every 16th rising edge of CCPx input Yes
0110 Every 4th rising edge of CCPx input Yes
0101 Capture Every rising edge of CCPx input Yes
0100 Every falling edge of CCPx input Yes
0011 Every edge of CCPx input Yes
0010 Toggle output Yes
Compare
0001 Toggle output; clear TMR1(2) Yes
0000 Disabled
Note 1: The set and clear operations of the Compare mode are reset by setting MODE = 4b0000 or EN = 0.
2: When MODE = 0001 or 1011, then the timer associated with the CCP module is cleared. TMR1 is the
default selection for the CCP module, so it is used for indication purpose only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Connection
CTS<1:0>
CCP1 CCP2
11 IOC_Interrupt
10 CMP2_output
01 CMP1_output
00 Pin selected by CCP1PPS Pin selected by CCP2PPS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
RxyPPS
CCPx
PPS
TRIS Control
CCPxCTS<1:0>
CCPRxH CCPRxL
IOC_interrupt 11 16
C2OUT_sink set ccpxif
10 Prescaler and
C1OUT_sink 01 1,4,16 Edge Detect
PPS 00 16
CCPxMODE<3:0> TMR1H TMR1L
CCPxPPS
Pulse Width
TMR2 = PR2
TMR2 = CCPRxH:CCPRxL
TMR2 = 0
CCPRxH CCPRxL
CCPx_out
To Peripherals
set CCPIF
10-bit Latch(2)
(Not accessible by user)
S RxyPPS
TMR2 Module TRIS Control
R
TMR2 (1)
ERS logic
Comparator CCPx_pset
PR2
Notes: 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit.
CCPRxH CCPRxL
FMT = 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
PWMxDCH
Latched PWMxOUT
(Not visible to user)
to other peripherals
Comparator R Q 0
PPS PWMx
S Q 1
RxyPPS
TMR2 Module
Comparator
Clear Timer,
PR2 PWMx pin and
latch Duty Cycle
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to
create a 10-bit time base.
FIGURE 22-2: PWM OUTPUT For a step-by-step procedure on how to set up this
module for PWM operation, refer to Section
Period 22.1.9 Setup for PWM Operation using PWMx
Pins.
Pulse Width
TMR2 = PR2
TMR2 =
PWMxDCH<7:0>:PWMxDCL<7:6>
TMR2 = 0
PWMxDCH:PWMxDCL<7:6>
Duty Cycle Ratio = -----------------------------------------------------------------------------------
4 PR2 + 1
log 4 PR2 + 1
Resolution = ------------------------------------------ bits
log 2
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
optional
VDD RPULLUP
- ZCDxIN RSERIES
External
Zcpinv + RPULLDOWN voltage
source
optional
ZCDx_output
D Q ZCDxOUT bit
ZCDxPOL
Q1
Interrupt
det
ZCDxINTP Set
ZCDIF
ZCDxINTN flag
Interrupt
det
asin ---------------------------------
An interrupt will be generated upon a change in the V DD V CPINV
ZCD logic output when the appropriate interrupt V PEAK
enables are set. A rising edge detector and a falling T OFFSET = -------------------------------------------------
edge detector are present in the ZCD for this purpose. 2 Freq
The ZCDIF bit of the PIR2 register will be set when
either edge detector is triggered and its associated This offset time can be compensated for by adding a
enable bit is set. The ZCDINTP enables rising edge pull-up or pull-down biasing resistor to the ZCD pin. A
interrupts and the ZCDINTN bit enables falling edge pull-up resistor is used when the external voltage
interrupts. Both are located in the ZCDCON register. source is varying relative to VSS. A pull-down resistor is
Priority of the interrupt can be changed if the IPEN bit used when the voltage is varying relative to VDD. The
of the INTCON register is set. The ZCD interrupt can be resistor adds a bias to the ZCD pin so that the target
made high or low priority by setting or clearing the external voltage source must go to zero to pull the pin
ZCDIP bit of the IPR2 register. voltage to the VCPINV switching voltage. The pull-up or
To fully enable the interrupt, the following bits must be set: pull-down value can be determined with the equations
shown in Equation 23-3 or Equation 23-4.
ZCDIE bit of the PIE2 register
ZCDINTP bit of the ZCDCON register EQUATION 23-3: ZCD PULL-UP/DOWN
(for a rising edge detection)
ZCDINTN bit of the ZCDCON register When External Signal is relative to Vss:
(for a falling edge detection)
R SERIE S V PULLUP V CPINV
PEIE and GIE bits of the INTCON register R PULLUP = --------------------------------------------------------------------------
V CPINV
Changing the ZCDPOL bit will cause an interrupt,
regardless of the level of the ZCDSEN bit.
When External Signal is relative to VDD:
The ZCDIF bit of the PIR2 register must be cleared in
software as part of the interrupt service. If another edge R SERIES V CPINV
is detected while this flag is being cleared, the flag will
R PULLDOWN = ---------------------------------------------
V DD V CPINV
still be set at the end of the sequence.
V MAXPEAK + V MINPEAK
R SERIES = ---------------------------------------------------------
4
7 10
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
The CWG generates two output waveforms from the The unused outputs CWG1C and CWG1D drive similar
selected input source. signals, with polarity independently controlled by the
POLC and POLD bits of the CWG1CON1 register,
The off-to-on transition of each output can be delayed respectively.
from the on-to-off transition of the other output, thereby,
creating a time delay immediately where neither output
is driven. This is referred to as dead time and is covered
in Section 24.6 Dead-Band Control.
It may be necessary to guard against the possibility of
circuit faults or a feedback event arriving too late or not
at all. In this case, the active drive must be terminated
before the Fault condition causes damage. This is
referred to as auto-shutdown and is covered in Section
24.10 Auto-Shutdown.
FIGURE 24-1: SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE, MODE<2:0> = 100)
1 00
0 01
High-Z 10
11
Rising Dead-Band Block
CWG Clock clock 1
CWG Data A
data out
CWG Data data in 0 CWG1A
POLA
LSBD<1:0>
E LSAC<1:0>
EN 1 00
0 01
High-Z 10
SHUTDOWN = 1
11
AS0E
PPS
CWG1PPS 1
Auto-
AS1E shutdown 0 CWG1C
POLC
TMR2_postscaled source
AS2E LSBD<1:0>
TMR4_postscaled
AS3E
TMR6_postscaled 1 00
0 01
AS4E
CMP1OUT High-Z 10
AS5E 11
S Q
CMP2OUT
R 1
0 CWG1D
REN POLD
SHUTDOWN = 0
SHUTDOWN
FREEZE
D Q
CWG Data
CWGx_clock
CWGxA
CWGxC
Rising Event Dead Band Rising Event D
Falling Event Dead Band Falling Event Dead Band
CWGxB
CWGxD
CWGx_data
Note: CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out
FIGURE 24-3: SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE, MODE<2:0> = 101)
LSAC<1:0>
Rev. 10-000210C
8/7/2015
1 00
0 01
High-Z 10
11
1
CWG Data CWG Data A
0 CWG1A
POLA
LSBD<1:0>
D Q
Q
1 00
0 01
High-Z 10
CWG Data B 11
1
CWG Data Input CWG 0 CWG1B
POLB
Data
D Q
LSAC<1:0>
E
1 00
EN 0 01
High-Z 10
11
SHUTDOWN = 1
AS0E 1
PPS
CWG1PPS 0 CWG1C
Auto- POLC
AS1E shutdown
TMR2_postscaled source
LSBD<1:0>
AS2E
TMR4_postscaled
1 00
AS3E
TMR6_postscaled 0 01
High-Z 10
AS4E
CMP1OUT 11
S Q
AS5E
CMP2OUT R 1
0 CWG1D
REN POLD
SHUTDOWN = 0
SHUTDOWN
FREEZE
D Q
CWG Data
CWG1
clock
Input
source
CWG1A
CWG1B
VDD
FET QA QC
FET
Driver Driver
CWG1A
CWG1B LOAD
CWG1D QB QD
FIGURE 24-6: SIMPLIFIED CWG BLOCK DIAGRAM (FORWARD AND REVERSE FULL-BRIDGE
MODES)
LSAC<1:0>
MODE<2:0> = 011: Reverse
1 00
Rising Dead-Band Block 0 01
CWG Clock clock
signal out High-Z 10
signal in 11
CWG 1
CWG Data A
Data
MODE<2:0> 0 CWG1A
POLA
D Q
CWG Q LSBD<1:0>
Data
cwg data 1 00
signal in 0 01
signal out
CWG Clock clock High-Z 10
1
CWG Data Input CWG Data B
CWG Data
0 CWG1B
POLB
D Q
E LSAC<1:0>
1 00
EN
0 01
High-Z 10
SHUTDOWN = 1 11
AS0E
PPS CWG Data C
1
CWG1PPS 0 CWG1C
Auto-
POLC
AS1E shutdown
TMR2_postscaled source
LSBD<1:0>
AS2E
TMR4_postscaled
AS3E 1 00
TMR6_postscaled
0 01
AS4E High-Z 10
CMP1OUT
11
AS5E S Q
CMP2OUT
R
CWG Data D
1
0 CWG1D
REN POLD
SHUTDOWN = 0
SHUTDOWN
FREEZE
D Q
CWG Data
CWG1A(2)
CWG1B(2)
CWG1C(2)
Pulse Width
CWG1D(2)
(1) (1)
Reverse
Mode
Period
CWG1A(2)
Pulse Width
CWG1B(2)
CWG1C(2)
CWG1D(2)
(1) (1)
Note 1: A rising CWG data input creates a rising event on the modulated output.
2: Output signals shown as active-high; all POLy bits are clear.
FIGURE 24-8: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
t1
Forward Period Reverse Period
CWG1A
CWG1C
External Switch C
TOFF
External Switch D
CWG1
clock
Input
source
CWG1A
CWG1B
CWG1
INPUT
End of Instruction Cycle End of Instruction Cycle
STRA
CWG1A
Rev. 10-000211C
8/7/2015
1 00
0 01
High-Z 10
11
CWG Data A 1
1
POLA 0 CWG1A
0
DATA
STRA LSBD<1:0>
1 00
0 01
CWG
CWG Data Data High-Z 10
Input
11
D Q CWG Data B
1
E 1
POLB 0 CWG1B
0
DATB
EN
STRB LSAC<1:0>
1 00
0 01
SHUTDOWN = 1
High-Z 10
AS0E
PPS 11
CWG1PPS
Auto-
AS1E shutdown CWG Data C 1
TMR2_postscaled source 1
POLC 0 CWG1C
AS2E 0
DATC
TMR4_postscaled
STRC LSBD<1:0>
AS3E
TMR6_postscaled
AS4E 1 00
CMP1OUT 0 01
AS5E High-Z 10
CMP2OUT
11
S Q
CWG Data D
R 1
1
POLD 0 CWG1D
REN 0
SHUTDOWN = 0 DATD
SHUTDOWN
STRD
FREEZE
D Q
CWG Data
cwg_clock
Input Source
CWGxA
CWGxB
Preliminary
FIGURE 24-13: DEAD-BAND OPERATION, CWG1DBR = 0x03, CWG1DBF = 0x06, SOURCE SHORTER THAN DEAD BAND
PIC18(L)F26/45/46K40
cwg_clock
Input Source
CWGxA
DS40001816C-page 304
CWGxB
T
JITTER
= T
DEAD BAND _ MAX
TDEAD BAND _ MIN
1
T = --------------------------------------------
JITTER F
CWG _ CLOCK
T = T +T
DEAD BAND _ MAX DEAD BAND _ MIN JITTER
EXAMPLE
DBR<4:0> = 0x0A = 10
F = 8 MHz
CWG_CLOCK
1
T = ---------------- = 125 ns
JITTER 8MHz
T = 125 ns*10 = 125 s
DEAD BAND_MIN
SHUTDOWN bit
PPS
AS0E
CWGxINPPS
C1OUT_sync
AS4E
C2OUT_sync
AS5E
TMR2_postscaled SHUTDOWN S
S Q
AS1E D Q CWG_shutdown
TMR4_postscaled
REN FREEZE
R
AS2E Write 0 to
SHUTDOWN bit
TMR6_postscaled CWG_data CK
AS3E
FIGURE 24-15: SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01)
Preliminary
PIC18(L)F26/45/46K40
CWG Input
Source
Shutdown Source
SHUTDOWN
CWG Input
Source
Shutdown Source
SHUTDOWN
PIC18(L)F26/45/46K40
DS40001816C-page 309
PIC18(L)F26/45/46K40
24.14 Register Definitions: CWG Control
Long bit name prefixes for the CWG peripheral is
shown in Table 24-2. Refer to Section 1.4.2.2 Long
Bit Names for more information.
TABLE 24-2:
Peripheral Bit Name Prefix
CWG CWG
l
REGISTER 24-1: CWG1CON0: CWG CONTROL REGISTER 0
R/W-0/0 R/W/HC-0/0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0
EN LD(1) MODE<2:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Note 1: This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
CS Clock Source
1 HFINTOSC (remains operating during Sleep)
0 FOSC
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Note 1: The bits in this register apply only when MODE<2:0> = 00x (Register 24-1, Steering modes).
2: This bit is double-buffered when MODE<2:0> = 001.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS/HC = Bit is set/cleared by hardware
q = Value depends on condition
Note 1: This bit may be written while EN = 0 (Register 24-1), to place the outputs into the shutdown configuration.
2: The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this
bit is cleared.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
See
MDCARH CARH
Register
MDCHPOL D
111 SYNC
Q
MDSRCS<3:0> 1
0
0000
MDCHSYNC
RxyPPS
See MOD
MDSRC
PPS
Register
MDOPOL
1111
MDCLS<2:0>
D
SYNC
000 Q
1
0
See
MDCARL CARL
Register MDCLSYNC
MDCLPOL
111
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: The modulated output frequency can be greater and asynchronous from the clock that updates this
register bit, the bit value may not be valid for higher speed modulator or carrier signals.
2: MDBIT must be selected as the modulation source in the MDSRC register for this operation.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Modulator (MOD)
MDCHSYNC = 1
MDCLSYNC = 0
MDCHSYNC = 1
MDCLSYNC = 1
MDCHSYNC = 0
MDCLSYNC = 0
MDCHSYNC = 0
MDCLSYNC = 1
carrier_high
carrier_low
modulator
MDCHSYNC = 0
MDCLSYNC = 0
Active Carrier
carrier_high carrier_low carrier_high carrier_low
State
carrier_high
carrier_low
modulator
MDCHSYNC = 1
MDCLSYNC = 0
carrier_high
carrier_low
modulator
MDCHSYNC = 0
MDCLSYNC = 1
Active Carrier
State carrier_high carrier_low carrier_high carrier_low
carrier_high
carrier_low
Active Carrier
State carrier_high carrier_low carrier_high CL
25.7 Programmable Modulator Data Upon any device Reset, the DSM module is disabled.
The users firmware is responsible for initializing the
The MDBIT of the MDCON0 register can be selected module before enabling the output. The registers are
as the source for the modulator signal. This gives the reset to their default values.
user the ability to program the value used for modula-
tion. 25.11 Peripheral Module Disable
25.8 Modulated Output Polarity The DSM module can be completely disabled using the
PMD module to achieve maximum power saving. The
The modulated output signal provided on the DSM pin DSMMD bit of PMD5 (Register 7-6) when set disables
can also be inverted. Inverting the modulated output the DSM module completely. When enabled again all
signal is enabled by setting the MDOPOL bit of the the registers of the DSM module default to POR status.
MDCON0 register.
Data Bus
Read Write
SSPxBUF Reg
SSPxDATPPS
SDI
PPS SSPSR Reg
SDO bit 0 Shift
Clock
PPS
RxyPPS
Edge
SSPxSSPPS Select
SSPxCLKPPS(2) SSPM<3:0>
SCK PPS
4
( T2_match
2
)
Edge Prescaler TOSC
PPS Select 4, 16, 64
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
General I/O
General I/O SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by
writing to the SSPxBUF register.
2: When enabled, these pins must be properly configured as inputs or outputs.
3: SSPxADD = 0 is not supported.
4: Bit combinations not specifically listed here are either reserved or implemented in I2C mode only.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set HS/HC = Bit is set/cleared by hardware
x = Bit is unknown 0 = Bit is cleared
Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
2: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to
SSPxBUF.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Slave Select
General I/O SS
Processor 1 (optional) Processor 2
Write to
SSPxBUF
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
4 Clock
SCK Modes
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Input
Sample
(SMP = 1)
SSPxIF
SSPSR to
SSPxBUF
SCK SCK
SPI Master
SDO SDI SPI Slave
SDI SDO #1
General I/O SS
SCK
SDI SPI Slave
SDO #2
SS
SCK
SDI SPI Slave
SDO #3
SS
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Shift register SSPSR
and bit count are reset
SSPxBUF to
SSPSR
SDI bit 0
bit 7 bit 7
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
SS
Optional
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPxBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
SS
Not Optional
SCK
(CKP = 0
CKE = 1)
SCK
(CKP = 1
CKE = 1)
Write to
SSPxBUF
Valid
SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SDI
bit 7 bit 0
Input
Sample
SSPxIF
Interrupt
Flag
SSPSR to
SSPxBUF
Write Collision
detection active
Internal
data bus [SSPM<3:0>]
SSPxDATPPS(1) Read Write
SDA
SDA in
PPS SSPxBUF Baud Rate
Generator
(SSPxADD)
Shift
RxyPPS(1) Clock
Clock Cntl
PPS
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
Read Write
SSPxMSK Reg
(1)
SSPxDATPPS
SDA Match Detect Addr Match
PPS
SSPxADD Reg
PPS
Start and Set, Reset
RxyPPS(1) Stop bit Detect S, P bits
(SSPxSTAT Reg)
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
The I2C bus specifies two signal connections: If the requested slave exists on the bus, it will respond
Serial Clock (SCL) with an Acknowledge bit, otherwise known as an ACK.
The master then continues in either Transmit mode or
Serial Data (SDA)
Receive mode and the slave continues in the comple-
Both the SCL and SDA connections are bidirectional ment, either in Receive mode or Transmit mode,
open-drain lines, each requiring pull-up resistors for the respectively.
supply voltage. Pulling the line to ground is considered
A Start bit is indicated by a high-to-low transition of the
a logical zero and letting the line float is considered a
SDA line while the SCL line is held high. Address and
logical one.
data bytes are sent out, Most Significant bit (MSb) first.
Figure 26-11 shows a typical connection between two The Read/Write bit is sent out as a logical one when the
processors configured as master and slave devices. master intends to read data from the slave, and is sent
The I2C bus can operate with one or more master out as a logical zero when it intends to write data to the
devices and one or more slave devices. slave.
There are four potential modes of operation for a given
FIGURE 26-11: I2C MASTER/
device:
SLAVE CONNECTION
Master Transmit mode
(master is transmitting data to a slave)
VDD
Master Receive mode
(master is receiving data from a slave)
Slave Transmit mode SCL SCL
(slave is transmitting data to a master)
VDD
Slave Receive mode Master Slave
(slave is receiving data from the master)
To begin communication, a master device starts out in SDA SDA
Master Transmit mode. The master device sends out a
Start bit followed by the address byte of the slave it
intends to communicate with. This is followed by a
single Read/Write bit, which determines whether the The Acknowledge bit (ACK) is an active-low signal,
master intends to transmit to or receive data from the which holds the SDA line low to indicate to the transmit-
slave device. ter that the slave device has received the transmitted
data and is ready to receive more.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit HC = Bit is cleared by hardware
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: When enabled, the SDAx and SCLx pins must be configured as inputs.
2: Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
3: When SSPM<3:0> = 1001, any reads or writes to the SSPxADD SFR address actually accesses the
SSPxMSK register.
4: This mode is only available when 7-Bit Address Masking mode is selected (MSSPMSK Configuration bit
is 1).
Legend:
R = Readable bit W = Writable bit HC = Bit is cleared by hardware
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Note 1: The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a
receive.
2: If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written
(or writes to the SSPxBUF are disabled).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set HS/HC = Bit is set/cleared by hardware
x = Bit is unknown 0 = Bit is cleared
Note 1: This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
REGISTER 26-10: SSPxBUF: MSSP DATA BUFFER REGISTER (I2C MASTER MODE)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
BUF<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a dont care. Bit
pattern sent by master is fixed by I2C specification and must be equal to 11110. However, those bits
are compared by hardware and are not affected by the value in this register.
bit 2-1 ADD<9:8>: Two Most Significant bits of 10-bit Address
bit 0 Not used: Unused in this mode. Bit state is a dont care.
10-Bit Slave mode Least Significant Address Byte:
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
SDA
SCL
S P
Change of Change of
Data Allowed Data Allowed
Start Stop
Condition Condition
Sr
Change of Change of
Data Allowed Data Allowed
Restart
Condition
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
SSPxIF set on 9th
Cleared by software Cleared by software falling edge of
SCL
Preliminary
BF
First byte
SSPxBUF is read of data is
available
in SSPxBUF
PIC18(L)F26/45/46K40
SSPOV
SSPxIF
BF
First byte
of data is
SSPxBUF is read available
PIC18(L)F26/45/46K40
in SSPxBUF
SSPOV
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SSPxIF
If AHEN = 1: SSPxIF is set on
SSPxIF is set 9th falling edge of Cleared by software No interrupt
SCL, after ACK after not ACK
BF from Slave
Address is
read from Data is read from SSPxBUF
ACKDT SSBUF
Preliminary
Slave software
clears ACKDT to Slave software
ACK the received sets ACKDT to
byte not ACK
PIC18(L)F26/45/46K40
CKP
When AHEN=1:
When DHEN=1: CKP set by software,
CKP is cleared by hardware
CKP is cleared by SCL is released
and SCL is stretched hardware on 8th falling
edge of SCL
ACKTIM
S
DS40001816C-page 359
P
FIGURE 26-17: I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1)
2016 Microchip Technology Inc.
Master sends
Stop condition
Master releases
R/W = 0 SDA to slave for ACK sequence
Receiving Address Receive Data Receive Data ACK
SDA ACK
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SSPxIF
Cleared by software No interrupt after
if not ACK
from Slave
BF
Received
address is loaded into Received data is SSPxBUF can be
Preliminary
PIC18(L)F26/45/46K40
ACKDT to ACK not ACK
the received byte
CKP
When AHEN = 1; When DHEN = 1; CKP is not cleared
on the 8th falling edge on the 8th falling edge Set by software, if not ACK
of SCL of an address of SCL of a received release SCL
byte, CKP is cleared data byte, CKP is cleared
ACKTIM
S
DS40001816C-page 360
P
PIC18(L)F26/45/46K40
26.9.3 SLAVE TRANSMISSION 26.9.3.2 7-bit Transmission
When the R/W bit of the incoming address byte is set A master device can transmit a read request to a
and an address match occurs, the R/W bit of the slave, and then clock data out of the slave. The list
SSPxSTAT register is set. The received address is below outlines what software for a slave will need to
loaded into the SSPxBUF register, and an ACK pulse is do to accomplish a standard transmission.
sent by the slave on the ninth bit. Figure 26-18 can be used as a reference to this list.
Following the ACK, slave hardware clears the CKP bit 1. Master sends a Start condition on SDA and
and the SCL pin is held low (see Section SCL.
26.9.6 Clock Stretching for more detail). By 2. S bit of SSPxSTAT is set; SSPxIF is set if inter-
stretching the clock, the master will be unable to assert rupt on Start detect is enabled.
another clock pulse until the slave is done preparing 3. Matching address with R/W bit set is received by
the transmit data. the Slave setting SSPxIF bit.
The transmit data must be loaded into the SSPxBUF 4. Slave hardware generates an ACK and sets
register which also loads the SSPSR register. Then the SSPxIF.
SCL pin should be released by setting the CKP bit of 5. SSPxIF bit is cleared by user.
the SSPxCON1 register. The eight data bits are shifted
6. Software reads the received address from
out on the falling edge of the SCL input. This ensures
SSPxBUF, clearing BF.
that the SDA signal is valid during the SCL high time.
7. R/W is set so CKP was automatically cleared
The ACK pulse from the master-receiver is latched on after the ACK.
the rising edge of the ninth SCL input pulse. This ACK
8. The slave software loads the transmit data into
value is copied to the ACKSTAT bit of the SSPxCON2
SSPxBUF.
register. If ACKSTAT is set (not ACK), then the data
transfer is complete. In this case, when the not ACK is 9. CKP bit is set releasing SCL, allowing the
latched by the slave, the slave goes idle and waits for master to clock the data out of the slave.
another occurrence of the Start bit. If the SDA line was 10. SSPxIF is set after the ACK response from the
low (ACK), the next transmit data must be loaded into master is loaded into the ACKSTAT register.
the SSPxBUF register. Again, the SCL pin must be 11. SSPxIF bit is cleared.
released by setting bit CKP. 12. The slave software checks the ACKSTAT bit to
An MSSP interrupt is generated for each data transfer see if the master wants to clock out more data.
byte. The SSPxIF bit must be cleared by software and
Note 1: If the master ACKs the clock will be
the SSPxSTAT register is used to determine the status
stretched.
of the byte. The SSPxIF bit is set on the falling edge of
the ninth clock pulse. 2: ACKSTAT is the only bit updated on the
rising edge of SCL (9th) rather than the
26.9.3.1 Slave Mode Bus Collision falling.
A slave receives a Read request and begins shifting 13. Steps 9-13 are repeated for each transmitted
data out on the SDA line. If a bus collision is detected byte.
and the SBCDE bit of the SSPxCON3 register is set, 14. If the master sends a not ACK; the clock is not
the BCLxIF bit of the PIR register is set. Once a bus col- held, but SSPxIF is still set.
lision is detected, the slave goes idle and waits to be
15. The master sends a Restart condition or a Stop.
addressed again. User software can use the BCLxIF bit
to handle a slave bus collision. 16. The slave is no longer addressed.
Master sends
Stop condition
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S P
SSPxIF
Cleared by software
BF
BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCL
CKP
Preliminary
PIC18(L)F26/45/46K40
Masters not ACK
is copied to
ACKSTAT
R/W
R/W is copied from the
matching address byte
D/A
Indicates an address
has been received
S
DS40001816C-page 362
P
PIC18(L)F26/45/46K40
26.9.3.3 7-bit Transmission with Address
Hold Enabled
Setting the AHEN bit of the SSPxCON3 register
enables additional clock stretching and interrupt
generation after the eighth falling edge of a received
matching address. Once a matching address has
been clocked in, CKP is cleared and the SSPxIF
interrupt is set.
Figure 26-19 displays a standard waveform of a 7-bit
address slave transmission with AHEN enabled.
1. Bus starts Idle.
2. Master sends Start condition; the S bit of
SSPxSTAT is set; SSPxIF is set if interrupt on
Start detect is enabled.
3. Master sends matching address with R/W bit
set. After the eighth falling edge of the SCL line
the CKP bit is cleared and SSPxIF interrupt is
generated.
4. Slave software clears SSPxIF.
5. Slave software reads the ACKTIM bit of
SSPxCON3 register, and R/W and D/A of the
SSPxSTAT register to determine the source of
the interrupt.
6. Slave reads the address value from the
SSPxBUF register clearing the BF bit.
7. Slave software decides from this information if it
wishes to ACK or not ACK and sets the ACKDT
bit of the SSPxCON2 register accordingly.
8. Slave sets the CKP bit releasing SCL.
9. Master clocks in the ACK value from the slave.
10. Slave hardware automatically clears the CKP bit
and sets SSPxIF after the ACK if the R/W bit is
set.
11. Slave software clears SSPxIF.
12. Slave loads value to transmit to the master into
SSPxBUF setting the BF bit.
Note: SSPxBUF cannot be loaded until after the
ACK.
13. Slave sets the CKP bit releasing the clock.
14. Master clocks out the data from the slave and
sends an ACK value on the ninth SCL pulse.
15. Slave hardware copies the ACK value into the
ACKSTAT bit of the SSPxCON2 register.
16. Steps 10-15 are repeated for each byte transmit-
ted to the master from the slave.
17. If the master sends a not ACK the slave
releases the bus allowing the master to send a
Stop and end the communication.
Master sends
Master releases SDA Stop condition
to slave for ACK sequence
Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK
SDA
A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL
S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
P
SSPxIF
Cleared by software
BF BF is automatically
Received address Data to transmit is cleared after 8th falling
is read from SSPxBUF loaded into SSPxBUF edge of SCL
ACKDT
Preliminary
Slave clears
ACKDT to ACK
address
PIC18(L)F26/45/46K40
ACKSTAT
Masters ACK
response is copied
to SSPxSTAT
CKP
When AHEN = 1; CKP not cleared
CKP is cleared by hardware When R/W = 1; Set by software, after not ACK
after receiving matching CKP is always releases SCL
address. cleared after ACK
ACKTIM
ACKTIM is set on 8th falling ACKTIM is cleared
edge of SCL on 9th rising edge of SCL
R/W
DS40001816C-page 364
D/A
PIC18(L)F26/45/46K40
26.9.4 SLAVE MODE 10-BIT ADDRESS 26.9.5 10-BIT ADDRESSING WITH
RECEPTION ADDRESS OR DATA HOLD
This section describes a standard sequence of events Reception using 10-bit addressing with AHEN or
for the MSSP module configured as an I2C slave in DHEN set is the same as with 7-bit modes. The only
10-bit Addressing mode. difference is the need to update the SSPxADD register
Figure 26-20 is used as a visual reference for this using the UA bit. All functionality, specifically when the
description. CKP bit is cleared and SCL line is held low are the
same. Figure 26-21 can be used as a reference of a
This is a step by step process of what must be done by slave in 10-bit addressing with AHEN set.
slave software to accomplish I2C communication.
Figure 26-22 shows a standard waveform for a slave
1. Bus starts Idle. transmitter in 10-bit Addressing mode.
2. Master sends Start condition; S bit of SSPxSTAT
is set; SSPxIF is set if interrupt on Start detect is
enabled.
3. Master sends matching high address with R/W
bit clear; UA bit of the SSPxSTAT register is set.
4. Slave sends ACK and SSPxIF is set.
5. Software clears the SSPxIF bit.
6. Software reads received address from
SSPxBUF clearing the BF flag.
7. Slave loads low address into SSPxADD,
releasing SCL.
8. Master sends matching low address byte to the
slave; UA bit is set.
Note: Updates to the SSPxADD register are not
allowed until after the ACK sequence.
Master sends
Stop condition
Receive First Address Byte Receive Second Address Byte Receive Data Receive Data
SDA
1 1 1 1
0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
SCL is held low
while CKP = 0
SSPxIF
Set by hardware Cleared by software
on 9th falling edge
Preliminary
BF
If address matches Receive address is Data is read
SSPxADD it is loaded into read from SSPxBUF from SSPxBUF
PIC18(L)F26/45/46K40
SSPxBUF
UA
When UA = 1; Software updates SSPxADD
SCL is held low and releases SCL
CKP
Receive First Address Byte R/W = 0 Receive Second Address Byte Receive Data Receive Data
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5
SCL S 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 UA 1 2 3 4 5 6 7 8 9 1 2
SSPxIF
Set by hardware Cleared by software Cleared by software
on 9th falling edge
BF
Preliminary
PIC18(L)F26/45/46K40
ACKDT
Slave software clears
ACKDT to ACK
the received byte
UA
ACKTIM
ACKTIM is set by hardware
on 8th falling edge of SCL
FIGURE 26-22: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0)
2016 Microchip Technology Inc.
Master sends
Master sends Stop condition
Restart event Master sends
not ACK
Receiving Address R/W = 0 Receiving Second Address Byte Receive First Address Byte Transmitting Data Byte ACK = 1
SDA 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 1 1 1 0 A9 A8 ACK D7 D6 D5 D4 D3 D2 D1 D0
SCL 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
S
Sr
SSPxIF
BF
PIC18(L)F26/45/46K40
must be updated updated, UA is cleared
CKP and SCL is released
Indicates an address
has been received
DS40001816C-page 368
PIC18(L)F26/45/46K40
26.9.6 CLOCK STRETCHING 26.9.6.2 10-bit Addressing Mode
Clock stretching occurs when a device on the bus In 10-bit Addressing mode, when the UA bit is set, the
holds the SCL line low, effectively pausing communi- clock is always stretched. This is the only time the SCL
cation. The slave may stretch the clock to allow more is stretched without CKP being cleared. SCL is
time to handle data or prepare a response for the released immediately after a write to SSPxADD.
master device. A master device is not concerned with
Note: Previous versions of the module did not
stretching as anytime it is active on the bus and not
stretch the clock if the second address byte
transferring data it is stretching. Any stretching done
did not match.
by a slave is invisible to the master software and
handled by the hardware that generates SCL.
26.9.6.3 Byte NACKing
The CKP bit of the SSPxCON1 register is used to
control stretching in software. Any time the CKP bit is When the AHEN bit of SSPxCON3 is set; CKP is
cleared, the module will wait for the SCL line to go low cleared by hardware after the eighth falling edge of
and then hold it. Setting CKP will release SCL and SCL for a received matching address byte. When the
allow more communication. DHEN bit of SSPxCON3 is set; CKP is cleared after
the eighth falling edge of SCL for received data.
26.9.6.1 Normal Clock Stretching Stretching after the eighth falling edge of SCL allows
Following an ACK if the R/W bit of SSPxSTAT is set, a the slave to look at the received address or data and
read request, the slave hardware will clear CKP. This decide if it wants to ACK the received data.
allows the slave time to update SSPxBUF with data to
transfer to the master. If the SEN bit of SSPxCON2 is 26.9.7 CLOCK SYNCHRONIZATION AND
set, the slave hardware will always stretch the clock THE CKP BIT
after the ACK sequence. Once the slave is ready; CKP Any time the CKP bit is cleared, the module will wait
is set by software and communication resumes. for the SCL line to go low and then hold it. However,
clearing the CKP bit will not assert the SCL output low
Note 1: The BF bit has no effect on if the clock will
until the SCL output is already sampled low. There-
be stretched or not. This is different than
fore, the CKP bit will not assert the SCL line until an
previous versions of the module that
external I2C master device has already asserted the
would not stretch the clock, clear CKP, if
SCL line. The SCL output will remain low until the CKP
SSPxBUF was read before the ninth
bit is set and all other devices on the I2C bus have
falling edge of SCL.
released SCL. This ensures that a write to the CKP bit
2: Previous versions of the module did not will not violate the minimum high time requirement for
stretch the clock for a transmission if SCL (see Figure 26-23).
SSPxBUF was loaded before the ninth
falling edge of SCL. It is now always
cleared for read requests.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SDA DX DX 1
SCL
Master device
CKP asserts clock
Master device
releases clock
WR
SSPxCON1
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
S
SSPxIF
BF (SSPxSTAT<0>)
Cleared by software
SSPxBUF is read
GCEN (SSPxCON2<7>)
1
Master mode of operation is supported by interrupt In Master Transmitter mode, serial data is output
generation on the detection of the Start and Stop through SDA, while SCL outputs the serial clock. The
conditions. The Stop (P) and Start (S) bits are cleared first byte transmitted contains the slave address of the
from a Reset or when the MSSP module is disabled. receiving device (7 bits) and the Read/Write (R/W) bit.
Control of the I 2C bus may be taken when the P bit is In this case, the R/W bit will be logic 0. Serial data is
set, or the bus is Idle. transmitted eight bits at a time. After each byte is
transmitted, an Acknowledge bit is received. Start and
In Firmware Controlled Master mode, user code Stop conditions are output to indicate the beginning
conducts all I 2C bus operations based on Start and and the end of a serial transfer.
Stop bit condition detection. Start and Stop condition
detection is the only active circuitry in this mode. All In Master Receive mode, the first byte transmitted
other communication is done by the user software contains the slave address of the transmitting device
directly manipulating the SDA and SCL lines. (7 bits) and the R/W bit. In this case, the R/W bit will be
logic 1. Thus, the first byte transmitted is a 7-bit slave
The following events will cause the SSP Interrupt Flag address followed by a 1 to indicate the receive bit.
bit, SSPxIF, to be set (SSP interrupt, if enabled): Serial data is received via SDA, while SCL outputs the
Start condition detected serial clock. Serial data is received eight bits at a time.
After each byte is received, an Acknowledge bit is
Stop condition detected
transmitted. Start and Stop conditions indicate the
Data transfer byte transmitted/received beginning and end of transmission.
Acknowledge transmitted/received
A Baud Rate Generator is used to set the clock
Repeated Start generated frequency output on SCL. See Section 26.11 Baud
Rate Generator for more detail.
Note 1: The MSSP module, when configured in
I2C Master mode, does not allow queuing
26.10.2 CLOCK ARBITRATION
of events. For instance, the user is not
allowed to initiate a Start condition and Clock arbitration occurs when the master, during any
immediately write the SSPxBUF register receive, transmit or Repeated Start/Stop condition,
to initiate transmission before the Start releases the SCL pin (SCL allowed to float high). When
condition is complete. In this case, the the SCL pin is allowed to float high, the Baud Rate
SSPxBUF will not be written to and the Generator (BRG) is suspended from counting until the
WCOL bit will be set, indicating that a SCL pin is actually sampled high. When the SCL pin is
write to the SSPxBUF did not occur sampled high, the Baud Rate Generator is reloaded
with the contents of SSPxADD<7:0> and begins count-
2: When in Master mode, Start/Stop
ing. This ensures that the SCL high time will always be
detection is masked and an interrupt is
at least one BRG rollover count in the event that the
generated when the SEN/PEN bit is
clock is held low by an external device (Figure 26-25).
cleared and the generation is complete.
SDA DX DX 1
BRG decrements on
Q2 and Q4 cycles
BRG
03h 02h 01h 00h (hold off) 03h 02h
Value
26.10.3 WCOL STATUS FLAG the Start condition and causes the S bit of the
SSPxSTAT1 register to be set. Following this, the
If the user writes the SSPxBUF when a Start, Restart,
Baud Rate Generator is reloaded with the contents of
Stop, Receive or Transmit sequence is in progress, the
SSPxADD<7:0> and resumes its count. When the
WCOL bit is set and the contents of the buffer are
Baud Rate Generator times out (TBRG), the SEN bit of
unchanged (the write does not occur). Any time the
the SSPxCON2 register will be automatically cleared
WCOL bit is set it indicates that an action on SSPxBUF
by hardware; the Baud Rate Generator is suspended,
was attempted while the module was not idle.
leaving the SDA line held low and the Start condition is
Note: Because queuing of events is not allowed, complete.
writing to the lower five bits of SSPxCON2
Note 1: If at the beginning of the Start condition,
is disabled until the Start condition is
the SDA and SCL pins are already
complete.
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
26.10.4 I2C MASTER MODE START
the SDA line is driven low, a bus collision
CONDITION TIMING occurs, the Bus Collision Interrupt Flag,
To initiate a Start condition (Figure 26-26), the user BCLxIF, is set, the Start condition is
sets the Start Enable bit, SEN bit of the SSPxCON2 aborted and the I2C module is reset into
register. If the SDA and SCL pins are sampled high, its Idle state.
the Baud Rate Generator is reloaded with the contents 2: The Philips I2C specification states that a
of SSPxADD<7:0> and starts its count. If SCL and bus collision cannot occur on a Start.
SDA are both sampled high when the Baud Rate Gen-
erator times out (TBRG), the SDA pin is driven low. The
action of the SDA being driven low while SCL is high is
TBRG
SCL
S
TBRG
SDA A7 A6 A5 A4 A3 A2 A1 ACK = 0 D7 D6 D5 D4 D3 D2 D1 D0
BF (SSPxSTAT<0>)
PIC18(L)F26/45/46K40
SEN
PEN
R/W
DS40001816C-page 375
PIC18(L)F26/45/46K40
26.10.7 I2C Master Mode Reception 26.10.7.4 Typical Receive Sequence:
Master mode reception (Figure 26-29) is enabled by 1. The user generates a Start condition by setting
programming the Receive Enable bit, RCEN bit of the the SEN bit of the SSPxCON2 register.
SSP1CON2 register. 2. SSPxIF is set by hardware on completion of the
Note: The MSSP module must be in an Idle Start.
state before the RCEN bit is set or the 3. SSPxIF is cleared by software.
RCEN bit will be disregarded. 4. User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes 5. Address is shifted out the SDA pin until all eight
(high-to-low/low-to-high) and data is shifted into the bits are transmitted. Transmission begins as
SSPSR. After the falling edge of the eighth clock, the soon as SSPxBUF is written to.
receive enable flag is automatically cleared, the 6. The MSSP module shifts in the ACK bit from the
contents of the SSPSR are loaded into the SSPxBUF, slave device and writes its value into the
the BF flag bit is set, the SSPxIF flag bit is set and the ACKSTAT bit of the SSPxCON2 register.
Baud Rate Generator is suspended from counting, 7. The MSSP module generates an interrupt at the
holding SCL low. The MSSP is now in Idle state end of the ninth clock cycle by setting the
awaiting the next command. When the buffer is read by SSPxIF bit.
the CPU, the BF flag bit is automatically cleared. The 8. User sets the RCEN bit of the SSPxCON2 regis-
user can then send an Acknowledge bit at the end of ter and the master clocks in a byte from the slave.
reception by setting the Acknowledge Sequence 9. After the eighth falling edge of SCL, SSPxIF and
Enable, ACKEN bit of the SSPxCON2 register. BF are set.
26.10.7.1 BF Status Flag 10. Master clears SSPxIF and reads the received
byte from SSPUF, clears BF.
In receive operation, the BF bit is set when an address
11. Master sets the ACK value sent to slave in the
or data byte is loaded into SSPxBUF from SSPSR. It is
ACKDT bit of the SSPxCON2 register and initi-
cleared when the SSPxBUF register is read.
ates the ACK by setting the ACKEN bit.
26.10.7.2 SSPOV Status Flag 12. Masters ACK is clocked out to the slave and
SSPxIF is set.
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is 13. User clears SSPxIF.
already set from a previous reception. 14. Steps 8-13 are repeated for each received byte
from the slave.
26.10.7.3 WCOL Status Flag 15. Master sends a not ACK or Stop to end
If the user writes the SSPxBUF when a receive is communication.
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
Write to SSPxCON2<4>
to start Acknowledge sequence
SDA = ACKDT (SSPxCON2<5>) = 0
Write to SSPxCON2<0>(SEN = 1),
begin Start condition ACK from Master Set ACKEN, start Acknowledge sequence
Master configured as a receiver SDA = ACKDT = 0 SDA = ACKDT = 1
SEN = 0 by programming SSPxCON2<3> (RCEN = 1)
PEN bit = 1
Write to SSPxBUF occurs here, RCEN cleared RCEN = 1, start RCEN cleared
ACK from Slave next receive automatically written here
start XMIT automatically
Transmit Address to Slave Receiving Data from Slave Receiving Data from Slave
SDA A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
Bus master
ACK is not sent terminates
transfer
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL S P
Data shifted in on falling edge of CLK Set SSPxIF at end
of receive Set SSPxIF interrupt
Set SSPxIF interrupt at end of Acknow-
Set SSPxIF interrupt ledge sequence
at end of receive at end of Acknowledge
SSPxIF sequence
Preliminary
Set P bit
Cleared by software Cleared by software Cleared by software Cleared by software (SSPxSTAT<4>)
SDA = 0, SCL = 1 Cleared in
while CPU software and SSPxIF
responds to SSPxIF
PIC18(L)F26/45/46K40
BF
(SSPxSTAT<0>) Last bit is shifted into SSPSR and
contents are unloaded into SSPxBUF
SSPOV
ACKEN
RCEN
DS40001816C-page 377
Master configured as a receiver RCEN cleared ACK from Master RCEN cleared
by programming SSPxCON2<3> (RCEN = 1) automatically SDA = ACKDT = 0 automatically
PIC18(L)F26/45/46K40
26.10.8 ACKNOWLEDGE SEQUENCE 26.10.9 STOP CONDITION TIMING
TIMING A Stop bit is asserted on the SDA pin at the end of a
An Acknowledge sequence is enabled by setting the receive/transmit by setting the Stop Sequence Enable
Acknowledge Sequence Enable bit, ACKEN bit of the bit, PEN bit of the SSPxCON2 register. At the end of a
SSPxCON2 register. When this bit is set, the SCL pin is receive/transmit, the SCL line is held low after the
pulled low and the contents of the Acknowledge data bit falling edge of the ninth clock. When the PEN bit is set,
are presented on the SDA pin. If the user wishes to the master will assert the SDA line low. When the SDA
generate an Acknowledge, then the ACKDT bit should line is sampled low, the Baud Rate Generator is
be cleared. If not, the user should set the ACKDT bit reloaded and counts down to 0. When the Baud Rate
before starting an Acknowledge sequence. The Baud Generator times out, the SCL pin will be brought high
Rate Generator then counts for one rollover period and one TBRG (Baud Rate Generator rollover count)
(TBRG) and the SCL pin is deasserted (pulled high). later, the SDA pin will be deasserted. When the SDA
When the SCL pin is sampled high (clock arbitration), pin is sampled high while SCL is high, the P bit of the
the Baud Rate Generator counts for TBRG. The SCL pin SSPxSTAT register is set. A TBRG later, the PEN bit is
is then pulled low. Following this, the ACKEN bit is auto- cleared and the SSPxIF bit is set (Figure 26-31).
matically cleared, the Baud Rate Generator is turned off
and the MSSP module then goes into Idle mode 26.10.9.1 WCOL Status Flag
(Figure 26-30). If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
26.10.8.1 WCOL Status Flag contents of the buffer are unchanged (the write does
If the user writes the SSPxBUF when an Acknowledge not occur).
sequence is in progress, then the WCOL bit is set and
the contents of the buffer are unchanged (the write
does not occur).
FIGURE 26-30: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here, ACKEN automatically cleared
write to SSPxCON2
ACKEN = 1, ACKDT = 0
TBRG TBRG
SDA D0 ACK
SCL 8 9
SSPxIF
Cleared in
SSPxIF set at software
the end of receive Cleared in
software SSPxIF set at the end
of Acknowledge sequence
Note: TBRG = one Baud Rate Generator period.
SDA ACK
P
TBRG TBRG TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup Stop condition
SDA
BCLxIF
SDA
SCL
Set SEN, enable Start SEN cleared automatically because of bus collision.
condition if SDA = 1, SCL = 1 SSPx module reset into Idle state.
SEN
SDA sampled low before
Start condition. Set BCLxIF.
S bit and SSPxIF set because
BCLxIF SDA = 0, SCL = 1.
SSPxIF and BCLxIF are
cleared by software
SSPxIF
TBRG TBRG
SDA
SSPxIF 0 0
FIGURE 26-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA = 0, SCL = 1
Set S Set SSPxIF
Less than TBRG
TBRG
SCL S
SCL pulled low after BRG
time out
SEN
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BCLxIF 0
SSPxIF
SDA = 0, SCL = 1, Interrupts cleared
set SSPxIF by software
SDA
SCL
RSEN
BCLxIF
Cleared by software
S 0
SSPxIF 0
TBRG TBRG
SDA
SCL
S 0
SSPxIF
PEN
BCLxIF
P 0
SSPxIF 0
SDA
PEN
BCLxIF
P 0
SSPxIF 0
SSPM<3:0> SSPxADD<7:0>
Data Bus
TXxIE
SYNC
Interrupt
CSRC
TXxREG Register TXxIF
8 RxyPPS(1)
CKx pin TXEN
MSb LSb RXx/DTx pin
PPS 1 (8) 0 Pin Buffer
and Control PPS
0 Transmit Shift Register (TSR)
CKPPS SYNC
TRMT TX_out
Baud Rate Generator FOSC
n
TX9
BRG16 n
+1 Multiplier x4 x16 x64
TX9D TXx/CKx pin
SYNC 1 X 0 0 0 0
SPxBRGH SPxBRGL PPS
BRGH X 1 1 0 0
1
BRG16 X 1 0 1 0
RxyPPS
SYNC
Note 1: In Synchronous mode, the DT output and RX input PPS CSRC
selections should enable the same pin.
RXxPPS(1)
RXx/DTx pin MSb RSR Register LSb
Pin Buffer Data
PPS and Control Recovery
Stop (8) 7 1 0 Start
BRG16
+1 n
Multiplier x4 x16 x64
SYNC 1 X 0 0 0
SPxBRGH SPxBRGL BRGH FIFO
X 1 1 0 0 FERR RX9D RCxREG Register
BRG16 X 1 0 1 0
8
Data Bus
Note 1: In Synchronous mode, the DT output and RX input PPS RCxIF Interrupt
selections should enable the same pin. RCxIE
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: SREN/CREN bits of RCxSTA (Register 27-2) override TXEN in Sync mode.
Legend:
R = Readable bit W = Writable bit HC = Bit is cleared by hardware
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Write to TXxREG
Word 1
BRG Output
(Shift Clock)
TXx/CKx
pin Start bit bit 0 bit 1 bit 7/8 Stop bit
Word 1
TXxIF bit
(Transmit Buffer 1 TCY
Reg. Empty Flag)
Word 1
TRMT bit Transmit Shift Reg.
(Transmit Shift
Reg. Empty Flag)
Write to TXxREG
Word 1 Word 2
BRG Output
(Shift Clock)
TXx/CKx
pin Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0
TXxIF bit 1 TCY Word 1 Word 2
(Transmit Buffer
Reg. Empty Flag) 1 TCY
CREN = 1 Immediately after all data bits and the Stop bit have
been received, the character in the RSR is transferred
SYNC = 0
to the EUSART receive FIFO and the RCxIF interrupt
SPEN = 1 flag bit of the PIR3 register is set. The top character in
All other EUSART control bits are assumed to be in the FIFO is transferred out of the FIFO by reading the
their default state. RCxREG register.
Setting the CREN bit of the RCxSTA register enables Note: If the receive FIFO is overrun, no additional
the receiver circuitry of the EUSART. Clearing the SYNC characters will be received until the overrun
bit of the TXxSTA register configures the EUSART for condition is cleared. See Section
asynchronous operation. Setting the SPEN bit of the 27.2.2.5 Receive Overrun Error for
RCxSTA register enables the EUSART. The more information on overrun errors.
programmer must set the corresponding TRIS bit to
configure the RXx/DTx I/O pin as an input. 27.2.2.3 Receive Interrupts
Note: If the RX/DT function is on an analog pin, The RCxIF interrupt flag bit of the PIR3 register is set
the corresponding ANSEL bit must be whenever the EUSART receiver is enabled and there is
cleared for the receiver to function. an unread character in the receive FIFO. The RCxIF
interrupt flag bit is read-only, it cannot be set or cleared
by software.
RCxIF interrupts are enabled by setting all of the
following bits:
RCxIE, Interrupt Enable bit of the PIE3 register
PEIE, Peripheral Interrupt Enable bit of the
INTCON register
GIE, Global Interrupt Enable bit of the INTCON
register
The RCxIF interrupt flag bit will be set when there is an
unread character in the FIFO, regardless of the state of
interrupt enable bits.
Read Rcv
Buffer Reg.
RCxREG
RCxIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RXx input. The RCxREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
TABLE 27-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
on Page
BAUDxCON ABDOVF RCIDL SCKP BRG16 WUE ABDEN 390
RCxSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 389
SPxBRGH EUSARTx Baud Rate Generator, High Byte 399*
SPxBRGL EUSARTx Baud Rate Generator, Low Byte 399*
TXxSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 388
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207 300 0.00 191 300 0.16 51
1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12
2400 2404 0.16 51 2404 0.16 25 2400 0.00 23
9600 9615 0.16 12 9600 0.00 5
10417 10417 0.00 11 10417 0.00 5
19.2k 19.20k 0.00 2
57.6k 57.60k 0.00 0
115.2k
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300
1200
2400
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300 0.16 207
1200 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11
57.6k 55556 -3.55 8 57.60k 0.00 3
115.2k 115.2k 0.00 1
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303
1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575
2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287
9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71
10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65
19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35
57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11
115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207
1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51
2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25
9600 9615 0.16 51 9615 0.16 25 9600 0.00 23
10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5
19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11
57.6k 55556 -3.55 8 57.60k 0.00 3
115.2k 115.2k 0.00 1
BAUD FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215
1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303
2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151
9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287
10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264
19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143
57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47
115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23
BAUD FOSC = 8.000 MHz FOSC = 4.000 MHz FOSC = 3.6864 MHz FOSC = 1.000 MHz
RATE SPBRG SPBRG SPBRG SPBRG
Actual % Actual % Actual % Actual %
value value value value
Rate Error Rate Error Rate Error Rate Error
(decimal) (decimal) (decimal) (decimal)
300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832
1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207
2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103
9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25
10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23
19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12
57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15
115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7
BRG Clock
RCIDL
RCxIF bit
(Interrupt)
Read
RCxREG
Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
Note 1: The EUSART remains in Idle while the WUE bit is set.
Note 1: If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is
still active. This sequence should not depend on the presence of Q clocks.
2: The EUSART remains in Idle while the WUE bit is set.
Write to TXxREG
Dummy Write
BRG Output
(Shift Clock)
TXx (pin) Start bit bit 0 bit 1 bit 11 Stop bit
Break
TXxIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB Sampled Here Auto Cleared
SENDB
(send Break
control bit)
TXx/CKx pin
(SCKP = 1)
Write to
TXxREG Reg Write Word 1 Write Word 2
TXxIF bit
(Interrupt Flag)
TRMT bit
1 1
TXEN bit
Note: Sync Master mode, SPxBRGL = 0, continuous transmission of two 8-bit words.
TXx/CKx pin
Write to
TXxREG reg
TXxIF bit
TRMT bit
TXEN bit
RXx/DTx
pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
TXx/CKx pin
(SCKP = 0)
TXx/CKx pin
(SCKP = 1)
Write to
bit SREN
SREN bit
CREN bit 0 0
RCxIF bit
(Interrupt)
Read
RCxREG
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
2
ADFVR<1:0>
1x
FVR_buffer1
2x
4x (To ADC Module)
2
CDAFVR<1:0>
1x FVR_buffer2
2x (To Comparators
4x and DAC)
FVREN
+
_ FVRRDY
Note 1
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared q = Value depends on condition
High Range: VOUT = VDD - 4VT Table 29-1 shows the recommended minimum VDD vs.
range setting.
Low Range: VOUT = VDD - 2VT
TABLE 29-1: RECOMMENDED VDD VS.
RANGE
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See Section Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0
28.0 Fixed Voltage Reference (FVR) for more 3.6V 1.8V
information.
The circuit is enabled by setting the TSEN bit of the 29.3 Temperature Output
FVRCON register. When disabled, the circuit draws no
current. The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
The circuit operates in either high or low range. The high
the temperature circuit output. Refer to Section
range, selected by setting the TSRNG bit of the
31.0 Analog-to-Digital Converter with Computation
FVRCON register, provides a wider output voltage. This
(ADC2) Module for detailed information.
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The low range is selected by clearing the TSRNG bit of
the FVRCON register. The low range generates a lower
voltage drop and thus, a lower bias voltage is needed to
operate the circuit. The low range is provided for low
voltage operation.
Rev. 10-000026F
8/7/2015
Reserved 11
VSOURCE+ DACR<4:0>
FVR Buffer 10 5
VREF+ 01 R
AVDD 00
R
DACPSS
R
32-to-1 MUX
32 DACx_output
To Peripherals
Steps
DACEN
R
R DACxOUT1(1)
DACOE1
R
DACxOUT2(1)
DACNSS
DACR 4:0
DACx_output = VREF+ VREF- -----------------------------
5 + VREF-
2
Note: See the DAC1CON0 register for the available VSOURCE+ and VSOURCE- selections.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
10
complete 10-bit Result
Write to bit
GO/DONE
GO/DONE Q1 16
start
Q4
ADRESH ADRESL
Q2 Enable
Trigger Select
TRIGSEL<3:0> ADON
. . . VSS
Trigger Sources
AUTO CONVERSION
TRIGGER
ADC
ADCS<5:0> 64 MHz 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz
Clock Source
FOSC/2 000000 31.25 ns(2) 62.5 ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s
FOSC/4 000001 62.5 ns(2) 125 ns(2) 200 ns(2) 250 ns(2) 500 ns(2) 1.0 s 4.0 s
FOSC/6 000010 125 ns(2) 187.5 ns(2) 300 ns(2) 375 ns(2) 750 ns(2) 1.5 s 6.0 s
FOSC/8 000011 187.5 ns(2) 250 ns(2) 400 ns(2) 500 ns(2) 1.0 s 2.0 s 8.0 s(3)
... ... ... ... ... ... ... ... ...
FOSC/16 000100 250 ns(2) 500 ns(2) 800 ns(2) 1.0 s 2.0 s 4.0 s 16.0 s(3)
... ... ... ... ... ... ... ... ...
FOSC/128 111111 2.0 s 4.0 s 6.4 s 8.0 s 16.0 s(3) 32.0 s(2) 128.0 s(2)
FRC ADCS(ADCON0<4>) = 1 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s 1.0-6.0 s
Legend: Shaded cells are outside of recommended range.
Note 1: See TAD parameter for FRC source typical TAD value.
2: These values violate the required TAD time.
3: Outside the recommended TAD time.
4: The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system
clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep
mode.
Rev. 10-000035B
7/15/2016
Precharge Acquisition/ Conversion Time
Time Sharing Time (Traditional Timing of ADC Conversion)
1-127 TCY 1-127 TCY
(TPRE) (TACQ) TCY TCY-TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10TAD11 2 TCY
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
V AP P LI ED 1 -------------------------- = V CHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
n+1
2 1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED
Tc
---------
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------- ;combining [1] and [2]
RC 1
n+1
2 1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 10pF 1k + 7k + 10k ln(0.0004885)
= 1.37 s
Therefore:
T A CQ = 2s + 892ns + 50C- 25C 0.05 s/C
= 4.62s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
VDD
Analog Sampling
Input Switch
VT 0.6V
Rs pin RIC 1k SS Rss
VA CPIN I LEAKAGE(1)
VT 0.6V CHOLD = 10 pF
5 pF
Ref-
6V
5V RSS
Legend: CHOLD = Sample/Hold Capacitance VDD 4V
3V
CPIN = Input Capacitance 2V
I LEAKAGE = Leakage current at the pin due to
various junctions
5 6 7 8 9 10 11
RIC = Interconnect Resistance
Sampling Switch
RSS = Resistance of Sampling Switch (k)
SS = Sampling Switch
VT = Threshold Voltage
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
ADC Output Code
3FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB 1.5 LSB
REF- Zero-Scale
Transition Full-Scale
Transition REF+
ADOUT Pad
ADOUT
ADOEN
VDD
ADIPPOL = 1
ANx Pads
ADIPPOL = 0
VGND
ADDCAP<2:0>
Additional
Sample and
Hold Cap
VSS
First Sample Second Sample
Time
Voltage
External Capacitive Sensor
Guard Ring Output
VSS
First Sample Second Sample
Time
ADCALC<2:0>
ADMD<2:0>
ADRES
ADFILT
Set
Error Threshold
Interrupt
Average/ Calculation ADERR Logic
1 Flag
Filter ADPREV
0
ADSTPT
ADUTHR ADLTHR
ADPSIS
Mode ADMD ADACC and ADCNT ADACC ADCNT Retrigger Threshold Interrupt ADAOV ADFLTR ADCNT
Test
Basic 0 ADACLR = 1 Unchanged Unchanged No Every If thresh- N/A N/A count
Sample old=true
Accumulate 1 ADACLR = 1 S + ADACC If (ADCNT=FF): ADCNT, No Every If thresh- ADACC Overflow ADACC/2ADCRS count
or otherwise: ADCNT+1 Sample old=true
(S2-S1) + ADACC
Average 2 ADACLR = 1 or S + ADACC If (ADCNT=FF): ADCNT, No If If thresh- ADACC Overflow ADACC/2ADCRS count
ADCNT>=ADRPT at ADGO or otherwise: ADCNT+1 ADCNT>= old=true
or retrigger (S2-S1) + ADACC ADRPT
Burst 3 ADACLR = 1 or ADGO set or Each repetition: same as Each repetition: same as Repeat while If If thresh- ADACC Overflow ADACC/2ADCRS ADRPT
Average retrigger Average Average ADCNT<ADRPT ADCNT>= old=true
End with sum of all End with ADCNT=ADRPT ADRPT
samples
Low-pass 4 ADACLR = 1 S+ADACC-ADACC/ If (ADCNT=FF): ADCNT, No If If thresh- ADACC Overflow Filtered Value count
Filter 2ADCRS otherwise: ADCNT+1 ADCNT>= old=true
or ADRPT
(S2-S1)+ADACC-ADACC/
Preliminary
2ADCRS
Note: S1 and S2 are abbreviations for Sample 1 and Sample 2, respectively. When ADDSEN = 0, S1 = ADRES; When ADDSEN = 1, S1 = ADPREV and S2 = ADRES.
PIC18(L)F26/45/46K40
DS40001816C-page 440
PIC18(L)F26/45/46K40
31.5.1 DIGITAL FILTER/AVERAGE register, as well as the ADCNT register. The ADACLR
bit is cleared by the hardware when accumulator
The digital filter/average module consists of an accu-
clearing action is complete.
mulator with data feedback options, and control logic to
determine when threshold tests need to be applied.
The accumulator is a 16-bit wide register which can be Note: When ADC is operating from FRC, five
accessed through the ADACCH:ADACCL register pair. FRC clock cycles are required to execute
the ADACC clearing operation.
Upon each trigger event (the ADGO bit set or external
event trigger), the ADC conversion result is added to The ADCRS <2:0> bits in the ADCON2 register control
the accumulator. If the accumulated value exceeds the data shift on the accumulator result, which
2(accumulator_width)-1 = 216 = 65535, the overflow bit effectively divides the value in accumulator
ADAOV in the ADSTAT register is set. (ADACCH:ADACCL) register pair. For the Accumulate
mode of the digital filter, the shift provides a simple
The number of samples to be accumulated is
scaling operation. For the Average/Burst Average
determined by the ADRPT (A/D Repeat Setting)
mode, the shift bits are used to determine number of
register. Each time a sample is added to the
samples for averaging. For the Low-pass Filter mode,
accumulator, the ADCNT register is incremented. Once
the shift is an integral part of the filter, and determines
ADRPT samples are accumulated (ADCNT = ADRPT),
the cut-off frequency of the filter. Table 31-4 shows the
an accumulator clear command can be issued by the
-3 dB cut-off frequency in T (radians) and the highest
software by setting the ADACLR bit in the ADCON2
signal attenuation obtained by this filter at nyquist
register. Setting the ADACLR bit will also clear the
frequency (T = ).
ADAOV (Accumulator overflow) bit in the ADSTAT
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Otherwise:
The bit is ignored
bit 6 ADIPEN: A/D Inverted Precharge Enable bit
If ADDSEN = 1
1 = The precharge and guard signals in the second conversion cycle are the opposite polarity of the
first cycle
0 = Both Conversion cycles use the precharge and guards specified by ADPPOL and ADGPOL
Otherwise:
The bit is ignored
bit 5 ADGPOL: Guard Ring Polarity Selection bit
1 = ADC guard Ring outputs start as digital high during Precharge stage
0 = ADC guard Ring outputs start as digital low during Precharge stage
bit 4-1 Unimplemented: Read as 0
bit 0 ADDSEN: Double-sample enable bit
1 = Two conversions are performed on each trigger. Data from the first conversion appears in
ADPREV
0 = One conversion is performed for each trigger
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HC = Bit is cleared by hardware
Note 1: When ADPSIS = 0, the value of ADRES-ADPREV) is the value of (S2-S1) from Table 31-3.
2: When ADPSIS = 0
3: When ADPSIS = 1.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared HS/HC = Bit is set/cleared by hardware
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note: If ADPRE is not equal to 0, then ADACQ = b00000000 means Acquisition time is 256 clocks of the
selected ADC clock.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-6 ADRES<1:0>: ADC Result Register bits. Lower two bits of 10-bit conversion result.
bit 5-0 Reserved: Do not use.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADRES<7:0>: ADC Result Register bits. Lower eight bits of 10-bit conversion result.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the
ADFM bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
Note 1: If ADPSIS = 0, ADPREVH and ADPREVL are formatted the same way as ADRES is, depending on the
ADFM bit.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADACC<15:8>: ADC Accumulator MSB. Upper eight bits of accumulator value. See Table 31-2 for
more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADACC<7:0>: ADC Accumulator LSB. Lower eight bits of accumulator value. See Table 31-2 for more
details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADSTPT<15:8>: ADC Threshold Setpoint MSB. Upper byte of ADC threshold setpoint, depending on
ADCALC, may be used to determine ADERR, see Register 23-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADSTPT<7:0>: ADC Threshold Setpoint LSB. Lower byte of ADC threshold setpoint, depending on
ADCALC, may be used to determine ADERR, see Register 23-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADERR<7:0>: ADC Setpoint Error MSB. Upper byte of ADC Setpoint Error. Setpoint Error calculation
is determined by ADCALC bits of ADCON3, see Register 23-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADERR<7:0>: ADC Setpoint Error LSB. Lower byte of ADC Setpoint Error calculation is determined
by ADCALC bits of ADCON3, see Register 23-1 for more details.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADLTH<15:8>: ADC Lower Threshold MSB. ADLTH and ADUTH are compared with ADERR to set
the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADLTH<7:0>: ADC Lower Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the
ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADUTH<15:8>: ADC Upper Threshold MSB. ADLTH and ADUTH are compared with ADERR to set
the ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
bit 7-0 ADUTH<7:0>: ADC Upper Threshold LSB. ADLTH and ADUTH are compared with ADERR to set the
ADUTHR and ADLTHR bits of ADSTAT. Depending on the setting of ADTMD, an interrupt may be
triggered by the results of this comparison.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets
1 = Bit is set 0 = Bit is cleared
CxNCH<2:0>
CxEN(1)
3 Interrupt CxINTP
det
CXIN0- 0 Set CxIF
CXIN1- 1
2 MUX Interrupt CxINTN
CXIN2-
(2)
det
CXIN3- 3
CXPOL
Reserved 4 CxNCH
-
to CMXCON0 (CXOUT)
Reserved 5 D Q
Cx and CMOUT (MCXOUT)
FVR Buffer 2 6 +
CxPCH
Q1 EN
7
CxHYS
AGND
CXSYNC
TRIS bit
0
PPS
D Q 1 CXOUT
CXIN0+ 0 From Timer1 RxyPPS
tmr1_clk sync_CxOUT
CXIN1+ 1 To Other
MUX Peripherals
(2)
Reserved 2
Reserved 3
Reserved 4
DAC_Output 5
FVR Buffer 2 6
AGND CxEN
CXPCH<2:0>
3
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Rev. 10-000071A
8/2/2013
VDD
Analog
VT 0.6V
RS < 10K Input pin RIC
To Comparator
ILEAKAGE(1)
VA CPIN VT 0.6V
5pF
VSS
VDD
4 HLVDSEL<3:0>
HLVDEN
16-to-1 MUX
HLVDOUT
- Trigger/
Interrupt HLVDIF
+ Generation
HLVDRDY HLVDINTH HLVDINTL
Bandgap
Reference
HLVDEN Volatge
VDD
VHLVD
HLVDIF
Enable HLVD
TFVRST
HLVDRDY
HLVDIF Cleared in Software
Band Gap Reference Voltage is Stable
CASE 2:
VDD
VHLVD
HLVDIF
Enable HLVD
HLVDRDY TFVRST
VHLVD
VDD
HLVDIF
Enable HLVD
HLVDRDY TIRVST
CASE 2:
VHLVD
VDD
HLVDIF
Enable HLVD
HLVDRDY TIRVST
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared u = Bit is unchanged
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as 0
-n = Value at POR 1 = Bit is set 0 = Bit is cleared x = Bit is unknown
Pin 1 Indicator
Pin Description*
1 1 = VPP/MCLR
2
2 = VDD Target
3
4 3 = VSS (ground)
5
6 4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
External
Programming VDD Device to be
Signals Programmed
VDD VDD
VPP MCLR/VPP
VSS VSS
Data ICSPDAT
Clock ICSPCLK
* * *
To Normal Connections
1. The file register (specified by f) One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
2. The destination of the result (specified by d)
instruction execution time is 1 s. If a conditional test is
3. The accessed memory (specified by a)
true, or the program counter is changed as a result of
The file register designator f specifies which file an instruction, the instruction execution time is 2 s.
register is to be used by the instruction. The destination Two-word branch instructions (if true) would take 3 s.
designator d specifies where the result of the opera-
Figure 35-1 shows the general formats that the instruc-
tion is to be placed. If d is zero, the result is placed in
tions can have. All examples use the convention nnh
the WREG register. If d is one, the result is placed in
to represent a hexadecimal number.
the file register specified in the instruction.
The Instruction Set Summary, shown in Table 35-2,
All bit-oriented instructions have three operands:
lists the standard instructions recognized by the
1. The file register (specified by f) Microchip Assembler (MPASMTM).
2. The bit in the file register (specified by b) Section 35.1.1 Standard Instruction Set provides
3. The accessed memory (specified by a) a description of each instruction.
The bit field designator b selects the number of the bit
affected by the operation, while the file register
designator f represents the number of the file in which
the bit is located.
Literal operations
15 8 7 0
OPCODE k (literal) MOVLW 7Fh
Control operations
CALL, GOTO and Branch operations
15 8 7 0
OPCODE n<7:0> (literal) GOTO Label
15 12 11 0
1111 n<19:8> (literal)
15 8 7 0
OPCODE S n<7:0> (literal) CALL MYFUNC
15 12 11 0
1111 n<19:8> (literal)
S = Fast bit
15 11 10 0
OPCODE n<10:0> (literal) BRA MYFUNC
15 8 7 0
OPCODE n<7:0> (literal) BC MYFUNC
BYTE-ORIENTED OPERATIONS
ADDWF f, d, a Add WREG and f 1 0010 01da ffff ffff C, DC, Z, OV, N 1, 2
ADDWFC f, d, a Add WREG and CARRY bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2
ANDWF f, d, a AND WREG with f 1 0001 01da ffff ffff Z, N 1,2
CLRF f, a Clear f 1 0110 101a ffff ffff Z 2
COMF f, d, a Complement f 1 0001 11da ffff ffff Z, N 1, 2
CPFSEQ f, a Compare f with WREG, skip = 1 (2 or 3) 0110 001a ffff ffff None 4
CPFSGT f, a Compare f with WREG, skip > 1 (2 or 3) 0110 010a ffff ffff None 4
CPFSLT f, a Compare f with WREG, skip < 1 (2 or 3) 0110 000a ffff ffff None 1, 2
DECF f, d, a Decrement f 1 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
DECFSZ f, d, a Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 3, 4
DCFSNZ f, d, a Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None 1, 2
INCF f, d, a Increment f 1 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4
INCFSZ f, d, a Increment f, Skip if 0 1 (2 or 3) 0011 11da ffff ffff None 4
INFSNZ f, d, a Increment f, Skip if Not 0 1 (2 or 3) 0100 10da ffff ffff None 1, 2
IORWF f, d, a Inclusive OR WREG with f 1 0001 00da ffff ffff Z, N 1, 2
MOVF f, d, a Move f 1 0101 00da ffff ffff Z, N 1
MOVFF fs, fd Move fs (source) to 1st word 2 1100 ffff ffff ffff None
fd (destination) 2nd word 1111 ffff ffff ffff
MOVWF f, a Move WREG to f 1 0110 111a ffff ffff None
MULWF f, a Multiply WREG with f 1 0000 001a ffff ffff None 1, 2
NEGF f, a Negate f 1 0110 110a ffff ffff C, DC, Z, OV, N
RLCF f, d, a Rotate Left f through Carry 1 0011 01da ffff ffff C, Z, N 1, 2
RLNCF f, d, a Rotate Left f (No Carry) 1 0100 01da ffff ffff Z, N
RRCF f, d, a Rotate Right f through Carry 1 0011 00da ffff ffff C, Z, N
RRNCF f, d, a Rotate Right f (No Carry) 1 0100 00da ffff ffff Z, N
SETF f, a Set f 1 0110 100a ffff ffff None 1, 2
SUBFWB f, d, a Subtract f from WREG with 1 0101 01da ffff ffff C, DC, Z, OV, N
borrow
SUBWF f, d, a Subtract WREG from f 1 0101 11da ffff ffff C, DC, Z, OV, N 1, 2
SUBWFB f, d, a Subtract WREG from f with 1 0101 10da ffff ffff C, DC, Z, OV, N
borrow
SWAPF f, d, a Swap nibbles in f 1 0011 10da ffff ffff None 4
TSTFSZ f, a Test f, skip if 0 1 (2 or 3) 0110 011a ffff ffff None 1, 2
XORWF f, d, a Exclusive OR WREG with f 1 0001 10da ffff ffff Z, N
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem-
ory locations have a valid instruction.
BIT-ORIENTED OPERATIONS
BCF f, b, a Bit Clear f 1 1001 bbba ffff ffff None 1, 2
BSF f, b, a Bit Set f 1 1000 bbba ffff ffff None 1, 2
BTFSC f, b, a Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4
BTFSS f, b, a Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4
BTG f, b, a Bit Toggle f 1 0111 bbba ffff ffff None 1, 2
CONTROL OPERATIONS
BC n Branch if Carry 1 (2) 1110 0010 nnnn nnnn None
BN n Branch if Negative 1 (2) 1110 0110 nnnn nnnn None
BNC n Branch if Not Carry 1 (2) 1110 0011 nnnn nnnn None
BNN n Branch if Not Negative 1 (2) 1110 0111 nnnn nnnn None
BNOV n Branch if Not Overflow 1 (2) 1110 0101 nnnn nnnn None
BNZ n Branch if Not Zero 1 (2) 1110 0001 nnnn nnnn None
BOV n Branch if Overflow 1 (2) 1110 0100 nnnn nnnn None
BRA n Branch Unconditionally 2 1101 0nnn nnnn nnnn None
BZ n Branch if Zero 1 (2) 1110 0000 nnnn nnnn None
CALL k, s Call subroutine 1st word 2 1110 110s kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
CLRWDT Clear Watchdog Timer 1 0000 0000 0000 0100 TO, PD
DAW Decimal Adjust WREG 1 0000 0000 0000 0111 C
GOTO k Go to address 1st word 2 1110 1111 kkkk kkkk None
2nd word 1111 kkkk kkkk kkkk
NOP No Operation 1 0000 0000 0000 0000 None
NOP No Operation 1 1111 xxxx xxxx xxxx None 4
POP Pop top of return stack (TOS) 1 0000 0000 0000 0110 None
PUSH Push top of return stack (TOS) 1 0000 0000 0000 0101 None
RCALL n Relative Call 2 1101 1nnn nnnn nnnn None
RESET Software device Reset 1 0000 0000 1111 1111 All
RETFIE s Return from interrupt enable 2 0000 0000 0001 000s GIE/GIEH,
PEIE/GIEL
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
RETURN s Return from Subroutine 2 0000 0000 0001 001s None
SLEEP Go into Standby mode 1 0000 0000 0000 0011 TO, PD
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem-
ory locations have a valid instruction.
LITERAL OPERATIONS
ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N
ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N
IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N
LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None
to FSR(f) 1st word 1111 0000 kkkk kkkk
MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None
MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None
MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None
RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None
SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N
XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N
DATA MEMORY PROGRAM MEMORY OPERATIONS
TBLRD* Table Read 2 0000 0000 0000 1000 None
TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None
TBLRD*- Table Read with post-decrement 0000 0000 0000 1010 None
TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None
TBLWT* Table Write 2 0000 0000 0000 1100 None
TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None
TBLWT*- Table Write with post-decrement 0000 0000 0000 1110 None
TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an
external device, the data will be written back with a 0.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless
the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program mem-
ory locations have a valid instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write to
register f Data destination
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set
Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a}
Operands: 0 f 255 Operands: 0 f 255
0b7 0b<7
a [0,1] a [0,1]
Operation: skip if (f<b>) = 0 Operation: skip if (f<b>) = 1
Status Affected: None Status Affected: None
Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff
Description: If bit b in register f is 0, then the next Description: If bit b in register f is 1, then the next
instruction is skipped. If bit b is 0, then instruction is skipped. If bit b is 1, then
the next instruction fetched during the the next instruction fetched during the
current instruction execution is discarded current instruction execution is discarded
and a NOP is executed instead, making and a NOP is executed instead, making
this a 2-cycle instruction. this a 2-cycle instruction.
If a is 0, the Access Bank is selected. If If a is 0, the Access Bank is selected. If
a is 1, the BSR is used to select the a is 1, the BSR is used to select the
GPR bank. GPR bank.
If a is 0 and the extended instruction If a is 0 and the extended instruction
set is enabled, this instruction operates in set is enabled, this instruction operates
Indexed Literal Offset Addressing in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). mode whenever f 95 (5Fh).
See Section 35.2.3 Byte-Oriented and See Section 35.2.3 Byte-Oriented and
Bit-Oriented Instructions in Indexed Bit-Oriented Instructions in Indexed
Literal Offset Mode for details. Literal Offset Mode for details.
Words: 1 Words: 1
Cycles: 1(2) Cycles: 1(2)
Note: 3 cycles if skip and followed Note: 3 cycles if skip and followed
by a 2-word instruction. by a 2-word instruction.
Q Cycle Activity: Q Cycle Activity:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Decode Read Process No Decode Read Process No
register f Data operation register f Data operation
If skip: If skip:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
If skip and followed by 2-word instruction: If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
No No No No No No No No
operation operation operation operation operation operation operation operation
No No No No No No No No
operation operation operation operation operation operation operation operation
CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W
Syntax: CPFSGT f {,a} Syntax: CPFSLT f {,a}
Operands: 0 f 255 Operands: 0 f 255
a [0,1] a [0,1]
Operation: (f) W), Operation: (f) W),
skip if (f) > (W) skip if (f) < (W)
(unsigned comparison) (unsigned comparison)
Status Affected: None Status Affected: None
Encoding: 0110 010a ffff ffff
Encoding: 0110 000a ffff ffff
Description: Compares the contents of data memory
location f to the contents of the W by Description: Compares the contents of data memory
performing an unsigned subtraction. location f to the contents of W by
performing an unsigned subtraction.
If the contents of f are greater than the
contents of WREG, then the fetched If the contents of f are less than the
instruction is discarded and a NOP is contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
2-cycle instruction. executed instead, making this a
If a is 0, the Access Bank is selected. 2-cycle instruction.
If a is 0, the Access Bank is selected.
If a is 1, the BSR is used to select the
GPR bank. If a is 1, the BSR is used to select the
If a is 0 and the extended instruction GPR bank.
set is enabled, this instruction operates Words: 1
in Indexed Literal Offset Addressing Cycles: 1(2)
mode whenever f 95 (5Fh). See Sec-
Note: 3 cycles if skip and followed
tion 35.2.3 Byte-Oriented and Bit- by a 2-word instruction.
Oriented Instructions in Indexed Lit-
eral Offset Mode for details. Q Cycle Activity:
Words: 1 Q1 Q2 Q3 Q4
Cycles: 1(2) Decode Read Process No
Note: 3 cycles if skip and followed register f Data operation
by a 2-word instruction. If skip:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
Decode Read Process No operation operation operation operation
register f Data operation If skip and followed by 2-word instruction:
If skip: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4
No No No No Example: HERE CPFSLT REG, 1
operation operation operation operation NLESS :
No No No No LESS :
operation operation operation operation
Before Instruction
PC = Address (HERE)
Example: HERE CPFSGT REG, 0 W = ?
NGREATER : After Instruction
GREATER :
If REG < W;
Before Instruction PC = Address (LESS)
PC = Address (HERE) If REG W;
W = ? PC = Address (NLESS)
After Instruction
If REG W;
PC = Address (GREATER)
If REG W;
PC = Address (NGREATER)
Q1 Q2 Q3 Q4 Q Cycle Activity:
Decode Read Process Write to Q1 Q2 Q3 Q4
register f Data destination Decode Read Process Write to
If skip: register f Data destination
Q1 Q2 Q3 Q4 If skip:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
If skip and followed by 2-word instruction: operation operation operation operation
Q1 Q2 Q3 Q4 If skip and followed by 2-word instruction:
No No No No Q1 Q2 Q3 Q4
operation operation operation operation No No No No
No No No No operation operation operation operation
operation operation operation operation No No No No
operation operation operation operation
Example: HERE DECFSZ CNT, 1, 1
GOTO LOOP Example: HERE DCFSNZ TEMP, 1, 0
CONTINUE ZERO :
NZERO :
Before Instruction
PC = Address (HERE) Before Instruction
After Instruction TEMP = ?
CNT = CNT - 1 After Instruction
If CNT = 0; TEMP = TEMP 1,
PC = Address (CONTINUE) If TEMP = 0;
If CNT 0; PC = Address (ZERO)
PC = Address (HERE + 2) If TEMP 0;
PC = Address (NZERO)
W = E2h Q1 Q2 Q3 Q4
PRODH = ADh Decode Read Process Write
PRODL = 08h register f Data registers
PRODH:
PRODL
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read Process Write
register f Data register f
POP Pop Top of Return Stack PUSH Push Top of Return Stack
Syntax: POP Syntax: PUSH
Operands: None Operands: None
Operation: (TOS) bit bucket Operation: (PC + 2) TOS
Status Affected: None Status Affected: None
Encoding: 0000 0000 0000 0110 Encoding: 0000 0000 0000 0101
Description: The TOS value is pulled off the return Description: The PC + 2 is pushed onto the top of
stack and is discarded. The TOS value the return stack. The previous TOS
then becomes the previous value that value is pushed down on the stack.
was pushed onto the return stack. This instruction allows implementing a
This instruction is provided to enable software stack by modifying TOS and
the user to properly manage the return then pushing it onto the return stack.
stack to incorporate a software stack. Words: 1
Words: 1
Cycles: 1
Cycles: 1 Q Cycle Activity:
Q Cycle Activity: Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Decode PUSH No No
Decode No POP TOS No PC + 2 onto operation operation
operation value operation return stack
RLNCF Rotate Left f (No Carry) RRCF Rotate Right f through Carry
Syntax: RLNCF f {,d {,a}} Syntax: RRCF f {,d {,a}}
Operands: 0 f 255 Operands: 0 f 255
d [0,1] d [0,1]
a [0,1] a [0,1]
Operation: (f<n>) dest<n + 1>, Operation: (f<n>) dest<n 1>,
(f<7>) dest<0> (f<0>) C,
Status Affected: N, Z (C) dest<7>
Words: 1 C register f
Cycles: 1
Words: 1
Q Cycle Activity:
Cycles: 1
Q1 Q2 Q3 Q4
Decode Read Process Write to Q Cycle Activity:
register f Data destination Q1 Q2 Q3 Q4
Decode Read Process Write to
Example: RLNCF REG, 1, 0 register f Data destination
Before Instruction
REG = 1010 1011 Example: RRCF REG, 0, 0
After Instruction Before Instruction
REG = 0101 0111 REG = 1110 0110
C = 0
After Instruction
REG = 1110 0110
W = 0111 0011
C = 0
ADDFSR Add Literal to FSR ADDULNK Add Literal to FSR2 and Return
Syntax: ADDFSR f, k Syntax: ADDULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 + k FSR2,
Operation: FSR(f) + k FSR(f) (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1000 ffkk kkkk Encoding: 1110 1000 11kk kkkk
Description: The 6-bit literal k is added to the Description: The 6-bit literal k is added to the
contents of the FSR specified by f. contents of FSR2. A RETURN is then
Words: 1 executed by loading the PC with the
Cycles: 1 TOS.
The instruction takes two cycles to
Q Cycle Activity:
execute; a NOP is performed during
Q1 Q2 Q3 Q4 the second cycle.
Decode Read Process Write to This may be thought of as a special
literal k Data FSR case of the ADDFSR instruction,
where f = 3 (binary 11); it operates
only on FSR2.
Example: ADDFSR 2, 23h Words: 1
Before Instruction Cycles: 2
FSR2 = 03FFh
After Instruction Q Cycle Activity:
FSR2 = 0422h
Q1 Q2 Q3 Q4
Decode Read Process Write to
literal k Data FSR
No No No No
Operation Operation Operation Operation
Note: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in
symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
MOVSS Move Indexed to Indexed PUSHL Store Literal at FSR2, Decrement FSR2
Syntax: MOVSS [zs], [zd] Syntax: PUSHL k
Operands: 0 zs 127 Operands: 0k 255
0 zd 127
Operation: k (FSR2),
Operation: ((FSR2) + zs) ((FSR2) + zd) FSR2 1 FSR2
Status Affected: None
Status Affected: None
Encoding:
Encoding: 1111 1010 kkkk kkkk
1st word (source) 1110 1011 1zzz zzzzs
2nd word (dest.) 1111 xxxx xzzz zzzzd Description: The 8-bit literal k is written to the data
memory address specified by FSR2. FSR2
Description The contents of the source register are
moved to the destination register. The is decremented by 1 after the operation.
addresses of the source and destination This instruction allows users to push values
onto a software stack.
registers are determined by adding the
7-bit literal offsets zs or zd, Words: 1
respectively, to the value of FSR2. Both
Cycles: 1
registers can be located anywhere in
the 4096-byte data memory space Q Cycle Activity:
(000h to FFFh). Q1 Q2 Q3 Q4
The MOVSS instruction cannot use the Decode Read k Process Write to
PCL, TOSU, TOSH or TOSL as the data destination
destination register.
If the resultant source address points to
an indirect addressing register, the Example: PUSHL 08h
value returned will be 00h. If the
resultant destination address points to Before Instruction
an indirect addressing register, the FSR2H:FSR2L = 01ECh
Memory (01ECh) = 00h
instruction will execute as a NOP.
Words: 2 After Instruction
Cycles: 2 FSR2H:FSR2L = 01EBh
Memory (01ECh) = 08h
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Determine Determine Read
source addr source addr source reg
Decode Determine Determine Write
dest addr dest addr to dest reg
SUBFSR Subtract Literal from FSR SUBULNK Subtract Literal from FSR2 and Return
Syntax: SUBFSR f, k Syntax: SUBULNK k
Operands: 0 k 63 Operands: 0 k 63
f [ 0, 1, 2 ] Operation: FSR2 k FSR2
Operation: FSR(f) k FSRf (TOS) PC
Status Affected: None Status Affected: None
Encoding: 1110 1001 ffkk kkkk Encoding: 1110 1001 11kk kkkk
Description: The 6-bit literal k is subtracted from Description: The 6-bit literal k is subtracted from the
the contents of the FSR specified by contents of the FSR2. A RETURN is then
f. executed by loading the PC with the TOS.
Words: 1 The instruction takes two cycles to
execute; a NOP is performed during the
Cycles: 1
second cycle.
Q Cycle Activity: This may be thought of as a special case of
Q1 Q2 Q3 Q4 the SUBFSR instruction, where f = 3 (binary
Decode Read Process Write to 11); it operates only on FSR2.
register f Data destination Words: 1
Cycles: 2
Q Cycle Activity:
Example: SUBFSR 2, 23h
Before Instruction Q1 Q2 Q3 Q4
FSR2 = 03FFh Decode Read Process Write to
register f Data destination
After Instruction
FSR2 = 03DCh No No No No
Operation Operation Operation Operation
The MPASM Assembler generates relocatable object Support for the entire device instruction set
files for the MPLINK Object Linker, Intel standard HEX Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol Command-line interface
reference, absolute LST files that contain source lines Rich directive set
and generated machine code, and COFF files for Flexible macro language
debugging.
MPLAB X IDE compatibility
The MPASM Assembler features include:
Integration into MPLAB X IDE projects
User-defined macros to streamline
assembly code
Conditional assembly for multipurpose
source files
Directives that allow complete control over the
assembly process
Note 1: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 37-6 to calculate device
specifications.
2: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + VDD - VOH) x IOH} + VOI x IOL
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
5.5
3.0
VDD (V)
2.5
2.3
0 4 10 16 32 64
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 37-7 for each Oscillator modes supported frequencies.
3.6
VDD (V)
3.0
2.5
1.8
0 4 10 16 32 64
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 37-7 for each Oscillator modes supported frequencies.
PIC18F26/45/46K40
Param.
Sym. Characteristic Min. Typ. Max. Units Conditions
No.
Supply Voltage
D002 VDD 1.8 3.6 V FOSC 16 MHz
2.5 3.6 V FOSC 16 MHz
3.0 3.6 V FOSC 32 MHz
D002 VDD 2.3 5.5 V FOSC 16 MHz
2.5 5.5 V FOSC 16 MHz
3.0 5.5 V FOSC 32 MHz
RAM Data Retention(1)
D003 VDR 1.5 V Device in Sleep mode
D003 VDR 1.7 V Device in Sleep mode
Power-on Reset Release Voltage(2)
D004 VPOR 1.6 V BOR or LPBOR disabled(3)
D004 VPOR 1.6 V BOR or LPBOR disabled(3)
Power-on Reset Rearm Voltage(2)
D005 VPORR 0.8 V BOR or LPBOR disabled(3)
D005 VPORR 1.5 V BOR or LPBOR disabled(3)
VDD Rise Rate to ensure internal Power-on Reset signal(2)
D006 SVDD 0.05 V/ms BOR or LPBOR disabled(3)
D006 SVDD 0.05 V/ms BOR or LPBOR disabled(3)
Data in Typ. column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 37-3, POR and POR REARM with Slow Rising VDD.
3: Please see Table 37-11 for BOR and LPBOR trip point information.
VDD
VPOR
VPORR
SVDD
VSS
NPOR(1)
POR REARM
VSS
TVLOW(3) TPOR(2)
PIC18F26/45/46K40
Param. Conditions
Symbol Device Characteristics Min. Typ. Max. Units
No. VDD Note
D100 IDDXT4 XT = 4 MHz 450 650 A 3.0V
D100 IDDXT4 XT = 4 MHz 550 750 A 3.0V
D100A IDDXT4 XT = 4 MHz 310 A 3.0V PMDs all 1s
D100A IDDXT4 XT = 4 MHz 410 A 3.0V PMDs all 1s
D101 IDDHFO16 HFINTOSC = 16 MHz 1.9 2.6 mA 3.0V
D101 IDDHFO16 HFINTOSC = 16 MHz 2.0 2.7 mA 3.0V
D101A IDDHFO16 HFINTOSC = 16 MHz 1.4 mA 3.0V PMDs all 1s
D101A IDDHFO16 HFINTOSC = 16 MHz 1.5 mA 3.0V PMDs all 1s
D102 IDDHFOPLL HFINTOSC = 64 MHz 7.4 9.4 mA 3.0V
D102 IDDHFOPLL HFINTOSC = 64 MHz 7.5 9.5 mA 3.0V
D102A IDDHFOPLL HFINTOSC = 64 MHz 5.2 mA 3.0V PMDs all 1s
D102A IDDHFOPLL HFINTOSC = 64 MHz 5.3 mA 3.0V PMDs all 1s
D103 IDDHSPLL32 HS+PLL = 64 MHz 6.9 8.9 mA 3.0V
D103 IDDHSPLL32 HS+PLL = 64 MHz 7.0 9.0 mA 3.0V
D103A IDDHSPLL32 HS+PLL = 64 MHz 4.9 mA 3.0V PMDs all 1s
D103A IDDHSPLL32 HS+PLL = 64 MHz 5.0 mA 3.0V PMDs all 1s
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz 1.05 mA 3.0V
D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz 1.15 mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 1.1 mA 3.0V
D105 IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 1.2 mA 3.0V
Data in Typ. column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from
rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switch-
ing rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.
3: IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (Register 6-2).
4: PMD bits are all in the default state, no modules are disabled.
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
CLKIN
OS1 OS2 OS2
OS20
CLKOUT
(CLKOUT Mode)
Param
Sym. Characteristic Min. Typ Max. Units Conditions
No.
ECL Oscillator
OS1 FECL Clock Frequency 500 kHz
OS2 TECL_DC Clock Duty Cycle 40 60 %
ECM Oscillator
OS3 FECM Clock Frequency 4 MHz
OS4 TECM_DC Clock Duty Cycle 40 60 %
ECH Oscillator
OS5 FECH Clock Frequency 32 MHz
OS6 TECH_DC Clock Duty Cycle 40 60 %
LP Oscillator
OS7 FLP Clock Frequency 100 kHz Note 4
XT Oscillator
OS8 FXT Clock Frequency 4 MHz Note 4
HS Oscillator
OS9 FHS Clock Frequency 20 MHz Note 4
Secondary Oscillator
OS10 FSEC Clock Frequency 32.4 32.768 33.1 kHz
System Oscillator
OS20 FOSC System Clock Frequency 64 MHz (Note 2, Note 3)
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at min values with an external clock applied to OSC1 pin.
When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
2: The system clock frequency (FOSC) is selected by the main clock switch controls as described in Section 6.0 Power-
Saving Operation Modes.
3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 Standard
Operating Conditions.
4: LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking
the device with the external square wave, one of the EC mode selections must be used.
Param
Sym. Characteristic Min. Typ Max. Units Conditions
No.
OS21 FCY Instruction Frequency FOSC/4 MHz
OS22 TCY Instruction Period 62.5 1/FCY ns
* These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected
current consumption. All devices are tested to operate at min values with an external clock applied to OSC1 pin.
When an external clock input is used, the max cycle time limit is DC (no clock) for all devices.
2: The system clock frequency (FOSC) is selected by the main clock switch controls as described in Section 6.0 Power-
Saving Operation Modes.
3: The system clock frequency (FOSC) must meet the voltage requirements defined in the Section 37.2 Standard
Operating Conditions.
4: LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking
the device with the external square wave, one of the EC mode selections must be used.
Param
Sym. Characteristic Min. Typ Max. Units Conditions
No.
OS50 FHFOSC Precision Calibrated HFINTOSC 4 MHz (Note 2)
Frequency 8
12
16
32
64
OS51 FHFOSCLP Low-Power Optimized HFINTOSC 1 MHz
Frequency 2 MHz
OS52 FMFOSC Internal Calibrated MFINTOSC 500 kHz
Frequency
OS53* FLFOSC Internal LFINTOSC Frequency 31 kHz
OS54* THFOSCST HFINTOSC 11 20 s VREGPM = 0
Wake-up from Sleep Start-up 50 s VREGPM = 1
Time
OS56 TLFOSCST LFINTOSC 0.2 ms
Wake-up from Sleep Start-up Time
*These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to
the device as possible. 0.1 F and 0.01 F values in parallel are recommended.
2: See Figure 37-6: Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Tempera-
ture.
125
5%
85
3%
Temperature (C)
60
2%
0
5%
-40
1.8 2.0 2.3 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
VDD
MCLR
RST01
Internal
POR
RST04
PWRT
Time-out RST05
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
RST03
RST02
RST02
I/O pins
VDD
VBOR and VHYST
VBOR
RST08
Reset
RST04(1)
(due to BOR)
Note 1: Only if PWRTE bit in the Configuration Word register is programmed to 1; 2 ms delay if
PWRTE = 0.
Param
Sym. Characteristic Min. Typ Max. Units Conditions
No.
Param
Sym. Characteristic Min. Typ Max. Units Conditions
No.
AD20 TAD ADC Clock Period 1 9 s Using FOSC as the ADC clock
source ADOCS = 0
AD21 2 s Using FRC as the ADC clock
source ADOCS = 1
AD22 TCNV Conversion Time(1) 11 + 3TCY TAD Set of GO/DONE bit to Clear of GO/
DONE bit
AD23 TACQ Acquisition Time 2 s
AD24 THCD Sample and Hold Capacitor s FOSC-based clock source
Disconnect Time FRC-based clock source
*
These parameters are characterized but not tested.
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Does not apply for the ADCRC oscillator.
BSF ADCON0, GO
1 TCY
AD133
AD131
Q4
AD130
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
BSF ADCON0, GO
AD133 1 TCY
AD131
Q4
AD130
ADC_clk
ADC Data 9 8 7 6 3 2 1 0
ADIF 1 TCY
GO DONE
Note 1: If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This allows the
SLEEP instruction to be executed.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
CM01 VIOFF Input Offset Voltage 30 mV VICM = VDD/2
CM02 VICM Input Common Mode Range GND VDD V
CM03 CMRR Common Mode Input Rejection Ratio 50 dB
CM04 VHYST Comparator Hysteresis 15 25 35 mV
CM05 TRESP(1) Response Time, Rising Edge 300 600 ns
Response Time, Falling Edge 220 500 ns
* These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD.
2: A mode change includes changing any of the control register values, including module enable.
Param
Sym. Characteristics Min. Typ. Max. Units Comments
No.
Param.
Symbol Characteristic Min. Typ. Max. Units Conditions
No.
FVR01 VFVR1 1x Gain (1.024V) -4 +4 % VDD 2.5V, -40C to 85C
FVR02 VFVR2 2x Gain (2.048V) -4 +4 % VDD 2.5V, -40C to 85C
FVR03 VFVR4 4x Gain (4.096V) -5 +5 % VDD 4.75V, -40C to 85C
FVR04 TFVRST FVR Start-up Time 25 us
Param.
Sym. Characteristics Min Typ Max Units Comments
No.
ZC01 VPINZC Voltage on Zero Cross Pin 0.75 V
ZC02 IZCD_MAX Maximum source or sink current 600 A
ZC03 TRESPH Response Time, Rising Edge 1 s
TRESPL Response Time, Falling Edge 1 s
Data in Typ column is at 3.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
T0CKI
40 41
42
T1CKI
45 46
47 49
TMR0 or
TMR1
CC01 CC02
CC03
CK
US121 US121
DT
US120 US122
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US120 TCKH2DTV SYNC XMIT (Master and Slave) 80 ns 3.0V VDD 5.5V
Clock high to data-out valid 100 ns 1.8V VDD 5.5V
US121 TCKRF Clock out rise time and fall time 45 ns 3.0V VDD 5.5V
(Master mode) 50 ns 1.8V VDD 5.5V
US122 TDTRF Data-out rise time and fall time 45 ns 3.0V VDD 5.5V
50 ns 1.8V VDD 5.5V
CK
US125
DT
US126
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-setup before CK (DT hold time) 10 ns
US126 TCKL2DTL Data-hold after CK (DT hold time) 15 ns
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP75, SP76
SP74
SP73
SS
SP81
SCK
(CKP = 0)
SP71 SP72
SP79
SP73
SCK
(CKP = 1)
SP80
SP78
SP75, SP76
SP74
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SP78 SP79
SCK
(CKP = 1)
SP79 SP78
SP80
SP74
SP73
SP82
SS
SP70
SCK SP83
(CKP = 0)
SP71 SP72
SCK
(CKP = 1)
SP80
SP77
SP75, SP76
SDI
MSb In bit 6 - - - -1 LSb In
SP74
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
SCL
SP91 SP93
SP90 SP92
SDA
Start Stop
Condition Condition
Param
Symbol Characteristic Min. Typ Max. Units Conditions
No.
SP90* TSU:STA Start condition 100 kHz mode 4700 ns Only relevant for Repeated Start
Setup time 400 kHz mode 600 condition
SP91* THD:STA Start condition 100 kHz mode 4000 ns After this period, the first clock
Hold time 400 kHz mode 600 pulse is generated
SCL
SP90
SP106
SP107
SP91 SP92
SDA
In
SP110
SP109
SP109
SDA
Out
Param.
Symbol Characteristic Min. Max. Units Conditions
No.
SP100* THIGH Clock high time 100 kHz mode 4.0 s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 0.6 s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY
SP101* TLOW Clock low time 100 kHz mode 4.7 s Device must operate at a
minimum of 1.5 MHz
400 kHz mode 1.3 s Device must operate at a
minimum of 10 MHz
SSP module 1.5TCY
SP102* TR SDA and SCL rise 100 kHz mode 1000 ns
time 400 kHz mode 20 + 0.1CB 300 ns CB is specified to be from
10-400 pF
SP103* TF SDA and SCL fall time 100 kHz mode 250 ns
400 kHz mode 20 + 0.1CB 250 ns CB is specified to be from
10-400 pF
SP106* THD:DAT Data input hold time 100 kHz mode 0 ns
400 kHz mode 0 0.9 s
SP107* TSU:DAT Data input setup time 100 kHz mode 250 ns (Note 2)
400 kHz mode 100 ns
SP109* TAA Output valid from 100 kHz mode 3500 ns (Note 1)
clock 400 kHz mode ns
SP110* TBUF Bus free time 100 kHz mode 4.7 s Time the bus must be free
400 kHz mode 1.3 s before a new transmission
can start
SP111 CB Bus capacitive loading 400 pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns)
of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement
TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of
the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA
line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL
line is released.
PIC18F26K40
/SP e3
1526017
XXXXXXXXXXXXXXXXXXXX PIC18F26K40
XXXXXXXXXXXXXXXXXXXX /SO e3
XXXXXXXXXXXXXXXXXXXX 1526017
YYWWNNN
PIC18F26K40
/SS e3
1526017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIN 1 PIN 1
XXXXXXXX 18F26K40
XXXXXXXX /ML e3
YYWWNNN 1526017
526017
XXXXXXXXXXXXXXXXXX PIC18F45K40
XXXXXXXXXXXXXXXXXX /P e3
XXXXXXXXXXXXXXXXXX
YYWWNNN 1526017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
PIN 1 PIN 1
PIC18
F45K40
/MV e 3
1526017
44-Lead QFN (8x8x0.9 mm) Example
PIN 1 PIN 1
XXXXXXXXXXX 18F45K40
XXXXXXXXXXX /ML e3
XXXXXXXXXXX 1526017
YYWWNNN
XXXXXXXXXX 18F45K40
XXXXXXXXXX /PT e3
XXXXXXXXXX
YYWWNNN 1526017
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
!
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A A2
L c
A1 b1
b e eB
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
$%
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D
N
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1 2
b
NOTE 1
e
c
A A2
A1
L1 L
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
+ ,4 " 5 7 9;9 +,"!
<$ *'' =
5$
"# J
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
*
K%
6#/
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' * *%*
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NOTE 1
E1
1 2 3
A A2
L c
b1
A1
b e eB
V*# X9Y?
+#[+*# X X\ ]
X$+5
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**! _ _
%%! K K## _
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Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A B
N
NOTE 1
1
2
E
(DATUM B)
(DATUM A)
2X
0.20 C
2X
0.20 C TOP VIEW
0.10 C A1
C
SEATING A
PLANE 44X
A3 0.08 C
SIDE VIEW
L
0.10 C A B
D2
0.10 C A B
E2
K
2
1
NOTE 1 N
44X b
e 0.07 C A B
0.05 C
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 44
Pitch e 0.65 BSC
Overall Height A 0.80 0.90 1.00
Standoff A1 0.00 0.02 0.05
Terminal Thickness A3 0.20 REF
Overall Width E 8.00 BSC
Exposed Pad Width E2 6.25 6.45 6.60
Overall Length D 8.00 BSC
Exposed Pad Length D2 6.25 6.45 6.60
Terminal Width b 0.20 0.30 0.35
Terminal Length L 0.30 0.40 0.50
Terminal-to-Exposed-Pad K 0.20 - -
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
44
G2
1
2
V
EV
C2 Y2
G1
Y1
E SILK SCREEN
X1
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D A
D1 B
NOTE 2
(DATUM A)
(DATUM B)
E1 E
NOTE 1 A A
2X
N
0.20 H A B
2X 1 2 3
0.20 H A B 4X 11 TIPS
TOP VIEW
0.20 C A B
A A2
C
SEATING PLANE
0.10 C A1
SIDE VIEW
1 2 3
NOTE 1
44 X b
e 0.20 C A B
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(L1)
SECTION A-A
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 44
Lead Pitch e 0.80 BSC
Overall Height A - - 1.20
Standoff A1 0.05 - 0.15
Molded Package Thickness A2 0.95 1.00 1.05
Overall Width E 12.00 BSC
Molded Package Width E1 10.00 BSC
Overall Length D 12.00 BSC
Molded Package Length D1 10.00 BSC
Lead Width b 0.30 0.37 0.45
Lead Thickness c 0.09 - 0.20
Lead Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle 0 3.5 7
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exact shape of each corner is optional.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Revision B (5/2016)
Updated Example 11-6; Figures 37-1, 37-2, 37-5; Reg-
ister 31-5; Sections 1.1.2, 21.4.1, 21.4.2, 22.1.3,
22.1.9, 22.1.10, 37.2; Tables 37-1, 37-2, 37-3, 37-7, 37-
8, 37-9, 37-11, 37-13.
Removed Register 5-3.
Added long name bit/short name bits section 1.4 and
updated bit names accordingly.
Revision C (9/2016)
Updated Peripheral Module, Memory and Core fea-
tures descriptions on cover page. Updated the
PIC18(L)F2x/4xK40 Family Types Table. Updated
Examples 11-1, 11-3, 11-5 and 11-6; Figures 14-1 and
31-2; Registers 4-2, 4-5, 13-18 and 31-6; Sections 1.2,
4.4.1, 4.5, 4.5.4, 17.3, 17.5, 17.7, 18.1, 18.1.1,
18.1.1.1, 18.1.2, 18.1.6, 18.3, 18.4, 18.7, 19.0, 19.8.1,
20.0, 21.3, and 25.3; Tables 4-2, 37-2, 37-3, 37-5, 37-
13 and 37-14.
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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