Integrated Wireless Power Supply Receiver, Qi (Wireless Power Consortium) Compliant
Integrated Wireless Power Supply Receiver, Qi (Wireless Power Consortium) Compliant
Integrated Wireless Power Supply Receiver, Qi (Wireless Power Consortium) Compliant
bq51013A
bq51014
www.ti.com SLUSAY6B MARCH 2012 REVISED OCTOBER 2013
1FEATURES
Integrated Wireless Power Receiver Solution DESCRIPTION
with a 5V Regulated Supply The bq5101x is an advanced, integrated, receiver IC
93% Overall Peak AC-DC Efficiency for wireless power transfer in portable applications.
The device provides the AC/DC power conversion
Full Synchronous Rectifier
while integrating the digital control required to comply
WPC v1.0 Compliant Communication with the Qi v1.0 communication protocol. Together
Control with the bq500210 transmitter controller, the bq5101x
Output Voltage Conditioning enables a complete contact-less power transfer
system for a wireless power supply solution. By using
Only IC Required Between RX coil and 5V
near-field inductive power transfer, the receiver coil
DC Output Voltage embedded in the portable device receives the power
Dynamic Rectifier Control for Improved Load transmitted by the transmitter coil via mutually
Transient Response coupled inductors. The AC signal from the receiver
Dynamic Efficiency Scaling for Optimized coil is then rectified and regulated to be used as a
Performance Over any Range of Output Power power supply for down-system electronics. Global
feedback is established from the secondary to the
Adaptive Communication Limit for Robust transmitter in order to stabilize the power transfer
Communication During High Levels of Load process via back-scatter modulation. This feedback is
Current Noise established by using the Qi v1.0 communication
Supports 20-V Maximum Input protocol supporting up to 5 W applications.
Low-power Dissipative Rectifier Overvoltage The device integrates a low-impedance full
Clamp (VOVP = 15V) synchronous rectifier, low-dropout regulator, digital
Thermal Shutdown control, and accurate voltage and current loops. The
entire power stage (rectifier and LDO) use low
Multifunction NTC and Control Pin for resistive NMOS FETs to ensures high efficiency and
Temperature Monitoring, Done Charging and low power dissipation.
Fault Host Control
Power bq5101x
Stand-alone Digital Controller
Programmable Termination Pin for Charge AC to DC Drivers Rectification
Voltage
Conditioning
Load
APPLICATIONS Controller
V/I
Sense
Controller
Headsets
Digital Cameras Figure 1. Wireless Power Consortium
(WPC or Qi) Inductive Power System
Portable Media Players
Hand-held Devices
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 20122013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
bq51014 is Not Recommended For New Designs
bq51013A
bq51014
SLUSAY6B MARCH 2012 REVISED OCTOBER 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
Ordering Number
Part NO Marking Function Package Quantity
(Tape and Reel)
bq51013AYFPR 3000
DSBGA-YFP
bq51013AYFPT 250
bq51013A bq51013A 5V Regulated Power Supply
bq51013ARHLR 3000
QFN-RHL
bq51013ARHLT 250
bq51014YFPR 3000
bq51014 bq51014 5V Regulated Power Supply DSBGA-YFP
bq51014YFPT 250
AVAILABLE OPTIONS
Over
WPC Termination Communication
Device Function VRECT-OVP VOUT-(REG) Current AD-OVP
Version (CS100) Current Limit (1) (2)
Shutdown
Tracking + 1s Hold-
bq51013A 5V Power Supply v1.0 15V 5V Disabled Disabled Disabled
Off
Tracking + 1s Hold-
bq51014 5V Power Supply v1.0 15V 5V Enabled 12.5V Enabled
Off
(1) All voltages are with respect to the VSS terminal, unless otherwise noted.
(2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
THERMAL INFORMATION
RHL YFP
THERMAL METRIC (1) UNITS
20 PiNS 28 PINS
JA Junction-to-ambient thermal resistance 37.7 58.9
JCtop Junction-to-case (top) thermal resistance 35.5 0.2
JB Junction-to-board thermal resistance 13.6 9.1
C/W
JT Junction-to-top characterization parameter 0.5 1.4
JB Junction-to-board characterization parameter 13.5 8.9
JCbot Junction-to-case (bottom) thermal resistance 2.7 n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
bq5101x
AD-EN System
Load
AD
OUT
C COMM1
COMM1 C4
CBOOT1 D1
BOOT1
C1 RECT
AC1 R4
C3
HOST
COIL C2
TS-CTRL
AC2
NTC
BOOT2
CBOOT2
COMM2 CHG
CCOMM2 3 - State
Figure 2. bq5101x Used as a Wireless Power Receiver and Power Supply for System Loads
System
USB or Q1 Load
AC Adapter
Input D2 (bq51014)
bq5101x
AD-EN
AD
OUT
C COMM1
COMM1 C4
C5 C BOOT1 D1
BOOT1
C1 RECT
AC1 R4
C3
COIL C2
TS-CTRL
AC2
NTC
BOOT2
C BOOT2 HOST
COMM2 CHG
CCOMM2 Tri-State
CLAMP2 EN1 or TERM Bi-State
CCLAMP2
EN2 Bi-State
CLAMP1
C CLAMP1
ILIM FOD PGND
RTERM
(bq51014)
R1
140
Figure 3. bq5101x Used as a Wireless Power Receiver and Power Supply for System Loads With Adapter
Power-Path Multiplexing
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, 40C to 125C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UVLO Undervoltage lock-out VRECT: 0V 3V 2.5 2.7 2.8 V
Hysteresis on UVLO VRECT: 3V 2V 250 mV
VHYS
Hysteresis on OVP VRECT: 16V 5V 150 mV
VRECT Input overvoltage threshold VRECT: 5V 16V 14.5 15 15.5 V
Dynamic VRECT Threshold 1 ILOAD < 0.1 x IILIM (ILOAD rising) 7.08
0.1 x IILIM < ILOAD < 0.2 x IILIM
Dynamic VRECT Threshold 2 6.28
(ILOAD rising)
VRECT-REG V
0.2 x IILIM < ILOAD < 0.4 x IILIM
Dynamic VRECT Threshold 3 5.53
(ILOAD rising)
Dynamic VRECT Threshold 4 ILOAD > 0.4 x IILIM (ILOAD rising) 5.11
ILOAD Hysteresis for dynamic VRECT
ILOAD ILOAD falling 4%
thresholds as a % of IILIM
Rectifier undervoltage protection, restricts
VRECT-DPM 3 3.1 3.2 V
IOUT at VRECT-DPM
Rectifier reverse voltage protection at the VRECT-REV = VOUT - VRECT,
VRECT-REV 8 9 V
output VOUT = 10V
Quiescent Current
ILOAD = 0 mA, 0C TJ 85C 8 10 mA
Active chip quiescent current consumption
IRECT ILOAD = 300 mA, 0C TJ
from RECT 2 3.0 mA
85C
Quiescent current at the output when
IOUT VOUT = 5 V, 0C TJ 85C 20 35 A
wireless power is disabled (Standby)
ILIM Short Circuit
Highest value of ILIM resistor considered a RILIM: 200 50. IOUT
RILIM 120
fault (short). Monitored for IOUT > 100 mA latches off, cycle power to reset
Deglitch time transition from ILIM short to
tDGL 1 ms
IOUT disable
ILIM-SHORT,OK enables the ILIM short
comparator when IOUT is greater than this ILOAD: 0 20 0mA 120 145 165 mA
ILIM_SC value
Hysteresis for ILIM-SHORT,OK comparator ILOAD: 0 200 mA 30 mA
Maximum ILOAD that will be
IOUT Maximum output current limit, CL delivered for 1 ms when ILIM is 2.4 A
shorted
OUTPUT
ILOAD = 1000 mA 4.82 4.95 5
VOUT-REG Regulated output voltage V
ILOAD = 10 mA 4.92 5 5.05
RLIM = KILIM / IILIM, where IILIM is A
Current programming factor for hardware
KILIM the hardware current limit. IOUT 280 300 320
short circuit protection
=1A
IIMAX = KIMAX / RLIM where IMAX A
Current programming factor for the nominal is the maximum normal
KIMAX 230 250 270
operating current operating current.
IOUT = 1 A
IOUT Current limit programming range 1500 mA
IOUT > 300 mA IOUT + 50 mA
ICOMM Current limit during WPC communication
IOUT < 300 mA 350 390 435 mA
Hold off time for the communication current
tHOLD 1 s
limit during startup
DEVICE INFORMATION
SIMPLIFIED BLOCK DIAGRAM
M1
RECT I OUT
VREF,ILIM VOUT,FB
+ _
VILIM _ + VOUT,REG
VREF,IABS
+
VIABS,FB _
ILIM
VIN,FB
+
VIN,DPM _ AD
+
_
VREFAD,OVP
BOOT2 _
+
BOOT1
VREFAD,UVLO
AD-EN
AC1
AC2 Sync
Rectifier VREF,TS-BIAS
+ VFOD
Control _ FOD
COMM1 TS_COLD +
VBG,REF _
VIN,FB
COMM2 VOUT,FB TS_HOT +
_
DATA _ VILIM
OUT VIABS,FB
ADC
CLAMP1 VIABS,REF TS-CTRL
VIC,TEMP TS_DETECT +
VREF_100MV
_
_ ILIM
CHG
EN1 or
TERM
200kW
VRECT
VOVP,REF
+ OVP EN2
_
200kW
PGND
A1 A2 A3 A4 AC1 AC2
PGND PGND PGND PGND 2 19
B1 B2 B3 B4 BOOT1
3
RECT
18
AC2 AC2 AC1 AC1
OUT BOOT2
4 17
C1 C2 C3 C4
BOOT2 RECT RECT BOOT1
CLMP1 CLMP2
5 16
D1 D2 D3 D4
OUT OUT OUT OUT
COM1 COM2
6 15
E1 E2 E3 E4
COM2 CLMP2 CLMP1 COM1 CHG FOD
7 14
F1 F2 F3 F4 TS-
AD-EN
TS-CTRL FOD /AD-EN /CHG 8 CTRL
13
G1 G2 G3 G4 AD ILIM
EN1 or 9 12
ILIM EN2 TERM
AD
EN1or EN2
TERM
11
10
PIN FUNCTIONS
NAME YFP RHL I/O DESCRIPTION
AC1 B3, B4 2 I
AC input from receiver coil antenna.
AC2 B1, B2 19 I
BOOT1 C4 3 O Bootstrap capacitors for driving the high-side FETs of the synchronous rectifier. Connect a 10
nF ceramic capacitor from BOOT1 to AC1 and from BOOT2 to AC2.
BOOT2 C1 17 O
Filter capacitor for the internal synchronous rectifier. Connect a ceramic capacitor to PGND.
RECT C2, C3 18 O
Depending on the power levels, the value may be 4.7 F to 22 F.
D1, D2, D3,
OUT 4 O Output pin, delivers power to the load.
D4
Open-drain output used to communicate with primary by varying reflected impedance. Connect
through a capacitor to either AC1 or AC2 for capacitive load modulation (COM2 must be
COM1 E4 6 O connected to the alternate AC1 or AC2 pin). For resistive modulation connect COM1 and
COM2 to RECT via a single resistor; connect through separate capacitors for capacitive load
modulation.
Open-drain output used to communicate with primary by varying reflected impedance. Connect
through a capacitor to either AC1 or AC2 for capacitive load modulation (COM1 must be
COM2 E1 15 O connected to the alternate AC1 or AC2 pin). For resistive modulation connect COM1 and
COM2 to RECT via a single resistor; connect through separate capacitors for capacitive load
modulation.
CLMP2 E2 16 O Open drain FETs which are utilized for a non-power dissipative over-voltage AC clamp
protection. When the RECT voltage goes above 15 V, both switches will be turned on and the
capacitors will act as a low impedance to protect the IC from damage. If used, Clamp1 is
CLMP1 E3 5 O required to be connected to AC1, and Clamp2 is required to be connected to AC2 via 0.47F
capacitors.
A1, A2, A3,
PGND 1, 20 Power ground
A4
Spacer
TYPICAL CHARACTERISTICS
100.0 100.0
90.0
Efficiency (%)
80.0
80.0
70.0
60.0 70.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 1.0 2.0 3.0 4.0 5.0
Output Power (W) Output Power (W)
6.5
40
< Dynamic Rectifier Control
6.0
30
20
5.5
RILIM=500
10 RILIM=220
Figure 6. Light Load Efficiency Improvement due to Figure 7. VRECT vs. ILOADat RILIM = 220
Dynamic Efficiency Scaling Feature(1)
1.2
RILIM=220 RILIM=500 RILIM=250
1.1 RILIM=400
RILIM=700
1.0 RILIM=300
7.0
0.8
Current Limit (A)
6.5
0.7
0.6
6.0 0.5
0.4
0.3
5.5
0.2
0.1
0.0 0.2 0.4 0.6 0.8 1.0 1.0 2.0 3.0 4.0 5.0
Output Current (A) Output Voltage (V)
G007 G001
Figure 8. VRECT vs. ILOAD at RILIM = 220 and 500 Figure 9. VOUT Sweep (I-V Curve)(2)
90.0
5.00
80.0
4.99
70.0
4.98
60.0
4.97
50.0
4.96
40.0
4.95
30.0
0.2 0.4 0.6 0.8 1.0 1.2 0.0 0.2 0.4 0.6 0.8 1.0
Load Current (A) Load Current (A)
Figure 10. ILOAD Sweep (I-V Curve) Figure 11. Output Ripple vs. ILOAD (COUT = 1F)
5.004
5.002
Vout (V)
5.000
4.998
0 20 40 60 80 100 120
Temperature (C)
VRECT
VOUT
Figure 14. 1A Instantaneous Load Dump(3) Figure 15. 1A Load Step Full System Response
VRECT
VRECT
VOUT
VOUT
Figure 16. 1A Load Dump Full System Response Figure 17. Rectifier Overvoltage Clamp (fop = 110kHz)
VTS/CTRL
VRECT
VRECT
VOUT
VAD
VRECT VAD_EN
VOUT VOUT
Figure 20. Adapter Insertion (VAD = 10V) Illustrating Break- Figure 21. 20V adapter Insertion with AD OVP Enabled
Before-Make Operation (bq51014) and Wireless Power not Present
VAD_EN
VAD
VAD
VOUT
VRECT
Figure 22. AD OVP Condition While Wireless Charging is Figure 23. On the Go Enabled (VOTG = 3.5V)(4)
Active (bq51014)
IOUT
IOUT
VRECT
VRECT VOUT
VOUT
Figure 24. bq5101x Typical Startup with a 1A System Load Figure 25. Adaptive Communication Limit Event Where the
400 mA Current Limit is Enabled (IOUT-DC < 300 mA)
IOUT
VRECT
VOUT
Figure 26. Adaptive Communication Limit Event Where the Figure 27. Rx Communication Packet Structure
Current Limit is IOUT + 50 mA (IOUT-DC > 300 mA)
(1) Efficiency measured from DC input to the transmitter to DC output of the receiver. Transmitter was the bq500210 EVM. Measurement
subject to change if an alternate transmitter is used.
(2) Curves illustrates the resulting ILIM current by sweeping the output voltage at different RILIM settings. ILIM current collapses due to the
increasing power dissipation as the voltage at the output is decreasedthermal shutdown is occurring.
(3) Total droop experienced at the output is dependent on receiver coil design. The output impedance must be low enough at that particular
operating frequency in order to not collapse the rectifier below 5V.
(4) On the go mode is enabled by driving EN1 high. In this test the external PMOS is connected between the output of the bq5101x IC and
the AD pin; therefore, any voltage source on the output is supplied to the AD pin.
PRINCIPLE OF OPERATION
Power bq5101x
Voltage
AC to DC Drivers Rectification Load
Conditioning
Communication
V/I Controller
Controller
Sense
bq500210
Transmitter Receiver
Figure 28. WPC Wireless Power System Indicating the Functional Integration of the bq5101x
Details of a Qi Wireless Power System and bq5101x Power Transfer Flow Diagrams
The bq5101x family integrates a fully compliant WPC v1.0 communication algorithm in order to streamline
receiver designs (no extra software development required). Other unique algorithms such has Dynamic Rectifier
Control are also integrated to provide best in class system performance. This section provides a high level
overview of these features by illustrating the wireless power transfer flow diagram from startup to active
operation.
During startup operation, the wireless power receiver must comply with proper handshaking to be granted a
power contract from the Tx. The Tx will initiate the hand shake by providing an extended digital ping. If an Rx is
present on the Tx surface, the Rx will then provide the signal strength, configuration and identification packets to
the Tx (see volume 1 of the WPC specification for details on each packet). These are the first three packets sent
to the Tx. The only exception is if there is a true shutdown condition on the EN1/EN2, AD, or TS-CTRL pins
where the Rx will shut down the Tx immediately. See Table 4 for details. Once the Tx has successfully received
the signal strength, configuration and identification packets, the Rx will be granted a power contract and is then
allowed to control the operating point of the power transfer. With the use of the bq5101x Dynamic Rectifier
Control algorithm, the Rx will inform the Tx to adjust the rectifier voltage above 7 V prior to enabling the output
supply. This method enhances the transient performance during system startup. See Figure 29 for the startup
flow diagram details.
Tx Powered
without Rx
Active
Yes
EN1/EN2/AD/TS-CTRL Send EPT packet with
EPT Condition? reason value
No
Identification and No
Configuration and SS,
Received by Tx?
Yes
Power Contract
Established. All
proceeding control is
dictated by the Rx.
No
Rx Active
Power Transfer
Stage
Once the startup procedure has been established, the Rx will enter the active power transfer stage. This is
considered the main loop of operation. The Dynamic Rectifier Control algorithm will determine the rectifier
voltage target based on a percentage of the maximum output current level setting (set by KIMAX and the ILIM
resistance to GND). The Rx will send control error packets in order to converge on these targets. As the output
current changes, the rectifier voltage target will dynamically change. As a note, the feedback loop of the WPC
system is relatively slow where it can take up to 90 ms to converge on a new rectifier voltage target. It should be
understood that the instantaneous transient response of the system is open loop and dependent on the Rx coil
output impedance at that operating point. More details on this will be covered in the section Receiver Coil Load-
Line Analysis. The main loop will also determine if any conditions in Table 4 are true in order to discontinue
power transfer. See Figure 30 which illustrates the active power transfer loop.
Rx Active
Power Transfer
Stage
No
No
No
No
No
Another requirement of the WPC v1.0 specification is to send the measured rectifier power. This entitles the Rx
to determine the rectifier voltage and output current in order to report this to the Tx as a percentage of the
maximum output power. This is also handled in the active power transfer loop.
If the device is a bq51014, a special state called the TERM STATE is enabled in the active power transfer loop.
This state is used to determine the level of the output current versus the programmed level of termination current
(set by the KTERM factor and RTERM resistor). The primary purpose of this feature is to determine if the charge
status is 100% based on the output current from the Rx. In a condition where the mobile device battery is fully
charged, a low system current (output current from Rx) signature can be determined. This current level
(signature) is set by the end system designer and is termed ITERM-HI. In addition to this current level, there is a no-
load termination current level termed ITERM-LO which is fixed at 40 mA. For the high termination condition to be
true, the output current must be between ITERM-HI and ITERM-LO for approximately 180s. Once this condition is true,
the Rx will send charge status of 100% to the Tx. The Tx can then illustrate that the mobile device has been fully
charged (100% charged). If the output current remains below ITERM-LO for ~7s then the charge status of 100% is
immediately sent. This condition can occur if the mobile device is put into a low standby mode after the battery is
fully charged. See Figure 31 for the flow diagram of the TERM STATE.
TERM STATE
(bq51014 only)
No No
No No
Rx Active
Power Transfer
Stage
Figure 31. TERM STATE Flow Diagram for the bq51014 Only
Table 1.
Output Current Percentage RILIM = 500 RILIM = 220 VRECT
IMAX = 0.5A IMAX = 1.14 A
0 to 10% 0 A to 0.05 A 0 A to 0.114 A 7.08 V
10 to 20% 0.05 A to 0.1A 0.114 A to 0.227 A 6.28 V
20 to 40% 0.1 A to 0.2 A 0.227 A to 0.454 A 5.53 V
>40% > 0.2 A > 0.454 A 5.11 V
Figure 8 illustrates the shift in the Dynamic Rectifier Controll behavior based on the two different RILIM settings.
With the rectifier voltage (VRECT) being the input to the internal LDO, this adjustment in the Dynamic Rectifier
Control thresholds will dynamically adjust the power dissipation across the LDO where:
( )
PDIS = VRECT - VOUT IOUT
(1)
Figure 6 illustrates how the system efficiency is improved due to the Dynamic Efficiency Scaling feature. Note
that this feature balances efficiency with optimal system transient response.
RILIM Calculations
The bq5101x includes a means of providing hardware overcurrent protection by means of an analog current
regulation loop. The hardware current limit provides an extra level of safety by clamping the maximum allowable
output current (e.g. a current compliance). The RILIM resistor size also set the thresholds for the dynamic rectifier
levels and thus providing efficiency tuning per each applications maximum system current. The calculation for
the total RILIM resistance is as follows:
R ILIM = 250
IMAX
IILIM = 1.2 IMAX = 300
R ILIM
R ILIM = R1 + 140 (2)
Where IMAX is the expected maximum output current during normal operation and IILIM is the hardware over
current limit. When referring to the application diagram shown in Figure 2, RILIM is the sum of 140 and the R1
resistance (e.g. the total resistance from the ILIM pin to GND).
ITERM-HI
ITERM-LO
t
t LO = 7s tHI = 180s
Input Overvoltage
If the input voltage suddenly increases in potential (e.g. a change in position of the equipment on the charging
pad), the voltage-control loop inside the bq5101x becomes active, and prevents the output from going beyond
VOUT-REG. The receiver then starts sending back error packets to the transmitter every 30ms until the input
voltage comes back to the VRECT-REG target, and then maintains the error communication every 250ms.
If the input voltage increases in potential beyond VOVP, the IC switches off the LDO and communicates to the
primary to bring the voltage back to VRECT-REG. In addition, a proprietary voltage protection circuit is activated by
means of CCLAMP1 and CCLAMP2 that protects the IC from voltages beyond the maximum rating of the IC (e.g.
20V).
Table 2.
EN1 EN2 Result
Adapter control enabled. If adapter is present then secondary charger is
0 0 powered by adapter, otherwise wireless charging is enabled when wireless
power is available. Communication current limit is enabled.
0 1 Disables communication current limit.
AD-EN is pulled low, whether or not adapter voltage is present. This feature
1 0
can be used, e.g., for USB OTG applications.
Adapter and wireless charging are disabled, i.e., power will never be
1 1
delivered by the OUT pin in this mode.
Table 3.
Adaptive
EN1 EN2 Wireless Power Wired Power OTG Mode Communication EPT Termination
Limit
0 0 Enabled Priority (1) Disabled Enabled Not Sent to Tx
0 1 Enabled Priority (1) Disabled Disabled Not Sent to Tx
(2)
1 0 Disabled Enabled Enabled N/A Sent to Tx
1 1 Disabled Disabled Disabled N/A Sent to Tx
(1) If both wired and wireless power are present, wired power is given priority.
(2) Allows for a boost-back supply to be driven from the output terminal of the Rx to the adapter port via the external back-to-back PMOS
FET.
As described in Table 2, pulling EN2 high disables the adapter mode and only allows wireless charging. In this
mode the adapter voltage will always be blocked from the OUT pin. An application example where this mode is
useful is when USB power is present at AD, but the USB is in suspend mode so that no power can be taken from
the USB supply. Pulling EN1 high enables the off-chip PMOS regardless of the presence of a voltage. This
function can be used in USB OTG mode to allow a charger connected to the OUT pin to power the AD pin.
Finally, pulling both EN1 and EN2 high disables both wired and wireless charging.
NOTE
It is required to connect a back-to-back PMOS between AD and OUT so that voltage is
blocked in both directions. Also, when AD mode is enabled no load can be pulled from the
RECT pin as this could cause an internal device overvoltage in bq5101x.
Table 4.
Reason Value Condition
Unknown 0x00 AD > 3.6V
Charge Complete 0x01 TS/CTRL = 1, or EN1 = 1, or <EN1 EN2> = <11>
Internal Fault 0x02 TJ > 150C or RILIM < 100
Over Temperature 0x03 TS < VHOT, TS > VCOLD, or TS/CTRL < 100mV
Over Voltage 0x04 Not Sent
Over Current 0x05 IOUT > 90% of ILIM (bq51014 only)
Battery Failure 0x06 Not Sent
Reconfigure 0x07 Not Sent
No Response 0x08 VRECT target doesn't converge
Status Outputs
bq5101x has one status output, CHG. This output is an open-drain NMOS device that is rated to 20V. The open-
drain FET connected to the CHG pin will be turned on whenever the output of the power supply is enabled.
Please note, the output of the power supply will not be enabled if the VRECT-REG does not converge at the no-load
target voltage.
CRES1
AC1
VRECT
R MOD
COIL C RES2
AC2 GND
CRES1
AC1
VRECT
C MOD
COIL C RES2
AC2 GND
The amplitude change in Tx coil voltage or current can be detected by the transmitters decoder. The resulting
signal observed by the Tx is shown in Figure 35.
Power bq5101x
Voltage
AC to DC Drivers Rectification Load
Conditioning
Communication
V/I Controller
Controller
Sense
bq500210
Transmitter Receiver
1 1
0 0 0
Figure 35.
The WPC protocol uses a differential bi-phase encoding scheme to modulate the data bits onto the Tx coil
voltage/current. Each data bit is aligned at a full period of 0.5 ms (tCLK) or 2 kHz. An encoded ONE results in two
transitions during the bit period and an encoded ZERO results in a single transition. See Figure 36 for an
example of the differential bi-phase encoding.
Figure 36. Differential Bi-phase Encoding Scheme (WPC volume 1: Low Power, Part 1 Interface
Definition)
The bits are sent LSB first and use an 11-bit asynchronous serial format for each portion of the packet. This
includes one start bit, n-data bytes, a parity bit, and a single stop bit. The start bit is always ZERO and the parity
bit is odd. The stop bit is always ONE. Figure 37 shows the details of the asynchronous serial format.
Figure 37. Asynchronous Serial Formatting (WPC volume 1: Low Power, Part 1 Interface Definition)
Figure 38. Packet Format (WPC volume 1: Low Power, Part 1 Interface Definition)
Figure 27 above shows an example waveform of the receiver sending a rectified power packet (header 0x04).
Communication Modulator
bq5101x provides two identical, integrated communication FETs which are connected to the pins COM1 and
COM2. These FETs are used for modulating the secondary load current which allows bq5101x to communicate
error control and configuration information to the transmitter. Figure 39 below shows how the COMM pins can be
used for resistive load modulation. Each COMM pin can handle at most a 24 communication resistor.
Therefore, if a COMM resistor between 12 and 24 is required COM1 and COM2 pins must be connected in
parallel. bq5101x does not support a COMM resistor less than 12.
RECTIFIER
24W 24W
COMM1 COMM2
COMM_DRIVE
In addition to resistive load modulation, the bq5101x is also capable of capacitive load modulation as shown in
Figure 40 below. In this case, a capacitor is connected from COM1 to AC1 and from COM2 to AC2. When the
COMM switches are closed there is effectively a 22 nF capacitor connected between AC1 and AC2. Connecting
a capacitor in between AC1 and AC2 modulates the impedance seen by the coil, which will be reflected in the
primary as a change in current.
Table 5.
IOUT Communication Current Limit
< 300 mA Fixed 400 mA
> 300 mA IOUT + 50 mA
The first mode is illustrated in Figure 25. In this plot, an output load pulse of 300 mA is periodically introduced on
a DC current level of 200 mA. Therefore, the 400 mA current limit is enabled. The pulses on VRECT indicate that a
communication packet event is occurring. When the output load pulse occurs, the regulator limits the pulse to a
constant 400 mA and; therefore, preserves communication. Note that VOUT drops to 4.5 V instead of GND. A
charger IC with an input voltage regulation set to 4.5 V allows this to occur by offloading the load transient
support to the mobile devices battery
The second mode is illustrated in Figure 26. In this plot, an output pulse of 200 mA is periodically introduced on a
DC current level of 400 mA. Therefore, the tracking current mode (IOUT + 50 mA) is enabled. In this mode the
bq5101x measures the active output current and sets the regulators current limit 50 mA above this
measurement. When the load pulse occurs during a communication packet event, the output current is regulated
to 450 mA. As the communication packet event has finished the output load is allowed to increase. Note that
during the time the regulator is in current limit VOUT is reduced to 4.5 V and 5 V when not in current limit.
Synchronous Rectification
The bq5101x provides an integrated, self-driven synchronous rectifier that enables high-efficiency AC to DC
power conversion. The rectifier consists of an all NMOS H-Bridge driver where the backgates of the diodes are
configured to be the rectifier when the synchronous rectifier is disabled. During the initial startup of the WPC
system the synchronous rectifier is not enabled. At this operating point, the DC rectifier voltage is provided by the
diode rectifier. Once VRECT is greater than UVLO, half synchronous mode will be enabled until the load current
surpasses 120 mA. Above 120 mA the full synchronous rectifier stays enabled until the load current drops back
below 100 mA where half synchronous mode is enabled instead.
VTSB (2.2V)
20k R2
TS-CTRL
R1
R3
NTC
Figure 41. NTC Circuit Used for Safe Operation of the Wireless Receiver Power Supply
The resistors R1 and R3 can be solved by resolving the system of equations at the desired temperature
thresholds. The two equations are:
R R
3 NTC TCOLD (
+ R1 )
%VCOLD =
R 3 + R NTC
TCOLD (
+ R1
100 )
R R
3 NTC TCOLD (
+ R1 )
+ R2
R 3 + R NTC
TCOLD (
+ R1
)
R R
3 ( NTC THOT
+ R1 )
R 3 + (R NTC + R1 )
TCOLD = 10C
THOT = 100C
= 3380
RO = 10k
The plot of the percent VTSB vs. temperature is shown in Figure 42:
Figure 42. Example Solution for an NTC resistor with RO = 10K and = 4500
Figure 43 illustrates the periodic biasing scheme used for measuring the TS state. The TS_READ signal enables
the TS bias voltage for 24ms. During this period the TS comparators are read (each comparator has a 10 ms
deglitch) and appropriate action is taken based on the temperature measurement. After this 24ms period has
elapsed, the TS_READ signal goes low, which causes the TS-Bias pin to become high impedance. During the
next 35ms (priority packet period) or 235ms (standard packet period), the TS voltage is monitored and compared
to 100mV. If the TS voltage is greater than 100mV then a secondary device is driving the TS/CTRL pin and a
CTRL = 1 is detected.
240 ms
240 ms
TERM
M3
TS-CTRL
FAULT
M4
Note that the signals TERM and FAULT are given by two GPIOs. The truth table for this circuit is found in
Table 6:
Table 6.
TERM FAULT F (Result)
1 0 Z (Normal Mode)
0 0 Charge Complete
1 1 System Fault
The default setting is TERM = 1 and FAULT = 0. In this condition, the TS-CTRL net is high impedance (hi-z) and;
therefore, the NTC is function is allowed to operate. When the TS-CTRL pin is pulled to GND by setting FAULT =
1, the Rx is shutdown with the indication of a fault. When the TS-CTRL pin is pulled to the battery by setting
TERM = 1, the Rx is shutdown with the indication of a charge complete condition. Therefore, the host controller
can indicate whether the Rx is system is turning off due to a fault or due to a charge complete condition.
Thermal Protection
The bq5101x includes a thermal shutdown protection. If the die temperature reaches TJ(OFF), the LDO is shut
off to prevent any further power dissipation.
Ls C2
Section 4.2 (Power Receiver Design Requirements) in volume 1 of the WPC v1.0 specification highlights in detail
the sizing requirements. To summarize, the receiver designer will be required take inductance measurements
with a fixed test fixture. The test fixture is shown in Figure 46:
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: bq51013A bq51014
bq51014 is Not Recommended For New Designs
bq51013A
bq51014
SLUSAY6B MARCH 2012 REVISED OCTOBER 2013 www.ti.com
Figure 46. WPC v1.0 Receiver Coil Test Fixture for the Inductance Measurement Ls (copied from System
Description Wireless Power Transfer, volume 1: Low Power, Part 1 Interface Definition, Version 1.0.1,
Figure 4-4)
The primary shield is to be 50 mm x 50 mm x 1 mm of Ferrite material PC44 from TDK Corp. The gap dZ is to be
3.4 mm. The receiver coil, as it will be placed in the final system (e.g. the back cover and battery must be
included if the system calls for this), is to be placed on top of this surface and the inductance is to be measured
at 1-V RMS and a frequency of 100 kHz. This measurement is termed Ls. The same measurement is to be
repeated without the test fixture shown in Figure 11. This measurement is termed Ls or the free-space
inductance. Each capacitor can then be calculated using Equation 6:
-1
2
C =
1
( S )
f 2p L'
S
-1
2
C =
2 (fD 2p) 1
L -
S C
1 (6)
Where fS is 100 kHz +5/-10% and fD is 1 MHz 10%. C1 must be chosen first prior to calculating C2.
The quality factor must be greater than 77 and can be determined by Equation 7:
2p f LS
Q= D
R (7)
where R is the DC resistance of the receiver coil. All other constants are defined above.
A
CP CS
VIN
LP L S CD CB V RL
Where:
VIN is a square-wave power source that should have a peak-to-peak operation of 19V.
CP is the primary series resonant capacitor (i.e. 100 nF for Type A1 coil).
LP is the primary coil of interest (i.e. Type A1).
LS is the secondary coil of interest.
CS is the series resonant capacitor chosen for the receiver coil under test.
CD is the parallel resonant capacitor chosen for the receiver coil under test.
CB is the bulk capacitor of the diode bridge (voltage rating should be at least 25 V and capacitance value of at
least 10 F)
V is a Kelvin connected voltage meter
A is a series ammeter
RL is the load of interest
It is recommended that the diode bridge be constructed of Schottky diodes.
The test procedure is as follows
Supply a 19V AC signal to LP starting at a frequency of 210 kHz
Measure the resulting rectified voltage from no load to the expected full load
Repeat the above steps for lower frequencies (stopping at 110 kHz)
An example load-line analysis is shown in Figure 48:
20
18
175 kHz
16 160 kHz
150 kHz
14 140 kHz
125 kHz
VRECT (V)
12
115 kHz
10 135 kHz
130 kHz
8
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
LOAD (A)
What this plot conveys about the operating point is that a specific load and rectifier target condition consequently
results in a specific operating frequency (for the type A1 TX). For example, at 1 A the dynamic rectifier target is
5.15 V. Therefore, the operating frequency will be between 150kHz and 160kHz in the above example. This is an
acceptable operating point. If the operating point ever falls outside the WPC frequency range (110kHz
205kHz), the system will never converge and will become unstable.
In regards to transient analysis, there are two major points of interest:
1. Rectifier voltage at the ping frequency (175kHz).
2. Rectifier voltage droop from no load to full load at the constant operating point.
In this example, the ping voltage will be approximately 5 V. This is above the UVLO of the bq5101x and;
therefore, startup in the WPC system can be ensured. If the voltage is near or below the UVLO at this frequency,
then startup in the WPC system may not occur.
If the max load step is 1 A, the droop in this example will be Approximately1V with a voltage at 1 A of
Approximately 5.5 V (140 kHz load-line). To analyze the droop locate the load-line that starts at 7 V at no-load.
Follow this load-line to the max load expected and take the difference between the 7V no-load voltage and the
full-load voltage at that constant frequency. Ensure that the full-load voltage at this constant frequency is above
5V. If it descends below 5V, the output of the power supply will also droop to this level. This type of transient
response analysis is necessary due to the slow feedback response of the WPC system. This simulates the step
response prior to the WPC system adjusting the operating point.
NOTE
Coupling between the primary and secondary coils will worsen with misalignment of the
secondary coil. Therefore, it is recommended to re-analyze the load-lines at multiple
misalignments to determine where, in planar space, the receiver will discontinue operation.
Table 7.
Manufacturer Part Number Dimensions Ls Ls Output Current Application
Range
TDK WR-483250-15M2-G 48 x 32mm 10.4 H 12 H (1) 50-1000 mA General 5V Power
Supply
TDK WR-383250-17M2-G 38 x 32mm 11.1 H 12.3 H (1) 50-1000 mA Space limited 5V Power
Supply
Vishay IWAS-4832FF-50 48 x 32mm 10.8 H 12.5 H (1) 50-1000 mA General 5V Power
Supply
Mingstar 312-00012 48 x 32mm 10.8 H 12.9 H (1) 50-1000 mA General 5V power
Supply
Mingstar 312-00015 28 x 14mm 36.5 H 45 H (2) 150-1000 mA Space limited 5V Power
Supply
(1) Ls measurements conducted with a standard battery behind the Rx coil assembly. This measurement is subject to change based on
different battery sizes, placements, and casing material.
(2) Battery not present behind the Rx coil assembly. Subject to drop in inductance depending on the placement of the battery.
It is recommended that all inductance measurements are repeated in the designers specific system as there are
many influence on the final measurements.
Package Summary
YFP Package
(Top View)
YFP Package Symbol
(Top Side Symbol for bq51013A)
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4 TI YMLLLLS
D1 D2 D3 D4 D bq51013A
E1 E2 E3 E4
F1 F2 F3 F4
0-Pin A1 Marker, TI-TI Letters, YM- Year Month Date Code,
G1 G2 G3 G4 LLLL-Lot Trace Code, S-Assembly Site Code
E
Figure 49. Chip Scale Packaging Dimensions
D = 3.0mm 0.035mm
E = 1.88mm 0.035mm
REVISION HISTORY
Changed AC1, AC2 input voltage spec MINIMUM value from 0.3 to 0.8 in the Absolute Maximum Ratings table ......... 2
Changed condition statement of Electrical Characteristics section from "0C to 125C" to "40C to 125C" .................... 6
Changed UVLO spec MIN value from "2.6" to "2.5" ............................................................................................................. 6
Changed VOUT-REG spec MIN value from "4.85" to "4.82 for ILOAD = 1000 mA condition. ...................................................... 6
Changed VOUT-REG spec MIN value from "4.95" to "4.92 for ILOAD = 10 mA condition. .......................................................... 6
www.ti.com 15-Apr-2017
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
BQ51013ARHLR ACTIVE VQFN RHL 20 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 125 BQ51013A
& no Sb/Br)
BQ51013ARHLT ACTIVE VQFN RHL 20 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 125 BQ51013A
& no Sb/Br)
BQ51013AYFPR ACTIVE DSBGA YFP 28 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM 0 to 125 BQ51013A
& no Sb/Br)
BQ51013AYFPT ACTIVE DSBGA YFP 28 250 Green (RoHS SNAGCU Level-1-260C-UNLIM 0 to 125 BQ51013A
& no Sb/Br)
BQ51014YFPR NRND DSBGA YFP 28 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM 0 to 125 BQ51014
& no Sb/Br)
BQ51014YFPT NRND DSBGA YFP 28 250 Green (RoHS SNAGCU Level-1-260C-UNLIM 0 to 125 BQ51014
& no Sb/Br)
HPA01195YFPR ACTIVE DSBGA YFP 28 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM 0 to 125 BQ51013A
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jun-2015
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Jun-2015
Pack Materials-Page 2
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