International Journal of Engineering and Technical Research (IJETR)

ISSN: 2321-0869, Volume-3, Issue-5, May 2015

Synthesis of area Optimized 64 Bit Double Precision

Floating Point Multiplier Using VHDL
Kanwaljeet Kaur, Parminder Singh Jassal
is that it can support a much wider range of values. The
Abstract Floating point arithmetic is widely used in many floating point numbers is based on scientific notation. A
areas. IEEE Standard 754 floating point is the most common scientific notation is just another way to represent very large
representation today for real numbers on computers. The way of or very small numbers in a compact form such that they can be
floating point operations are executed depends on the data
easily used for computations. Binary floating point numbers
format of the operands. IEEE standards specify a set of floating
point formats for single precision and double precision. This
multiplication is one of the basic functions used in digital
paper presents synthesis of double precision floating point signal processing (DSP) application. The IEEE 754 standard
multiplier using VHDL. In this paper breakdown technique is provides the format for representation of Binary Floating
used for Synthesis of double precision floating point multiplier. point numbers in computers. The Binary Floating point
Double precision floating point multiplier with minimum delay numbers are represented in Single and Double formats. The
9.251 ns and with an area of 599 no of slices LUTS. Double Single precision format consists of 32 bits and the Double
precision FPM targeted on a Xilinx Virtex-6 xc6vlx75t-3ff484 precision format consists of 64 bits. The formats are
device.The double precision floating point multiplier was composed of 3 fields; Sign, Exponent and Mantissa.
simulated in MODEL SIM simulator and synthesized using
Xilinx ISE 13.2 tool.) floating point multiplication is widely
used in large set of scientific and signal processing computation.
Floating point number consists of three fields:
Floating Point Multiplication is one of the common arithmetic 1. SIGN (S): It used to denote the sign of the number i.e. 0
operations in these computations. An area optimized floating represent positive number and 1 represent negative number.
point double precision multiplier is implemented on a Virtex-6 2. SIGNIFICAND OR MANTISSA (M): Mantissa is part of a
FPGA. The design achieved with an area of 599 no of slices floating point number which represents the magnitude of the
LUTs as compared to[1]. number.
3. EXPONENT (E): Exponent is part of the floating point
Index TermsLUTs, Virtex-6 FPGA, Xilinx ISE 13.2, FPM. number that represents the number of places that the decimal
point (binary point) is to be moved.Number system is[2]
I. INTRODUCTION completely specified by specifying a suitable base ,
Multipliers are key components of many high performance significand (mantissa) M, and exponent E. A floating point
systems such as FIR filters, microprocessors, digital signal number F has the value
processors, etc. Multiplication based operations such as F=
multiply and accumulate(MAC) and inner product are among is the base of exponent and it is common to all floating point
some of the frequently used computation- intensive arithmetic numbers in a system.
functions currently implemented in many digital signal
processing (DSP) applications such as convolution, fast Sign Bit 8 Bit Biased 23Bit
fourier transform (FFT), filtering and in Exponent Signifiacnd/
Mantissa/
microprocessors in its arithmetic and logic unit. Since Fraction
multiplication dominates the execution time of most DSP Table1.1.IEEE Single Precision Data Format
algorithms, so there is a need of area optmized
multiplier.[1]Floating point number system is a common
choice for many scientific computations due to its wide II. CHOICE OF FLOATING POINT REPRESENTATION
dynamic range feature. For instance,floating point arithmetic
is widely used in many areas, especially in scientific The way floating point operations are executed depends on
computation, numerical processing, image processing and the specific format used for representing the operands. The
signal processing. The term floating point is derived from the choice of a floating point format for the hardware
fact that there is no fixed number of digits before and after the implementation of floating point units is governed by factors
decimal point, that is, the decimal point or binary point can like the dynamic range requirements, maximum affordable
float.[1] There are also representations in which the number computational errors, power consumption etc.[6] The
of digits before and after the decimal or binary point is fixed; exponent bit width decides the dynamic range of floating
called fixed-point representations. The advantage of point numbers while the significand bit width decides the
floating-point representation over fixed point representation resolution. The dynamic range offered by floating point units
is much higher than that offered by fixed point units of
equivalent bit width. Larger dynamic range is of significant
Kanwaljeet Kaur, Mtech Student, Department Of Electronics, Yadavindra interest in many computing applications like in multiply -
College Of Engineering, Talwandi Sabo(Pb)- INDIA. accumulate operation of DSPs. But larger range is not needed
Parminder Singh Jassal, Assistant Professor, Department Of
in all the applications.
Electronics, Yadavindra College Of Engineering, Talwandi Sabo(Pb)- (a) IEEE single precision data format
INDIA.

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 Synthesis of area Optimized 64 Bit Double Precision Floating Point Multiplier Using VHDL

(b) IEEE double precision data format product_e = mul_a[40:24] * mul_b[16:0]

productj= mul_a[40:24] * mutb[33:17]
Sign Bit 11Bit 52Bit product_g = mul_a[40:24] * mul_b[52:34]
Biased Significand/Fraction/Mantissa product_h = mul_a[52:41] * mul_b[16:0]
Exponent product_i =mul_a[52:41] * mul_b[33:17]
Table1.2.IEEE Doublele Precision Data Format productj =mul_a[52:41] * mul_b[52:34]

III. FLOATING POINT MULTIPLICATION V. VHDL CODE FOR MULTIPLICATION OF IEEE-754

Decimal number are also called floating point because a DOUBLE PRECISION NUMBERS
single number can be represented with one or more VHDL code for multiplication of double precision (64-bit)
significant digits depending on position of the decimal point. numbers is being developed and then is simulated using
Since the point floats between mass of digits that represent the Model Sim SE Plus 6.5. VHDL code is break down into small
number such numbers are termed as floating point number. components to handle normalisation, rounding, Exponents are
floating-point multiplication, by complies with the IEEE 754 added and significands are further multiplied. Sign bit is
Standard, the two mantissas are to be multiplied, and the two computed with XOR operation. Various sets of inputs are fed
exponents are to be added. The sign logic is a simple XOR. In to the block to get the results. The further part of the document
order to perform floating-point multiplication, a simple deals with simulation and synthesis results.
algorithm is realized:[6] 6.4 Model Sim Simulation
1. Adding the exponent of the two numbers then subtracting Consider multiplication of two decimal numbers:
the bias from their result. Inputs:
2. Multiplying the significant of the two numbers A and B Where A= -18.5 and B = 9.5
3. Calculating the sign by XOR ing the sign of the two Binary representation of operands:
numbers. A= -10010.0
2.5THE FOLLOWING STEPS ARE NECESSARY TO B = +1001.1
MULTIPLY TWO FLOATING POINT NUMBERS Normalized representation of operands:
1. Multiplying the significand i.e. (I.MI * I.M2) [1] A= - 1.0012^4
2. Placing the decimal point in the result B = + 1.00112^3
3. Adding the exponents i.e. (E I + E2 - Bias) IEEE representation of the operands:
4. Obtaining the sign i.e. sl xor s2 Operands A = 1 10000000011
5. Normalizing the result i.e. obtaining I at the 001000000000000000000000000000000000000000000000
MSB of the results "significant" 0000 = 64hc03000000000000
6. Rounding the result to fit in the available bits Operands B = 0 10000000010
7. Checking for underflow/overflow occurrence 001100000000000000000000000000000000000000000000
0000 = 64h4023000000000000
IV. IMPLEMENTATION OF DOUBLE PRECISION Outputs:
FLOATING POINT MULTIPLTER A B = -18.0 9.5 = -1.01010112^(1030-1023)
= -10101011.0 = =171
In this paper we implemented a double precision floating
Output_FPM = 64Hc065600000000000000000000000
point multiplier Figure 1.1 shows the multiplier structure that
underflow = 0, overflow = 0, inexact = 0, exception = 0,
includes exponents addition, significant multiplication, and
invalid = 0, ready = 1
sign calculation [1]
Sign A Sign B Exp.A Exp.B Man. A Man.B
VI. XILINX SYNTHESIS
This device has following attributes manifests in Table 1.2
shows the Device Utilisation Summary of the VHDL code, so
written, it is been observed that number of device parameters
XOR +
used are very less. Hence, an optimum Device Utilisation is
Bias obtained. From the timing report obtained, it is found that the
-
maximum combinational path delay is 9.251 ns. Maximum
combinational path delay is only for paths that start at an input
to the design and go to an output of the design without being
clocked along the way.
Multiplier Structure This design has implemented, simulated on model sim and
Fig no 1.1Multiplier structure synthesized for VHDL. Simulation based verification is one
of the method for functional verification for design. The test
bench form top module that instantiates other module. The
simulation verification ensure that design is functionally
1.5 The breakdown of the multiply in module (fJ:lU_mul) corrected when tested with a given set of inputs. Though it is
is broken up as follows : not fully complete, by picking random set of inputs as well as
product_a = mul_a[23:0] * mul_b[16:0] corner cases simulation based verification can still yield
product_b = mul_a[23:0] * mul_b[33:17] reasonably good results. The result obtained shown in figure
product_c = mul_a[23:0] * mul_b[50:34] 1.3 and figure 1.4.The following snapshots are take from
product_d = mul_a[23:0] * mutb[52:51]

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 International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-3, Issue-5, May 2015
Model Sim after timing simulation of the floating point A =
multiplier. 010000000000000110011001100000000000000000000000
0000000000000000
B =
010000000000000110011001100000000000000000000000
0000000000000000

Outputs:
AB = 2.2 2.2 =
Output FPM = 40235BF0A4000000
X =
010000000010001101011011111100001010010000000000
0000000000000000

Figure 1.2 Design Summary Of Double Precision Floating

Point Multiplier

A= -18.0
B= 9.5
M= 171

Figure 1.5 Simulation Results Of Double Precision Floating

Point Multiplier

Figure 1.3 Simulation Results Of Double Precision Floating

Point Multiplier

Figure 1.6 Simulation Results Of Double Precision Floating

Point Multiplier(Hexadecimal)

Table Of Comparison
Device parameter Our Work Addanki,
Double Precision Tilak,Prasad[1]
Double Precision
No Of LUTs 599 648

Delay 9.251ns

Figure 1.4 Simulation Results Of Double Precision Floating

VII. CONCLUSION AND FUTURE SCOPE
Point Multiplier(Hexadecimal)
The double precision floating point multiplier supports the
Consider multiplication of two decimal numbers: IEEE-754 binary interchange format, targeted on a Xilinx
Inputs: Virtex-6 xc6vlx75t-3ff484 FPGA. The design achieved with
A and B Where A= 2.2 and B = 2.2 minimum dealy 9.251 and an area of 599 slices. The
Binary representation of operands: implemented design is verified with double precision floating
A= 10.001100110011 point multiplier [6]. this double precision floating point
B = 10.001100110011 multiplier uses a breakdown technique that reduced the area
Normalized representation of operands: compared to single precession. This design handles the
A= 1.0001100110011 2 ^1 overflow, underflow, and normalization rounding mode
B = 1.00011001100112^1
IEEE representation of the operands:
Operands

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 Synthesis of area Optimized 64 Bit Double Precision Floating Point Multiplier Using VHDL

VIII. FUTURE SCOPE

Speed can improved using advanced algorithm like
BREAKDOWN TECHNIQUE, BOOTH, ARRAY,
DADDA, Algorithm etc.
ALU Can be designed for DSP Applications.

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