CODE No.

:14BT40405 SVEC-14

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech II Semester (SVEC14) Regular Examinations May - 2016
SWITCHING THEORY AND LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Communication Engineering,
Electronics and Instrumentation Engineering ]
Time: 3 hours Max. Marks: 70
Answer One Question from each Unit
All questions carry equal marks

1 a) Convert the following. 6 Marks

i) (11011.1011)2 to decimal.
ii) (3FA8.2C) 16 to equivalent binary representation.
iii) (7562.45)10 to Octal.
b) i) Subtract 1100110 and 1100001 using 2s complement form. 8 Marks
ii) Explain the construction of Hamming code for 1010 message bits.
(OR)
2 a) Simplify the following Boolean expressions using Boolean algebra properties 6 Marks
i) v + vw + vwx + vwx y + vwxy z
ii) ( xy + z ) + z + xy + wz
iii) x + xy + x z + x yz
b) Obtain the canonical SOP form of the following functions: 8 Marks
i) f(x, y, z) = (xy + z) (xz + y)
ii) f(A, B, C, D) = AD + BD + BD

3 a) Draw the multi level NOR circuit for the following. 7 Marks
(AB+CD)E + BC(A+B)
b) Simplify the Boolean function using tabular method 7 Marks
F(A,B,C,D) = (0,1,2,8,10,11,14,15) + d(3,5)
(OR)
4 a) Simplify the Boolean function and obtain its realization using only NAND 7 Marks
gates:
F(A,B,C,D) = (0,1,3,4,6,9,11) + d(2,5)
b) Assume propagation delay of EX-OR gate is 20ns and OR and AND gate is 7 Marks
10ns and then find the propagation delay 4 bit parallel adder.

5 a) Explain the operation of ripple carry adder with a neat diagram. 6 Marks
b) Design a 3-bit binary to gray code converter 8 Marks
(OR)
6 a) Implement the following function using (8 : 1) MUX and (4 : 1) MUX 8 Marks
f = (0,2,3,5,7)
b) Realize a full adder circuit using 3 x 8 decoder and OR gates. 6 Marks

1
7 a) Write the conversion procedures of the Flip Flops. Convert T Flip Flop to JK. 7 Marks
b) Draw a 4 bit parallel in serial out shift register and briefly explain. 7 Marks
(OR)
8 a) Draw an asynchronous decade counter and explain its operation. 7 Marks
b) Design and explain the function of 4-bit bidirectional shift register. 7 Marks

9 A combinational circuit is defined by the following functions: 14 Marks

F1(a, b, c) = (3,5,6,7)
F2(a, b, c) = (0, 2, 4, 7)
Implement a PLA circuit having 3- inputs 4 product terms and 2 outputs
(OR)
10 a) What are the different types of hazards in asynchronous sequential circuits? 6 Marks
b) Reduce the following state table using implication table method. 8 Marks

Next State, Output(z)

Present State
00 01 11 10
A C, 1 E,1 B,1
B E,0
C F,0 F,1
D B,1
E F,0 A,0 D,1
F C,0 B,0 C,1

2
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Supplementary Examinations May - 2015
SWITCHING THEORY AND LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]

Time: 3 hours Max. Marks: 70

Answer any FIVE questions
All questions carry equal marks
1. a) Convert the following numbers.
i) (26153.7406)8 to binary.
ii) (153.513)10 to octal.
iii) Convert (9B2.1A)16 to decimal
b) Using 10's complement, subtract 72532 - 3250.
c) Convert gray number 1110 to its Binary equivalent.
d) Determine the value of base x if (193) x = (623) 8

2. a) Simplify the following Boolean expressions to a minimum number of literals.

i) A'C'+ABC+AC'
ii) (x'y'+ z)'+z+ xy +wz
iii) (A'+C) (A'+C') (A+B+C'D)
b) Obtain the Dual of the following Boolean expressions.
i) AB'C+AB'D+A'B'
ii) A'B'C+ABC'+A'B'C'D
c) What do you mean by min terms and max terms of Boolean expressions?
d) Prove that AND-OR network is equivalent to NAND-NAND network.

3. a) Obtain the simplified SOP and POS expressions for F=A'B'C'+B'CD'+A'BCD'+AB'C'

b) Given F = (0,1,2,8,10,11,14,15). Simplify F using Tabulation method.

4. a) What are the hazards in an digital system and explain in detail about static, dynamic
and essential hazards?
b) Implement the following functions using a multiplexer
Y = C'B'A' + C'BA' + C'BA + CB'A + CBA.

5. Derive the ROM programming table for the combinational circuit that squares a 4 bit number.
Minimize the number of product terms.

6. a) Convert the following

i) SR Flip-Flop to JK Flip-Flop
ii) JK Flip-Flop to T Flip-Flop and D Flip-Flop
b) Design and explain the operation of a serial binary adder.

7. a) With an example explain the simplification of incompletely specified machines.

b) Explain merger chart methods.

8. a) Explain the features of ASM chart.

b) With an example, explain about sequential binary multiplier.

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Supplementary Examinations November - 2015
SWITCHING THEORY AND LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]
Time: 3 hours Max. Marks: 70
Answer any FIVE questions
All questions carry equal marks
1. a) What do you mean by self complementary code? Give examples.
b) Express decimal number 8620 in i) BCD; ii) Excess-3; iii) 2421 code.
c) Show that the dual of EX-OR gate is equal to its complement.
d) Explain about error detecting and correcting codes.

2. Simplify the following Boolean expressions using Boolean algebra:

i) AB + AB'C(B'C' + C) + (AC)'
ii) A'BC' + A'BC + AB'C' + ABC
iii) ABC'D' +ABC'D + ABCD' +ABCD
iv) AB + ABC' + A'BC +ABC
v) ABCD + ABCD' +A'BCD +A'BCD'

3. a) Simplify the Boolean function 'F' using don't care conditions 'd' in (i) SOP form (ii) POS
form F=A'B'D'+A'CD+A'BC, d=A'BC'D+ACD+AB'D'
b) Given F(A,B,C,D,E) = (0,2,4,6,9,11,13,15,17,21,25,27,29,31). Obtain the simplified SOP
form using k-map method.

4. a) What is Full adder? Implement full adder using 2 half adders.

b) Realize F=X'Z+WXY' using 4X16 decoder.
c) Implement Inverter using multiplexer.

5. Draw the internal construction of PLA having 3 inputs, 3 product terms and 2 output and realize the
following functions using it. F1 = m (0,1,3,5) and F2 = m (0,3,5,7).

6. a) Draw a 3 bit Jhonson counter and explain.

b) Design a 3 bit asynchronous UP/DOWN counter

7. a) Discuss about capabilities and limitations of finite state machine.

b) A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described
by the following flip-flop input equations :
JA = x KA = B'
JB = x KB = A
i) Derive the state equation A(t+1) and B(t+1) by substituting the input equations for the
J and K variables.
ii) Draw the state diagram of the circuit

8. a) Explain control and data path interaction in algorithmic state machines.

b) Draw the ASMD charts for the following state transition.
i) If x=1, control goes from state 'S1' to state 'S2';
ii) If x=0, generate a conditional operation R R + 2 and go from S1 to S2.

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Regular/Supplementary Examinations January - 2014
SWITCHING THEORY & LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
1. a) Given (75) x = (61)10 then what is the value of x
b) What is ASCII code? What are the ASCII codes for decimal digits?
c) Explain with an example how error detection and correction can be done using
hamming code.

2. a) Prove the following using Boolean algebra

i) ABC +AB'C + A'BC + ABC' + AB'C +A'B'C = A+ B'C
ii) AB + ABC + A'B + AB'C = B + AC
b) Implement the following logical expression using AND-OR-INVERTER gates and
also using only NAND gates: A + (B' + C) (D' +BE').

3. a) Simplify the Boolean function using K-map

F (A.B, C, D) = A'B'C'+ B'CD'+ A'BCD'+AB'C'
b) Simplify the Boolean function using the tabulation method.
F (A.B, C, D) = m (0, 1, 2, 8, 10, 11, 14, 15)

4. a) Implement the Boolean function with suitable multiplexer.

F (A.B, C, D) = m (0, 1, 2, 4, 6, 9, 12, 14).
b) A combinational circuit is defined by the following three functions
F1 = x' y' + x y z' , F2 =x' + y , F3 =x y + x' y'. Design the circuit with a decoder and
external gates.

5. a) Implement the following three Boolean functions with a PLA:

F1(A,B,C)=(0, 1, 2, 4);
F2(A,B,C)= (0, 5, 6, 7);
F3=(0, 3, 5, 7)
b) Explain about programmable array logic (PAL).

6. a) Draw the logic diagram of a 4 bit binary ripple counter using positive edge triggering.
b) Design Mod-10 Counter using JK Flip-Flops.

7. a) Draw the block diagrams of Mealy and Moore state machines and explain.
b) Explain the capabilities and limitations of Finite state machines.

8. a) Show the eight exit paths in an ASM block emanating from the decision boxes that check
the eight possible binary values of three control variables x,y and z .
b) Explain the features of ASM charts.

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Supplementary Examinations June - 2014
SWITCHING THEORY AND LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks

1. a) Convert the following numbers

i) (41.6875)10 to binary ii) (1001001.011)2 to decimal
iii) Find the 9's Complement of number (25.639)10
b) A receiver with even parity Hamming code is received the data as 1110110.
Determine the correct code.
c) Subtract 111001 from 101011 using 2's complement.

2. a) Simplify the following Boolean expressions to a minimum number of literals.

i) A'C'+ABC+AC' ii) (x'y'+ z)'+z+ xy +wz iii) (A'+C) (A'+C') (A+B+C'D)
b) Obtain the Dual of the following Boolean expressions.
i) AB'C+AB'D+A'B' ii) A'B'C+ABC'+A'B'C'D
c) What you mean by min terms and max terms of Boolean expressions?
d) Prove that AND-OR network is equivalent to NAND-NAND network.

3. a) Simplify the following Boolean function for minimal POS form using K-map.
F(W,X,Y,Z) = (4,5,6,7,8,12) + d(1,2,3,9,11,14)
b) Simplify the following Boolean expressions using K-map and implement them using
NAND gates: F (W, X, Y, Z) = W'X'Y'Z' + WXY'Z' + W'X'YZ + WXYZ.

4. a) Draw the truth tables of half subtractor and full subtractor. Implement these using only
NAND gates.
b) Design a combinational circuit that accepts a 3 bit number and generates an output binary
number equal to the square of the input number.

5. a) Design a combinational circuit using a PROM. The circuits accept 3 bit binary number and
generate its equivalent Excess-3 code.
b) Derive the PLA programming table for the combinational circuit that squares a 3 bit number.

6. a) Draw a 3 bit Jhonson counter and explain.

b) Design a 3 bit asynchronous UP/DOWN counter.

7. Determine minimal state equivalent of State table given below

NS,z
PS
X=0 X=1
A B,1 H,1
B F,1 D,1
C D,0 E,1
D C,0 F,1
E D,1 C,1
F C,1 C,1
G C,1 D,1
H C,0 A,1
1
8. a) Draw the ASM chart for weighing machine and explain with an example.
b) Draw the ASM chart for the following state transition:
i) If x=0, controls goes from T1 to T2;
ii) If x=1, generate a condition operation and go from T1 to T2.

2
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Regular/Supplementary Examinations November - 2014
SWITCHING THEORY AND LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]

Time: 3 hours Max. Marks: 70

Answer any FIVE questions
All questions carry equal marks

1. a) Convert the following:

i) (F3A7C2)16 to Binary and Octal
ii) (4310)5 to Decimal
iii) (1938.257)10 to Hexadecimal
b) Perform the following operations without converting to decimal and using 2's
complement representation
i) (7568)8 - (8567)8
ii) (11110110)2 - (01111110)2

2. a) Implement the following logical expression using AND-OR-INVERTER gates and also
using only NOR gates. A + BC'(D' + BE').
b) Prove the following using Boolean algebra:
i) y'z' + w'x'z' + w'xyz' + wyz' = z'
ii) ABC + A'B'C + A'BC +ABC' + A'B'C' = A'B' + B(A + C).

3. Implement the following logical expression using only universal gates of NAND and NOR
i) ABC + AB'C +A'BC + A'B'C
ii) f(A,B,C,D) = m (0, 2,3,6,8,9,14,15).

4. a) What are the hazards in an digital system and explain in detail about static, dynamic
and essential hazards
b) Implement the following functions using a multiplexer
Y = C'B'A' + C'BA' + C'BA + CB'A + CBA.

5. a) Compare PROM, PLA and PAL.

b) Realize the functions given using a PAL
w(A,B,C,D) = m (1,2,5,7,8,10,12,13) and x(A,B,C,D) = m (0,2,6,8,9,14)

6. a) Design a four bit binary synchronous counter with D-flipflops.

b) Derive the characteristic equation of T-flipflop.

7. a) Design an overlapping sequence detector for detecting the sequence of 110110.

b) Explain the capabilities and limitations of finite state machines.

8. a) How do you indicate Moore outputs and mealy outputs in an ASM block?
b) Draw the ASM chart for binary multiplier and explain with an example.

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Supplementary Examinations June - 2013
SWITCHING THEORY & LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
1. a) Convert (ABC)16 = ( )2 = ( )8
b) Find the 2's compliment representation of -15.
c) Find the 10's compliment of (935)11
d) What is the use of hamming code? Derive the hamming code for the message 1001.

2. a) Simplify the following Boolean function to a minimum number of literals.

i) F ( A, B, C ) = ABC + A BC + A BC + ABC + A BC
ii) F ( A, B, C ) = (1,4,5,6,7)
iii) F (A, B, C) = M (3,5,7)
b) Implement F ( x, y , z ) = (1,3,6,7) using NAND gates only.
c) Obtain the Dual of the following Boolean expressions. AB'C+AB'D+A'B'

3. a) Simplify the Boolean function 'F' using don't care conditions 'd' in (i) SOP form (ii) POS
form F=A'B'D'+A'CD+A'BC, d=A'BC'D+ACD+AB'D'
b) Given F(A,B,C,D,E) = (0,2,4,6,9,11,13,15,17,21,25,27,29,31). Obtain the simplified SOP
form using k-map method.

4. a) Draw and explain the operation of an 2-bit comparator.

b) Realize the following using MUX. F(P,Q,R,S) = m (0,1,3,4,8,9,15)

5. Realize the following logical functions using an PLA and also the architecture of the PLA used
i) F1(x,y,z) = m(0,1,2,4,6) and F2(x,y,z) = m(0,2,6,7)
ii) F1(x,y,z) = m(0,1,3,5) and F2(x,y,z) = m(1,3,5,7).

6. a) Convert SR Flip-Flop to JK Flip-Flop.

b) Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D Flip-Flops.

7. a) Discuss about capabilities and limitations of finite state machine.

b) A sequential circuit has two JK flip-flops A and B and one input x. The circuit is described
by the following flip-flop input equations :
JA = x KA = B'
JB = x KB = A
i) Derive the state equation A(t+1) and B(t+1) by substituting the input equations for the
J and K variables.
ii) Draw the state diagram of the circuit

8. a) Explain how the ASM chart differs from a conventional flow chart and also explain the
advantages of using an ASM chart over conventional flow chart.
b) Design a Mealy type serial adder using an FSM.

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Supplementary Examinations May - 2012
SWITCHING THEORY & LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering, Electronics and Control
Engineering ]
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks

1. a) Convert the following numbers.

i) (26153.7406)8 to binary
ii) Convert (2AC5.D) 16 to binary and then to octal.
iii) (1032.2)4 to decimal
b) i) Convert gray code 101011 into its binary equivalent.
ii) Use 2's complement to perform M - N with the given number M=1010100 N=1000100

2. a) Implement the following logical expression using AND-OR-INVERTER gates and also
using only NOR gates. A + BC'(D' + BE')
b) Prove the following using Boolean algebra
i) y'z' + w'x'z' + w'xyz' + wyz' = z'
ii) ABC + A'B'C + A'BC +ABC' + A'B'C' = A'B' + B(A + C).

3. Simplify the following expressions using K-Map

i) F = A'B'C'D + AB'C'D + A'B'CD + ABCD' + AB'CD' +A'B'C'D
ii) F (A,B,C,D) = m (5,6,7,12,13) + d(4,9,14,15).

4. a) Implement a Full adder with a decoder and two OR-Gates

b) Design BCD to Gray code converter and realize using logic gates.

5. a) Design a combinational using a PROM . The circuits accept 3 bit binary number and generate
its equitant Excess-3 code.
b) Derive the PLA programming table for the combinational circuit that squares a 3 bit number.

6. a) Convert D Flip-Flop into T Flip-Flop?

b) Design a MOD8 synchronous counter using T Flip-Flops?

7. For the given minimal state table:

a) Give proper assignment.
b) And design the circuit using D Flip-Flops.
Next state, output
PS
X=0 X=1 X=0 X=1(Z)
q1 q2 q1 0 0
q2 q3 q1 0 0
q3 q4 q5 0 0
q4 q4 q1 0 0
q5 q2 q1 1 0

8. a) Explain the features of ASM chart?

b) With an example, explain about sequential binary multiplier?

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Regular/Supplementary Examinations November - 2012
SWITCHING THEORY & LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering,
Electronics and Control Engineering ]
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks

1. a) What do you mean by self complementary code? Give examples.

b) Express decimal number 8620 in i) BCD ii) Excess-3 iii) 2421 code.
c) Show that the dual of EX-OR gate is equal to its complement.
d) Explain about error detecting and correcting codes.

2. a) Obtain the Dual of the following Boolean expressions

i) A'B'C+ABC'+A'B'C'D
ii) AB+ABC'
b) For the given Boolean function F=x y' z + x' y' z +w' x y + w x' y + w x y
i) Simplify the function to minimal literals using Boolean algebra.
ii) Draw the logic diagram
c) Simplify the function to minimal literals using Boolean algebra.
F=(BC'+ A'D)(AB'+CD')

3. a) Simplify the Boolean function using the tabulation method.

F (A, B, C, D) = m (0, 1, 2, 8, 10, 11, 14, 15)
b) Simplify the Boolean function using K-map F(W,X,Y,Z) = (1,2,4,5,7,8,10,11,13,14)

4. a) Draw the truth tables of half subtractor and full subtractor. Implement these using only
NAND gates.
b) Design a combinational circuit that accepts a 3 bit number and generates an output binary
number equal to the square of the input number.

5. a) Implement the following three Boolean functions with a PLA:

F1(A,B,C)=(0,1,2,4);
F2(A,B,C)= (0,5,6,7);
F3=(0,3,5,7)
b) Explain about programmable array logic (PAL).

6. a) What is race-around problem in JK Flip-flop? Explain how it is eliminated in Master

slave JK Flip Flop.
b) Design Mod-10 Counter using T Flip-Flops.

7. a) Design an overlapping sequence detector for detecting the sequence of 110110.

b) Explain the capabilities and limitations of finite state machines.

8. a) Draw and explain the ASM chart for designing a binary multiplier.
b) Explain the procedure of state minimization using merger graph and merger table.

1
CODE No.:10BT40404

SREE VIDYANIKETHAN ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to JNTUA, Anantapur)
II B.Tech I Semester (SVEC10) Regular Examinations November - 2011
SWITCHING THEORY & LOGIC DESIGN
[ Electrical and Electronics Engineering, Electronics and Instrumentation Engineering, Electronics and Control
Engineering ]
Time: 3 hours Max Marks: 70
Answer any FIVE questions
All questions carry equal marks
1. a) Convert the following numbers
i) (41.6875)10 to binary
ii) (1001001.011)2 to decimal
iii) Find the 9's Complement of number (25.639)10
b) A receiver with even parity Hamming code is received the data as 1110110.
Determine the correct code.
c) Subtract 111001 from 101011 using 2's complement.

2. Simplify the following Boolean expressions using Boolean algebra:

i) AB + AB'C(B'C' + C) + (AC)'
ii) A'BC' + A'BC + AB'C' + ABC
iii) ABC'D' +ABC'D + ABCD' +ABCD
iv) AB + ABC' + A'BC +ABC
v) ABCD + ABCD' +A'BCD +A'BCD'

3. a) Simplify the Boolean function using K-map

F (A.B, C, D) = A'B'C'+ B'CD'+ A'BCD'+AB'C'
b) Simplify the Boolean function using the tabulation method.
F (A.B, C, D) = m (0, 1, 2, 8, 10, 11, 14, 15)

4. a) Given F(A,B,C,D)=BC+ABD'+A'C'D. Implement using 8x1 multiplexer?

b) Design a 2-bit magnitude comparator circuit?

5. Draw the internal construction of PLA having 3 inputs, 3 product terms and 2 output and realize the
following functions using it. F1 = m (0,1,3,5) and F2 = m (0,3,5,7).

6. a) Convert SR Flip-Flop to JK Flip-Flop.

b) Design a counter with the following repeated binary sequence: 0,1,2,4,6. Use D Flip-Flops.

7. a) With an example explain the simplification of incompletely specified machines?

b) Explain merger chart methods?

8. a) Show the eight exit paths in an ASM block emanating from the decision boxes that check
the eight possible binary values of three control variables x,y and z ?
b) Explain the features of ASM charts?