Code No: R05220403 Set No.

1
II B.Tech II Semester Regular Examinations, Apr/May 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electronics & Communication Engineering and Electronics &
Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. Convert the following to Decimal and then to Octal.

(a) 123416
(b) 12EF16
(c) 101100112
(d) 100011112
(e) 35210
(f) 99910 [3+3+3+3+2+2]

2. (a) Simplify the following Boolean expressions to minimum no. of literals. [8]
i. ABC+A’B+ABC’
ii. (BC’+A’D)(AB’+CD’)
iii. x’yz+xz
iv. xy+x(wz+wz’)
(b) Obtain the Dual of the following Boolean expressions. [8]
i. AB+A(B+C)+B’(B+D)
ii. A+B+A‘B’C
iii. A’B+A’BC’+A’BCD+A’BC’D’E
iv. ABEF+ABE’F’+A’B’EF

3. (a) Reduce the following function

Q using K- map and implement it in AOI logic as
well as NOR logic F= M (0, 1, 2, 3, 4, 7) [10]
(b) What do you mean by K-map? Name its advantages and disadvantages [6]

4. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five
NAND gates and the EXCLUSIVE ?OR circuit made by four NAND gates as shown
in figure 4. [16]

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Code No: R05220403 Set No. 1

Figure 4
5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1

6. (a) Compare synchronous & Asynchronous circuits

(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

7. (a) Determine the equivalence classes for the given state - table.
(b) Obtain final transition table. [8+8]
Present state q v Next state q v+1 ,x2 Output z v
x=0 x=1 x=2 x=3 x=0 x=1 x=2 x=3
q0 q4 q2 q1 q4 1 0 1 1
q1 q2 q5 q4 q1 0 1 1 0
q2 q1 q0 q3 q5 1 0 1 1
q3 q6 q5 q4 q1 0 1 1 0
q4 q2 q5 q3 q4 0 1 1 0
q5 q2 q5 q3 q7 1 1 0 0
q6 q3 q0 q1 q5 1 0 1 1
q7 q1 q2 q4 q5 1 0 1 1

8. (a) For the given ASM chart obtain its equivalent state diagram 8.
(b) Design the circuit using mulitiplexes. [8+8]

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Code No: R05220403 Set No. 1

Figure 8

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Code No: R05220403 Set No. 2
II B.Tech II Semester Regular Examinations, Apr/May 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electronics & Communication Engineering and Electronics &
Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Decimal and then to Binary.

(a) 101116
(b) ABCD16
(c) 72348
(d) 77668
(e) 12810
(f) 72010 . [3+3+3+3+2+2]

2. (a) Express the following functions in sum of minterms and product of maxterms.
[8]
i. (xy+z) (y+xz)
ii. B’D+A’D+BD
(b) Obtain the complement of the following Boolean expressions. [8]
i. AB’C+AB’D+A’B’
ii. A’B’C+ABC?+A’B’C’D
iii. ABCD+ABC’D’+A’B’CD
iv. AB+ABC’

3. (a) For the truth table given below , find the minimal expression for the out put
(Y) using K-map [8+8]

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Code No: R05220403 Set No. 2
Inputs Output(Y)
A B C D
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
(b) Expand A + B C̄ + AB D̄ + ABCD to minterms and maxterms.

4. (a) Design a combinational logic to subtract one bit from the other. Draw the
logic diagram using NAND and NOR gates.
(b) Explain the working of a serial adder. [12+4]

5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1

6. (a) Compare synchronous & Asynchronous circuits

(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.

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Code No: R05220403 Set No. 2
(a) Obtain State - Diagram.
(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]

8. For the ASM chart given 8:

Figure 8
(a) Draw the state diagram.
(b) Design the control unit using D flip-flops and a decoder. [8+8]

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Code No: R05220403 Set No. 3
II B.Tech II Semester Regular Examinations, Apr/May 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electronics & Communication Engineering and Electronics &
Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Decimal and then to Binary.

(a) 231116
(b) A44D16
(c) 74448
(d) 76678
(e) 15810
(f) 72910 [3+3+3+3+2+2]
2. (a) Simplify the following Boolean expressions. [8]
i. A’C’+ABC+AC’ to three literals
ii. (x’y’+z)’+z+xy+wz to three literals
iii. A’B(D’+C’D)+B(A+A’CD) to one literal
iv. (A’+C)(A’+C’)(A+B+C’D) to four literals
(b) Obtain the complement of the following Boolean expressions. [8]
i. B’C’D+(B+C+D)’+B’C’D’E
ii. AB+(AC)’+(AB+C)
iii. A’B’C’+A?BC’+AB’C’+ABC’
iv. AB+(AC)’+AB’C
3. (a) What is a cell of a K-map? What is meant by pair, a quad, and an octet of a
map and how many variables are eliminated? [8]
(b) Reduce thePfollowing function using K- map and implement it using NAND
logic. F= m(0, 2, 3, 4, 5, 6, ) [8]
4. (a) Implement the following multiple output combinational logic using a 4 line to
16 line Decoder.
Y1 = ĀB̄ C̄ D̄ + ĀB̄CD + ĀB̄C D̄ + ĀBC D̄ + AB̄C D̄ + AB̄CD
Y2 = ĀB̄ C̄D + ĀB C̄ D̄ + ĀB C̄D + AB C̄D
Y3 = ĀBCD + ABC D̄ + ABCD.
(b) Explain the terms Multiplexing and Demultiplexing. [10+6]

5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.

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Code No: R05220403 Set No. 3
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1

6. (a) Design a sequence detector which detects 110010 Implement the sequence
detector by using D - type flipflops
(b) Classify the required circuits into synchronous, asynchronous, clockmode, pulse
mode with suitable examples. [8+8]

7. (a) Determine the equivalence classes for the given state - table.
(b) Obtain final transition table. [8+8]
2
Present state q v
Next state q ,x
v+1
Output z v

x=0 x=1 x=2 x=3 x=0 x=1 x=2 x=3

q0 q4 q2 q1 q4 1 0 1 1
q1 q2 q5 q4 q1 0 1 1 0
q2 q1 q0 q3 q5 1 0 1 1
q3 q6 q5 q4 q1 0 1 1 0
q4 q2 q5 q3 q4 0 1 1 0
q5 q2 q5 q3 q7 1 1 0 0
q6 q3 q0 q1 q5 1 0 1 1
q7 q1 q2 q4 q5 1 0 1 1

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

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Code No: R05220403 Set No. 4
II B.Tech II Semester Regular Examinations, Apr/May 2008
SWITCHING THEORY AND LOGIC DESIGN
( Common to Electronics & Communication Engineering and Electronics &
Telematics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Decimal and then to Octal.

(a) 423416
(b) 125F16
(c) 100100112
(d) 101111112
(e) 39210
(f) 77910 [3+3+3+3+2+2]

2. (a) For the given Boolean function F=xy’z+x’y’z+w’xy+wx’y+wxy [8]

i. Draw the logic diagram
ii. Simplify the function to minimal literals using Boolean algebra.
(b) Obtain the Dual of the following Boolean expressions. [8]
i. AB’C+AB’D+A’B’
ii. A’B’C+ABC’+A’B’C’D
iii. ABCD+ABC’D’+A’B’CD
iv. AB+ABC’

3. (a) What do you mean by don?t care combinations? [4]

(b) What you mean by min terms and max terms of Boolean expressions. [4]
P
(c) Simplify the Boolean function using K-map F= m(0, 1, 3, 4, 5, 6, 7, 8, 9) +
d(10, 11, 12, 13, 14, 15) [8]

4. (a) A combinational circuit is defined by the following three functions F1 = x̄ȳ +

xyz̄ F2 =x̄ + y F3 =xy + x̄ȳ Design the circuit with a decoder and external
gates.
(b) List the applications of Multiplexer and Demultiplexer. [12+4]

5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.

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Code No: R05220403 Set No. 4
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.
(b) Compare synchronous & Asynchronous. [10+6]

7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.

(a) Obtain State - Diagram.

(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

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