AN1194

Recommended Usage of Microchip UNI/O

Bus-Compatible Serial EEPROMs
There are a number of conditions that could potentially
Author: Chris Parris result in nonstandard operation. The details of these
Microchip Technology Inc. conditions depend greatly on the serial protocol used.
This application note provides assistance and
guidance with the use of Microchip UNI/O bus-
INTRODUCTION compatible serial EEPROMs. These recommendations
The majority of embedded control systems require are not meant as requirements; however, their adoption
nonvolatile memory. Because of their small footprint, will lead to a more robust overall design.
byte level flexibility, low I/O pin requirement, low-power The following topics are discussed:
consumption and low cost, serial EEPROMs are a
Power Supply
popular choice for nonvolatile storage. Microchip
Technology has addressed this need by offering a full Checking for Acknowledge
line of serial EEPROMs covering industry-standard Write Protection Features
serial communication protocols for the UNI/O bus, Write-In-Process (WIP) Polling
two-wire (I2C), three-wire (Microwire), and SPI Increasing Data Throughput
communication. Serial EEPROM devices are available Bus Pull-Up Resistor
in a variety of densities, operational voltage ranges and
Device Address Polling
packaging options.
Figure 1 shows the suggested connections for using
In order to achieve a highly robust application when
Microchip UNI/O bus-compatible serial EEPROMs.
utilizing serial EEPROMs, the designer must consider
The basis for these connections will be explained in the
more than just the data sheet specifications.
sections that follow.

FIGURE 1: RECOMMENDED CONNECTIONS FOR 11XXX SERIAL EEPROM

VCC
(1)

SOT-23
2 VCC
11XXX

VSS 3 To Master
1 SCIO

Note 1: A decoupling capacitor (typically 0.1 F) should be used on VCC.

2008 Microchip Technology Inc. DS01194B-page 1

AN1194
POWER SUPPLY CHECKING FOR ACKNOWLEDGE
Microchip serial EEPROMs feature a high amount of One of the benefits of the UNI/O bus protocol is the
protection from unintentional writes and data corruption Acknowledge sequence performed after every byte
while power is within normal operating levels. But transmitted on the bus. This sequence allows both the
certain considerations should be made regarding master and slave to detect each byte whether or not the
power-up and power-down conditions to ensure the other device is still synchronized. With the exception of
same level of protection during those times when the start header, slave devices will always transmit a
power is not within normal operating levels. Slave Acknowledgment (SAK) after every byte if no
As shown in Figure 1, a decoupling capacitor (typically error has occurred. This means that if the master ever
0.1 F) should be used to help filter out small ripples on detects a NoSAK, then an error has occurred. In this
VCC. situation, the master is required to perform a standby
pulse before initiating a new command.
Power-Up A NoSAK will occur for the following events:
Following the start header
On power-up, VCC should always begin at 0V and rise
straight to its normal operating level to ensure a proper Following the device address, if no slave on the
Power-on Reset (POR). VCC should not linger at an bus matches the transmitted address
ambiguous level (i.e., below the minimum operating Following the command byte, if the command is
voltage). invalid, including read, Current Address Read
(CRRD), write, Write Status Register (WRSR),
As further protection during power-up, once VCC has
Set All (SETAL) and Erase All (ERAL) during a
reached its normal operating level, Microchip UNI/O
write cycle
bus-compatible serial EEPROMs will remain in POR
until a low-to-high transition is detected on SCIO. This If the slave becomes out of sync. with the master
transition must precede the standby pulse that is If a command is terminated prematurely by using
required before any communication can begin. a No Master Acknowledgment (NoMAK), with the
exception of immediately after the device address
Brown-Out Conditions
For added protection, Microchip serial EEPROMs
feature a Brown-out Reset circuit. However, if VCC
happens to fall below the minimum operating voltage
for the serial EEPROM, it is recommended that VCC be
brought down fully to 0V before returning to normal
operating level. This will help ensure that the device is
reset properly.
Furthermore, if the microcontroller features a Brown-
out Reset with a threshold higher than that of the serial
EEPROM, bringing VCC down to 0V will allow both
devices to be reset together. Otherwise, the microcon-
troller may reset during communication while the
EEPROM keeps its current state. In this case, a
software Reset sequence would be required before
beginning further communication.

Power Failure During a Write Cycle

During a write cycle, VCC must remain above the
minimum operating voltage for the entire duration of the
cycle (typically 5-10 ms max. for most devices). If VCC
falls below this minimum voltage at any point for any
length of time, data integrity cannot be ensured. It will
result in marginally programmed data that may or may
not be correct. Furthermore, because the EEPROM
cells were not able to be fully programmed, the device
will have shorter data retention time than specified in
the data sheet.

DS01194B-page 2 2008 Microchip Technology Inc.

 AN1194
WRITE PROTECTION FEATURES Note that for the WRITE, SETAL, ERAL, WRSR, and
WRDI instructions, the WEL is only reset if the instruc-
To help avoid unintended writes, Microchip UNI/O bus- tion is executed successfully. This means that if, for
compatible serial EEPROMs feature a number of write some reason, the instruction is not valid, the WEL will
protection options. not be reset. For example, if a write is attempted in an
area of the array protected by the Block Protect (BP)
Write Enable and Disable bits, then the instruction will not succeed, and the WEL
will remain set.
Microchip UNI/O bus serial EEPROMs feature a Write
Enable Latch (WEL) as bit 1 of the STATUS register. For WRITE, WRSR, SETAL, and ERAL instructions, the
This latch is used to allow write operations to occur to WEL is cleared at the end of the write cycle.
the array or the STATUS register. When set to a 1, It is highly recommended that the WEL only be set
writes are enabled. When set to a 0, writes are immediately before initiating an array or STATUS
blocked. The WEL can only be set by issuing a valid register write operation in order to minimize the chance
Write Enable (WREN) instruction, but can be reset upon of an undesired write operation.
a number of conditions:
Power-up Block Protection
WRDI instruction successfully executed The block protection feature on UNI/O bus-compatible
WRSR instruction successfully executed serial EEPROMs allows selective blocks of the array to
WRITE instruction successfully executed be protected from write operations. Block protection is
SETAL instruction successfully executed controlled through the BP0 and BP1 bits (bits 3 and 4,
ERAL instruction successfully executed respectively) in the STATUS register. This offers four
different options for protection, as shown in Table 1.
It is recommended that this feature be used in order to
protect crucial data in the array.

TABLE 1: ARRAY PROTECTION

BP1 BP0 Address Ranges Write-Protected Address Ranges Unprotected
0 0 None All
0 1 Upper 1/4 Lower 3/4
1 0 Upper 1/2 Lower 1/2
1 1 All None

2008 Microchip Technology Inc. DS01194B-page 3

AN1194
WIP POLLING FIGURE 2: WIP POLLING FLOW
Write operations on serial EEPROMs require that a
write cycle time be observed after initiating the write,
allowing the device time to store the data. During this
Perform
time, normal device operation is disabled, and any
WRITE Instruction
attempts by the master to access the memory array on
the device will be ignored. Therefore, it is important that
the master wait for the write cycle to end before
Send NoMAK
attempting to access the EEPROM again. to Initiate
Each device has a specified worst-case write cycle Write Cycle
time, typically listed as TWC. A simple method for
ensuring that the write cycle time is observed is to per-
form a delay for the amount of time specified before Issue RDSR
accessing the EEPROM again. However, it is not Instruction
uncommon for a device to complete a write cycle in
less than the maximum specified time. As such, using
the previously shown delay method results in a period Read Status
of time in which the EEPROM has finished writing, but Register Value
the master is still waiting.
In order to eliminate this extra period of time, and there-
fore operate more efficiently, it is highly recommended Is Write NO
to take advantage of the WIP polling feature. Complete
(WIP = 0)?
During both an array write and a STATUS register write,
the STATUS register in Microchips UNI/O bus- YES
compatible serial EEPROMs can still be read. This
Next
allows the user to check the state of the WIP bit. This is Operation
a read-only bit, set only while a write operation is in
progress. Once the operation completes, the WIP (and
the WEL) are cleared. Therefore, the STATUS register
can continue to be read in order to monitor the value of
the WIP bit to determine when the write cycle
completes.

WIP Polling Procedure

Once the NoMAK and SAK bits have been transmitted
at the end of a WRITE, WRSR, SETAL, or ERAL instruc-
tion, the device initiates the internally timed write cycle,
and WIP polling can begin immediately. This involves
performing a Read Status Register (RDSR) instruction
and checking the value read for the WIP bit. If it is high,
the device is still writing, and the master should send a
MAK bit to request the STATUS register value again. If
the WIP bit is low, the write cycle is complete, and the
master can terminate the command with a NoMAK and
proceed with the next instruction. See Figure 2 for
details.

DS01194B-page 4 2008 Microchip Technology Inc.

 AN1194
INCREASING DATA THROUGHPUT SAK, the standby pulse is not required to begin a new
command to that device. Instead, only the start header
Setup Time (TSS) must be observed. If, however, an
Standby Pulse vs. Start Header Setup
error occurs and a SAK is not received, or if a device
Time with a different device address is being selected, a
Before initiating communication to a device not previ- standby pulse must be generated.
ously selected, a standby pulse (TSTBY) must be Refer to Figure 3 for examples of when to use TSTBY
observed before beginning the start header. Once a and when to use TSS.
command to a device has been completed success-
fully, as indicated by the combination of a NoMAK and

FIGURE 3: STANDBY PULSE AND START HEADER SETUP TIME USAGE

SAK Received SAK Received SAK Not Received

POR After NoMAK After NoMAK After NoMAK

Command to Command to Command to

TSTBY Device Address 0xA0 TSS Device Address 0xA0 TSTBY Device Address 0xA1 TSTBY

Same Device Different Devices

Selected Both Selected Each
Commands Command

Set All and Erase All whereas the column Address Pointer selects which
byte from the chosen page is accessed first. Upon
When it is desired to set the entire EEPROM array to transmission of each data byte, the column Address
either 0xFF or 0x00, the simplest and fastest way is to Pointer is automatically incremented. However, during
use the SETAL or ERAL instructions. Both of these a write operation the page Address Pointer is not incre-
instructions require an extended write cycle (10 ms vs. mented, which means that attempting to cross a page
5 ms for a standard write), but are still considerably boundary during a page write operation will result in the
faster than performing the operation using byte or page data being looped back to the beginning of the page.
writes.
Note that physical page boundaries start at addresses
Note that the entire array must be unprotected for writ- that are multiples of the page size. For example, the
ing by clearing both BP1 and BP0 and setting the WEL 11XX160 features a 16-byte page size, which means
in order for either instruction to execute. that physical pages on the device begin at addresses
0x0000, 0x0010, 0x0020 and so on.
Page Writes
All Microchip UNI/O bus-compatible serial EEPROMs
feature a page buffer for use during write operations.
This allows the user to write any number of bytes from
one to the maximum page size in a single operation.
This can provide for a significant decrease in the total
write time when writing a large number of bytes.
Page write operations are limited to writing within a
single physical page, regardless of the number of bytes
actually being written. This is because the memory
array is physically stored as a two-dimensional array,
as shown in Figure 4. When the word address is given
at the beginning of a write operation, both the row and
column Address Pointers are set. The row Address
Pointer selects which row, or page, is accessed,

2008 Microchip Technology Inc. DS01194B-page 5

AN1194
FIGURE 4: PAGE BUFFER BLOCK DIAGRAM
Column
Address
Pointer

Byte 0 Byte 1 Byte 2 Byte 3 Byte n-3 Byte n-2 Byte n-1 Byte n Page Buffer

Row
Address
Pointer Memory Array

Note: n is equal to the page size - 1

Page Write Procedure Write Time Comparisons

After enabling write operations by issuing a WREN In order to accurately calculate the full period of time
command, the beginning of the WRITE instruction required to write a particular amount of data to a device,
command, word address, and the first data byte are two things must be considered:
transmitted to the device in the same way as in a byte Load time is the amount of time needed to com-
write operation. But instead of sending a NoMAK to end plete all bus operations. This includes issuing the
the operation, the master sends a MAK and continues necessary WREN instruction, as well as transmit-
transmitting additional data bytes, which are tempo- ting the start header, device address, WRITE
rarily stored in the on-chip page buffer, up to the instruction, word address, and data bytes. This
maximum page size of the device (with care being amount of time is dependent on the bus clock
taken not to wrap around the page). As with the byte speed and the number of data bytes to be written.
write operation, once the master sends a NoMAK, an The TSS time period is used before both WREN and
internal write cycle will begin during which all bytes WRITE instructions in place of the standby pulse.
stored in the page buffer will be written.
Write cycle time is the time during which the
device is executing its internal write cycle. As
described in the previous section (WIP
Polling), there is a specified maximum write
cycle time for each device. However, the internal
write cycle typically completes in less time than
specified. As such, both worst-case (5 ms) and
typical (3.2 ms at TAMB = 25C) calculations are
provided in Table 2.

DS01194B-page 6 2008 Microchip Technology Inc.

 AN1194
The following equations were used to calculate the
values for Table 2:

EQUATION 1: WRITE TIME EQUATIONS

10 ( 8 + # data bytes )
T LOAD = ----------------------------------------------------- + ( 2 ( T SS + T HDR ) )
F CLK

T TOTAL = ( T LOAD + T WC ) # write operations

TABLE 2: WRITE TIME COMPARISONS

Page Size # of Bytes Write Clock Speed Load Time Per Total Time (ms) Total Time (ms)
Device
(bytes) to Write Mode(1) (kHz) Operation (ms) Worst-Case(2) Typical(3)
11LC010 16 1 Byte 10 9.03 14.03 12.23
16 Byte 10 9.03 224.48 195.68
16 Page 10 24.03 29.03 27.23
1 Byte 100 0.93 5.93 4.13
16 Byte 100 0.93 94.88 66.08
16 Page 100 2.43 7.43 5.63
Note 1: Byte Write mode signifies that only 1 byte is written during a single write operation.
Page Write mode signifies that a full page is written during a single write operation.
2: Worst-case calculations assume a 5 ms timed delay is used.
3: Typical calculations assume WIP polling is used, with typical TWC = 3.2 ms, TAMB = 25 C.

From these examples, it is clear that both page writes Supply Voltage (VCC)
and WIP polling can provide significant time savings.
Writing 16 bytes to the 11LC160 via byte writes at Supply voltage limits the minimum RP value due to
100 kHz requires roughly 95 ms worst-case. Switching maximum low-level output voltage (VOL) specifications.
to WIP polling brings that down to roughly 66 ms Consequently, for a given VCC level, a smaller pull-up
(assuming typical conditions), nearly a 31% decrease. resistor value will result in a higher low-level output
Changing to page writes further lowers the time to voltage. For Microchip UNI/O bus-compatible devices,
5.63 ms, an additional decrease of over 91%. Overall, the VOL specification is a maximum of 0.4V at 300 A
the two techniques provide a combined time savings of for Vcc = 5.5V (200 A for VCC = 2.5V). In other words,
over 89 ms, increasing the total data throughput nearly if there is a voltage drop across RP of VCC -0.4V, it can-
17 times over. not be sourcing more than 200 A to 300 A, depend-
ing on VCC. Applying Ohms Law yields Equation 2 for
VCC > 2.5V, and Equation 3 for VCC 2.5V.
BUS PULL-UP RESISTOR
In order to ensure bus idle during times when no device EQUATION 2: MINIMUM RP VALUE
is driving the bus, a pull-up resistor is recommended on VCC > 2.5V
the SCIO bus. However, two limiting factors must be
considered when selecting pull-up resistor (RP) values: VCC V OL V CC 0.4V
R PMIN = --------------------------- = -----------------------------
Supply voltage (VCC) I OL 300 A
Total High-Level Input Current (IIH)
Note that the pull-up resistor is meant only to provide a
DC level during times when no device is driving the EQUATION 3: MINIMUM RP VALUE
bus, and so slow slew rates due to a large bus VCC 2.5V
capacitance should not adversely affect system
performance. VCC V OL V CC 0.4V
R PMIN = --------------------------- = -----------------------------
I OL 200 A

2008 Microchip Technology Inc. DS01194B-page 7

AN1194
Total High-Level Input Current (IIH) Example Resistor Value Calculation
The total high-level input current for a line is the total Here is an example of how to use the previous equa-
amount of current that will be flowing through the pull- tions to select the appropriate pull-up resistor value.
up resistor when there are no contentions and the line The following parameters will be used:
is allowed to be pulled up by the resistor. This current
consists of the sum of the input leakage currents for all TABLE 3: EXAMPLE PARAMETERS
devices connected to the bus, as well as any other
current being sunk by the devices through the input pin. Parameter Value Units

Because some current will exist through the pull-up VCC 5.0 V
1
resistor even when no device is actively driving the bus, VIH 3.5 V
the effective voltage seen at the SCIO pin will be lower IIH 102 A
than VCC due to the voltage drop across the resistor.
Note 1: VIH derived from 0.7*VCC spec.
This voltage drop must be small enough that the volt-
age at the pin will still be considered a high by the 2: IIH used as an example. Each system will
device. That is, the voltage at the pin must be higher vary based on the devices connected to
than VIH. Applying Ohms Law once again results in the bus.
Equation 4.
By applying Equation 2 and Equation 3, the following
resistor value limits were calculated:
EQUATION 4: MAX. RP DUE TO CURRENT
TABLE 4: RESISTOR VALUE LIMITS
V CC ( V IH )
R PMAX = ------------------------------- Limit Value Limiting Factor
I IH
RPMIN 15.33 k Supply Voltage
RPMAX 150 k Input Current

Although a 15.33 k resistor would be weak enough at

the specified VCC level to ensure the output reaches
VOL, choosing the smallest possible value would be a
waste of power. Selecting the largest possible value,
150 k in this example, leaves only the 0.05*VCC
margin (specified by VHYS) for any noise that may
occur. Therefore, a resistor value between the
minimum and maximum should be selected based on
power consumption requirements and noise
expectations.

DS01194B-page 8 2008 Microchip Technology Inc.

 AN1194
DEVICE ADDRESS POLLING In order to perform device address polling, the master
generates a standby pulse and start header and trans-
UNI/O bus devices will respond with a SAK if either a mits the desired device address followed by a NoMAK.
MAK or NoMAK is received following the device The master then checks to see whether or not a corre-
address, as long as the address is valid. In the case of sponding slave transmits a SAK. If a SAK is received,
a NoMAK, the slave device will return to Standby mode then a slave exists with the specified device address.
immediately following the transmission of the SAK. Note that a standby pulse must be generated before
This feature allows the master to perform an Address every command, because a different device is being
Polling sequence in order to determine what devices addressed during each sequence.
are connected to the bus. Such a sequence is typically Figure 5 shows an example of polling for two devices.
used in conjunction with a list of expected device In this example, the first device exists on the bus, and
addresses to allow for added flexibility in system the second device does not exist.
design.

FIGURE 5: DEVICE ADDRESS POLLING EXAMPLE

NoMAK
NoSAK
MAK

SAK
Standby Pulse Start Header Device Address 1

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0

NoMAK
NoSAK
NoSAK
MAK
Standby Pulse Start Header Device Address 2

SCIO
0 1 0 1 0 1 0 1 1 0 1 0 0 0 0 1

SUMMARY
This application note illustrates recommended
techniques for increasing design robustness when
using Microchip UNI/O bus-compatible serial
EEPROMs. These recommendations fall directly in line
with how Microchip designs, manufactures, qualifies
and tests its serial EEPROMs and will allow the devices
to operate within the data sheet parameters. It is
suggested that the concepts detailed in this application
note be incorporated into any system that utilizes a
UNI/O bus-compatible serial EEPROM.

2008 Microchip Technology Inc. DS01194B-page 9

AN1194
NOTES:

DS01194B-page 10 2008 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience
The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
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2008, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Companys quality system processes and procedures
are for its PIC MCUs and dsPIC DSCs, KEELOQ code hopping
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and manufacture of development systems is ISO 9001:2000 certified.

2008 Microchip Technology Inc. DS01194B-page 11

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Tel: 86-592-2388138 Tel: 886-2-2500-6610
Fax: 408-961-6445
Fax: 86-592-2388130 Fax: 886-2-2508-0102
Toronto
China - Xian Thailand - Bangkok
Mississauga, Ontario,
Tel: 86-29-8833-7252 Tel: 66-2-694-1351
Canada
Fax: 86-29-8833-7256 Fax: 66-2-694-1350
Tel: 905-673-0699
Fax: 905-673-6509 China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049

01/02/08

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