ECEN 248

Laboratory Exercise #5

Simple Arithmetic Logic Unit

ECEN 248 Laboratory Exercise #5

1. Introduction

In this lab, you will design, implement, and test a simple 4-bit Arithmetic Logic Unit

(ALU) which will perform elementary computations such as addition, subtraction, and

bit-wise AND. To do so, you will learn about Two’s Complement Arithmetic and

multiplexers.

2. Background

2.1 Two’s Complement Arithmetic

In the previous lab, we briefly introduced addition of unsigned numbers but made no

mention of subtraction. In order to perform subtraction, we need a way to represent

negative numbers in binary. Therefore, we will introduce a binary signed number

representation and show how to use it for subtraction. Note that a binary signed number is

simply a binary number that can take on either a positive or negative value. Although

there are many ways to represent signed numbers in binary, we will only touch on one

such representation in this lab assignment, namely Two’s Complement.

First of all, how to compute two’s complement? Just invert all the bits and add 1 to it.

Assume we have a 4-bit binary number that is 0101, what is the two’s complement of it?

1. Invert all the bits: 0101 = 1010

2. Add 1 to the result: 1010 + 1 = 1011

3. Check sum: 0101 + 1011 = 10000 = 2!

Thus the two’s complement of 0101 is 1011, or we can say two’s complement of 5 is

−5. Now you may have the question: 1011 should be 11, how can it be −5?

Next, we are going to learn how to read two’s complement negative binary number. The

leftmost bit indicates the sign of number: 0 means positive and 1 means negative.
2

ECEN 248 Laboratory Exercise #5

Positive numbers remain the same but negative ones do not. Let us go over the 4-bit

binary number 1011.

1. The leftmost 4th bit is 1, which means it is negative.

2. Take two’s complement again to determine its magnitude:

1011 + 1 = 0101 = 5!"#$%&'

So 1011 is −5 in two’s complement. To verify it, 0101 + 1011 = 10000, which is 0.

Here, because we are doing 4-bit binary math, we do not care about the leftmost 5th bit,

which is also a carry out bit 1.

Last but not least, there is a small trick for you to extend the original binary number to

more bits. For positive numbers, fill the missing bits with 0s and for negative numbers,

fill the missing bits with 1s. 0101 and 1011 are extended to 6-bit numbers as below:

1. 0101!!!"# = 000101!!!"#

2. 1010!!!"# = 111010!!!"#

Up till now, we have been able to represent both positive and negative in binary.

Therefore, subtraction can be performed by negating the subtrahend and adding it to the

minuend. Figure 1 illustrates the addition of two’s complement numbers.

Overflow!
5 0101 5 0101
3 1101 3 0011

2 10010 8 1000

Figure 1. Addition of Two's Complement Numbers

3

ECEN 248 Laboratory Exercise #5

The subtraction on the left generates the result correctly but the addition on the right does

not! 1000 is −8 in two’s complement, not 8. This situation is called overflow because it

exceeds the range of two’s complement. In mathematical terms, the decimal value of a

two’s complement binary number belongs in [−2!!! , 2!!! − 1], where n is the number

of bits. Thus 4-bit two’s complement cannot represent decimal number 8, which causes

the overflow.

Because the result is wrong when overflow has occurred, it must be indicated so that the

wrong one can be discarded. For two’s complement arithmetic, overflow occurs when

both input sign bits are the same but differ from the output’s sign bit. If there is still

something unclear, please consult your text book and lecture slides.

2.2 Multiplexers

A multiplexer(MUX) is a digital circuit which routes one of its 𝑁 data inputs to the

output based on binary value log ! 𝑁 of select inputs. Figure 2 shows a 4-bit wide 2:1

MUX that is necessary for today’s design. If the select signal s is logic 0, 𝑌 = 𝐴;

otherwise 𝑌 = 𝐵.

4
A
4-bit
4
Y
4 2:1
B

s

Figure 2. 4-bit 2:1 MUX

4

ECEN 248 Laboratory Exercise #5

In this lab, we are using component SN74CT257N as our chip for the MUX. Its pin-out

diagram is shown in Figure 3. The only thing needs to be noticed is that 𝐴/𝐵 is the select

signal s and 𝑂𝐸 must be connected to ground. For more information, please consult your

data sheet.

74CT257

Figure 3. 4-bit 2:1 MUX SN74CT257N

2.2 Arithmetic Logic Unit

The ALU is a component that is capable of performing various arithmetic and logical

operations based on control inputs, so it is a fundamental building block of any sort of

computational device. Simple microprocessors found in home appliances often contain

only one ALU, while the modern Central Processing Units (CPUs) and Graphics

Processing Units (GPUs) found in today’s desktops and mobile devices contain

5

ECEN 248 Laboratory Exercise #5

tremendous amount of extremely powerful ALUs. The symbol typically used to represent

an ALU is shown in Figure 4.

A
Y
B

Figure 4. ALU Symbol

𝐴 and 𝐵 represent the input buses, while 𝑌 represents the output bus. Not shown in this

simple drawing are the control and status signals, which will be expounded upon shortly.

One way to create a simple ALU is to build several computational blocks and multiplex

their output buses. The selection signals for the multiplexer then serve as the control

signals for the ALU. Today we are going to build a simple ALU by ourselves.

3. Logic Design

3.1 Adder & Subtractor Design

As we learned in the background, both addition and subtraction can be implemented by

an adder circuit with the help of two’s complement. For our ALU, these two operations

are essential. We could create a separate adder for addition and another one for

subtraction without consideration, however, we can do better by designing the unit as

seen in Figure 5. Here you can see the only difference between our design and the 4-bit

carry ripple adder are the XOR gates. Also the carry-in bit can select the function now.

6

ECEN 248 Laboratory Exercise #5

a3 b3 a2 b2 a1 b1 a0 b0

A B A B A B A B
Cout
Co FA Ci Co FA Ci Co FA Ci Co FA Ci
!Add/Sub
S S S S

s3 s2 s1 s0

Figure 5. 4-bit Addition/Subtraction Unit

Remember that subtraction is simply addition in which the B operand is complemented.

To take two’s complement of a binary number, we must invert all the binary digits and

add one to the result. When feeding the carry-in signal with “Sub” as 1, the circuit is

performing XOR between B and 1111. As we know, 1⨁𝑏 = 𝑏. Thus it is a subtraction

unit when “Sub” is logic 1. Similarly, when “Add” is logic 1 it is an addition unit.

In this lab, you do not have to build every single full adder on you own. Instead, we

provide you the component SN74HC283E as the 4-bit carry ripple adder. All you need to

do is to connect several XOR gates.

3.2 Multiplexer Design

In this part, you don’t need to design anything because we will provide you the chip

SN74CT257N with the 4-bit wide 2:1 MUX packed inside it. Reading over the

background section will help you a lot.

3.3 4-bit ALU Design

7

ECEN 248 Laboratory Exercise #5

At this point, we have acquired all pieces we need to finish our simple ALU design which

can do three operations: AND, addition and subtraction. Our last job is signal connection.

4
A 4
AND
2:1 Result
4

4
B
+/- Overflow
c1 ?
c0

Figure 6. Simple ALU Design

Figure 6 is the block design diagram of our ALU. 𝑐! is the signal that selects AND or

math function. 𝑐! is the signal that determines addition or subtraction. Note that there is a

black box in Figure 6, which is the unit to detect overflow. We will use it later.

4. Lab Procedures

For the lab procedures below, consult the datasheets of each component for the pin-outs

and electrical/timing characteristics of these circuits. If you do not remember how to wire

up the DIP switch and LEDs, read the background section of lab manual 3. Please note

that the following experiments are leading you to build an ALU, so please organize the

breadboard area in advance for your final design.

4.1 Part 1

8

ECEN 248 Laboratory Exercise #5

In the first part, bread-board and test your addition/subtraction unit. To do so, we must

utilize the 4-bit carry ripple adder component SN74HC283E. Because A and B are 4-bit

signals, DIP switch is recommended. However, you will have to use a jump wire for the

control signal. Display the output signals using LEDs.

4.2 Part 2

Test your 4-bit 2:1 MUX chip SN74CT257N using LEDs.

4.3 Part 3

a. Connect the outputs of AND units and addition/subtraction units to the inputs of

the 4-bit 2:1 MUX.

b. Connect 𝑂𝐸 of the MUX to ground.

c. Use LEDs to display the result coming from the MUX.

d. Vary the control signals 𝑐! 𝑐! by manually connecting them to power or ground.

Verify the circuit operation matches the operation table created in the pre-lab.

In the demonstration, you need to show AND, addition and subtraction function of you

ALU.

5. Lab Deliverables

5.1 Pre-lab Deliverables

Please include the following items in your pre-lab write-up.

1. Examples demonstrating how the circuit in Figure 5 adds and subtracts.

2. Truth table and minimized Boolean expression for a 1-bit wide 2:1 MUX.

3. Gate-level schematic for the final ALU design.

4. Create a table with three columns: 𝑐! , 𝑐! and OP, such that 𝑐! and 𝑐! correspond

to the ALU control signals and OP is the operation it will perform, like AND.
9

ECEN 248 Laboratory Exercise #5

5.2 Post-lab Deliverables

Please include the following items in your post-lab write-up.

1. Observe and fill in the table. Both A and B are two’s complement numbers. The

result should be a 4-bit binary number. Determine whether overflow occurs or not.

𝑐! 𝑐! Operation A B Result Overflow

0 0 0100 0110

0 1 0110 1101

1 0 0100 0110

1 0 0100 1101

1 0 1101 1001

1 1 0100 0111

1 1 0110 1001

2. Determine the maximum gate delay through your final ALU circuit assuming

each gate has a delay of 1 unit. Highlight the critical path on the gate-level

schematic.

3. Please design the overflow detecting unit in Figure 6. You can use all available

signals except the signals inside the chip package. Show your process and draw a

gate-level schematic.

10