REPORT ON SYSTEM AND INTEGRATED CIRCUIT

DESIGN
Dated 9/9/2022

Student’s Name: Lý Gia Huy

ID: 20161205
*Design a full adder 4 bit
The first overview of RTL Schematic:

The sum of two number four bits requires bit carry, thus the top module circuit must have every
one bit being summed up by each other to take the carry bit from the LSB to the MSB and give
the right answer. Because of that, an adder of 1 bit must be done as an instance to calculate the
whole circuit.
The truth table for adder 1 bit:
A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Using Karnaugh map:
For S: S = A ⨁ B ⨁ Cin
B\Cin\ B\Cin BCin BCin\
A\ 0 1 0 1
A 1 0 1 0
For Cout: Cout = AB + BCin + CinA
B\Cin\ B\Cin BCin Bcin\
A\ 0 0 1 0
A 0 1 1 1
Figure 1 The detailed RTL Schematic

Verilog coding:

Figure 2 Instance 1-bit full-adder

Figure 3 Top module full-adder 4 bit

Figure 4 Test bench (line 1 is S, line 2 is Cout, line 3 is A, line 4 is B)

From figure 3, every stimulus is correct, at the third stimulus because the output is only four bits so it
can not carry the last bit too, the correct answer is 19 but the Cout count up to 1 for that bit, the last
stimulus has Cin = 1 so the total is 11.
*Design a full subtract 4-bit using the full adder

Figure 5 RTL Schematic overview

Figure 6 Detail RTL schematic

Figure 7 Verilog Coding

The idea from the circuit above is S = A ⨁ B ⨁ Bin => S = A ⨁ ~B ⨁ Bin => the B input
change to the 2’s complements, thus the B input has to go through the NOT logic to get 1’s
complement, also change the carry input to the borrow input ( always at a high level for 2’s
complement ) then result will be exactly.

Figure 8 Test bench

Because of the 2’s complement form, some results will have an extra bit and be stored in the
borrow output.
*Design a full subtract in another way

Figure 9 RTL Schematic overview

The operation of this module is the same as the full-adder module, one different thing is the
function for Borrow output.

The truth table for full-subtract 1 bit:

A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
For D: D = A ⨁ B ⨁ Bin
B\Cin\ B\Cin BCin BCin\
A\ 0 1 0 1
A 1 0 1 0
For Bout: Bout = A\B + BBin + BinA\
B\Cin\ B\Cin BCin Bcin\
A\ 0 1 1 1
A 0 0 1 0

Figure 10 Detail RTL Schematic

Figure 11 Verilog coding top module

Figure 12 Instance for the top module

Figure 13 Test bench ( line 1 is Bout, line 2 is D, line 3 is A, line 4 is B)

*Design 74HC83

Figure 14 Block diagram

The advance of this IC is its fast carry, this is different from the adder above while the carry
output is connected in series of each instance, this IC has the carry output connected in parallel in
other to improve faster the calculations.
Figure 15 Truth table

Function connect from figure 14:

C1= NAND(NOT(A1) NAND(~C0, B1))
C2= NAND(NOT(A2) NAND(A1,B2) NAND(~C0,B2,B1))
C3= NAND(NOT(A3) NAND(A2,B3) NAND(A1,B3,B2) NAND(B1,B2,B3,~C0))
C4= NAND(NOT(A4) NAND(A3,B4) NAND(A2,B4,B3) NAND(A1,B4,B3,B2)
NAND(~C0,B4,B3,B2,B1))
S = (A~^B) ^ (~C0) ( First calculation only)
S = (A~^B) ^ C ( The rest)
Figure 16 Schematic for S[0]

Figure 17 Schematic for S[1]

Figure 18 Schematic for S[2]

Figure 19 Schematic for S[3]

Figure 20 Verilog coding

The test bench isn’t the correct answer, the stimulation of IC74HC83 is failing.
 REPORT ON SYSTEM AND INTEGRATED CIRCUIT DESIGN
DATED 16/09/2022 + 24/09/2022
Student’s name: Lý Gia Huy
ID: 20161205
1. Design a decoder circuit.
The decoder is a combinational logic circuit that has n inputs and 2n outputs. The
application of this circuit is many, for example, it is used as an address in CPU memory
location identification, mainly used in logical circuits, and data transfer. Then, it has many
different types in other to use for many different circuits.

1.1_2 to 4 decoder ( active high output).

Truth table
Input Output
A B Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0

Figure 1 Verilog coding

In fig1, the 2 to 4 decoder with high active output is definite as two inputs a,b one bit and the output is
four bit, all those inputs and output don’t declare the type for net or variance then the compiler will
define it as the net is a wire data type, used assign statement operator condition for wire y =
<condition>? < correct expression> : < wrong expression > by depend on the truth table.
Figure 2 Waveform

In fig2, the waveform is shown up as the coded Verilog in fig 1, every stimulus delay for 100ns,
compared to the truth table, and has the right behavior.

Figure 3 RTL schematic insight

Fig3 shows up the number of the logic and gate for the decoder code. The triangle symbol simply
indicates that the pin connects to one bit of a bus in the schematic. Buses are indicated by a thick line,
notice that wherever one bit of that bus only is connected the bus, goes into a triangle, and then from
the triangle, there is a thinner line going to the pin. It is not a buffer, nor it is configurable. It is not
anything physical at all, simply how ISE chose to represent places where a single bit from a bus is used.
Figure 4 Product

1.2_2 to 4 decoder ( active low output ).

Truth table
Input Output
A B Y3 Y2 Y1 Y0
0 0 1 1 1 0
0 1 1 1 0 1
1 0 1 0 1 1
1 1 0 1 1 1

Figure 5 Verilog coding

Fig3 shows 2 to 4 Decoder codes with low active output similar to the active high output, but with a
different truth table.
Figure 6 Waveform

Fig4 demonstrates the waveform for low active output is correct.

Figure 7 RTL schematic insight

The Schematic of low active output is different from the highly active, it uses and logic gate, or logic
gate, one inverse and three, the finished circuit is the same as fig4
1.3_2 to 4 decoder has high active enable input.
Truth table
Input Output
EN A B Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

Figure 8 HDL description

Using SOP ( sum of product ) from the truth table, create the function used for assigning four-bit wire
output y.

Figure 9 Waveform

Waveform goes the same value as the truth table for the impact of a, b, en input.
Figure 10 The schematic insight

The 2 to 4 Decoder with low activity enables using four logic and with three different high low inputs
from above to below.

Figure 11 Product
 1.4_2 to 4 decoder has active low enable input.
Truth table
Input Output
EN A B Y3 Y2 Y1 Y0
1 X X 1 1 1 1
0 0 0 1 1 1 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 1 1 1

Figure 12 HDL description

Use POS ( product of sum ) from the truth table, and create the function that is used for assigning four-
bit wire output y.

Figure 13 Waveform

Waveform stimulation for a coding test and the value are quite close in the truth table.
Figure 14 The schematic insight

The circuit changes the logic gate (and) three inputs to the logic gate (or) three inputs for the description
code in fig12. The finished circuit was similar to fig11.

1.5_2 to 4 decoder has a selection of active high or low output.

This circuit has a selection input to choose between the decoder with active high enable (1.4) and
the decoder with active low enable (1.3).
Figure 15 HDL description

The code provides the idea of making a selection of decoder circuit, by declaring two more ports named
sel and z, the input sel help choose which decoder operates, and the wire z is held for the value of an
active high enable decoder.

Figure 16 Test bench

The code for testing value to compare to the truth table, by giving those ports the input value then the
output will show the results in the following waveform below.
Figure 17 Waveform

In figure17, at the period 100ns to 200ns, the input sel is 0, which means it chooses active low to enable
decoder running, the en input is high then no matter how the value of a and b input, the output will be
four-bit zero. All the rest stimuli can be compared to the truth table from above.

Figure 18 The schematic insight

Fig18 view the name and the number of the logic gate for the circuit, the two pictures are the first part
y[0], and z[0] of the whole circuit, and the remaining outputs are the same.
Figure 19 Product

1.6_3 to 8 decoder in directly Verilog coding ( active low output).

Truth table
Input Output
A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0 1
0 1 0 1 1 1 1 1 0 1 1
0 1 1 1 1 1 1 0 1 1 1
1 0 0 1 1 1 0 1 1 1 1
1 0 1 1 1 0 1 1 1 1 1
1 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
Figure 20 HDL description

Using POS from the truth table again, it is the idea for decoder 3_8 directly coding, it has another input c
and the output y is come up with eight-bit.

Figure 21 Waveform

Fig21 demonstrates some impact of those inputs a, b, and c as a stimulus with the period is 100ns, the
result at the output is similar to the truth table with an active low bit.
Figure 22 The schematic insight

The circuit use OR logic gate with three input, actually it has a NOT gate to separate the exact input from
the idea in the HDL description from above, each gate will give an output from y[7] to y[0].

Figure 23 Product
1.7_3 to 8 decoder using 2 to 4 decoder ( active high output ).
Truth table
A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

Figure 24 HDL description for Instance

The decoder 2_4 is used as an instance for top module decoder 3_8 by connecting the wire statement as
the following description below.

Figure 25 HDL description for the top module

By connecting the wire type from the top module to the instance, first, declare the name of the
instance, second give it another name, and finally, sort all the ports in the top module connected to the
instance by order. The waveform would inform error if those ports have the wrong connection.
Figure 26 Waveform

Fig26 shows five stimulations for the HDL description above, then compare to the truth table, the
waveform is going correct.

Figure 27 The schematic insight

By connecting a NOT gate, divide two enable inputs from instance dec_low_en that mean when dec1
runs then dec2 stop. The schematic insight for Dec 1 and Dec 2 can be seen above.

Figure 28 Product
2. Design encoder circuits
An encoder is a device that converts information from one format or code to another. The
main purpose of the encoder is standardization, security, speed, or saving space by
shrinking size. The encoder is a combinational logic circuit and they are exactly the
opposite of the decoder. They accept 2n inputs and generate n outputs code.

2.1_4 to 2 encoder active high input

Truth table
Input Output
A3 A2 A1 A0 Y1 Y0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

Figure 29 HDL description

Using the always procedure to generate a 4 to 2 Encoder, the symbol “ @(*) “ mean simulation and
synthesis will automatically be sensitive to all signals read within the procedure, when the A input is
active, the CASE statement is declared in ALWAYS will run, also the Y output has to be a reg type in to
form in always. The benefit of using always procedure is to make coding easier.

Figure 30 Waveform
The waveform runs 100ns per period, at the first stimulus, the output came up with XX value when the
impact from the input A is four-bit zero because the four-bit zero doesn’t exist in the truth table so the
stimulation can’t recognize the result.

Figure 31 RTL schematic insight

From the RTL schematic, the circuit uses a lot of logic gates for the HDL description, it also has a latch,
which only allows the correct value to go out of the output.

Figure 32 Product
 2.2_4 to 2 encoder active high input, with active high enable.
Truth table
Input Output
EN A3 A2 A1 A0 Y1 Y0
0 X X X X X X
1 0 0 0 1 0 0
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 1 0 0 0 1 1

Figure 33 HDL description

Continue using the always procedure but with the IF statement, the input now has active-high enable,
then check the enable input first and the rest is the description as the following truth table above.

Figure 34 Waveform

From the beginning, the low active enable it goes with a low bit, so the output is X ( unknown or
uninitialized ), point at the waveform goes from 200ns to 300ns the output still stays X because the
value from A input is not in the truth table, just only the remaining stimulus is giving the wanted value
for output.

Figure 35 The schematic insight

The integration of logic gates is denser than the HDL description above.

Figure 36 Product
 2.3_8_3 encoder directly coding, low active enable.
Truth table
Input Output
EN A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0
0 X X X X X X X X X X X
1 0 0 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0 1
1 0 0 0 0 0 1 0 0 0 1 0
1 0 0 0 0 1 0 0 0 0 1 1
1 0 0 0 1 0 0 0 0 1 0 0
1 0 0 1 0 0 0 0 0 1 0 1
1 0 1 0 0 0 0 0 0 1 1 0
1 1 0 0 0 0 0 0 0 1 1 1

Figure 37 HDL description

Generate an 8 to 3 Encoder by using the IF statement again, including eight bits input A, one-bit input
EN, and three-bit output Y.
Figure 38 Waveform

From fig38, there are eight stimuli for each 100ns period, when enable goes low level then how to
matter the input A, the output Y will get a XXX value, it also gets the same value the input A has eight
zero bit, the last 4 remaining stimuli can compare with the truth table.

Figure 39 The schematic insight

Figure 40 Product
 2.4_8_3 encoder using two 2_4 encoder.
The truth table is similar to 2.3

Figure 41 Instance

Fig41 describes Verilog coding for the 2_4 encoder by using POS for the temporary output, and
condition assign statement for wire type.

Figure 42 HDL description

Fig42 shows how to connect all ports in the top module to the instance by calling it, then using the
Karnaugh map to change the temporary four-bit output to three-bit output as the following
mathematics above.

Figure 43 Waveform
In the beginning, the input en get low level then no matter how the input is, the output will
unrecognized, when the input en active high level, the waveform will run the right behavior of fig 42.

Figure 44 RTL schematic insight

Figure 45 Product
3. Design compare circuit
Truth table
Input Output
A B A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

3.1_Compare circuit using instance.

Figure 46 Instance

In fig44, the description uses the always procedure with using the if statement to generate the behavior
as the following truth table above.
 Figure 47 Top module

In the top module, it expresses the connection between the top module’s wire and the instance’s wire in
order, also using the assign condition for selecting which instance will operate.

Figure 48 Waveform

The waveform goes right.

Figure 49 The RTL schematic insight

 Figure 50 Product

3.2_Compare circuit using full subtractor.

Figure 51 Instance

Fig49 builds a full subtractor one bit from using the Karnaugh map, generating two mathematics for
output D and Cout.
 Figure 52 Top module

To make a comparison circuit from the full subtract circuit, the Cout is the key, if the Cout is up to a
high level that means B higher than A, if Cout is low level, then start with the result of the difference, if
the result is zero that means A equal B, and the rest is A higher than B.

Figure 53 Waveform

Compare the waveform fig51 to fig46, it is completely the same.

Figure 54 The RTL schematic insight

Figure 55 Product
REPORT ON SYSTEM AND INTEGRATED CIRCUIT
DESIGN
Dated 30/09/2022
Student’s name: Lý Gia Huy
ID: 20161205
I. Frequency division circuit
1. Generate a 1Hz clock pulse circuit.

module clock1hz(
input wire clk,reset,
output wire q
);
reg[31:0] cou=0;
wire c;
always @(posedge clk,posedge reset)
begin
if(reset)
cou <= 0;
else
begin
if (c) cou <= 32'b0;
else cou <= cou + 32'b1;
end
end
assign c = (cou == 32'd25000000) ? 1'b1 : 1'b0;
assign q = c;
endmodule

HDL description to generate 1Hz pulse from 50Mhz pulse

The idea for a 1Hz clock pulse circuit from any value of the internal clock of any
circuit is math, for example, if a circuit has an internal clock is 50Mhz, then compare
its period to a 1Hz period, a 50Mhz clock has many periods but 1Hz clock is only
one, thus, a half period of 1Hz clock is a half period of 50Mhz clock that means first
25Mhz clock is active low and the rest is active high of 1Hz clock, use always
procedure combines with assign operator condition statement for the design.
Figure 1 RTL Schematic insight

Fig1 show much different logic gates connected to fabricate the 1Hz clock pulse

Figure 2 Product
 2. Generate four different clock pulse circuits.

module frequency(
input wire reset,clk,
output wire [3:0] q
);
reg [35:0] f01,f1,f10,f100;
wire c,c1,c2,c3;
always @(posedge clk,posedge reset)
begin
if(reset) begin
f01<=0; f1<=0; f10<=0; f100<=0; end
else
begin
if (c) f01 <= 32'b0;
else f01 <= f01 + 32'b1;
if (c1) f1 <= 32'b0;
else f1 <= f1 + 32'b1;
if (c2) f10 <= 32'b0;
else f10 <= f10 + 32'b1;
if (c3) f100 <= 32'b0;
else f100 <= f100 + 32'b1;
end
end
assign c = (f01 == 32'd250000000) ? 1'b1 : 1'b0;
assign c1= (f1 == 32'd25000000) ? 1'b1 : 1'b0;
assign c2= (f10 == 32'd2500000) ? 1'b1 : 1'b0;
assign c3= (f100 == 32'd250000) ? 1'b1 : 1'b0;
assign q[0] = c;
assign q[1] = c1;
assign q[2] = c2;
assign q[3] = c3;
endmodule
The description above describes four different frequency clock pulses which declare
in the code are 0.1Hz, 1Hz, 10Hz, and 100Hz, manipulate the knowledge of math to
generate these frequency clock pulses from 50Mhz clock pulses. The code has a
combination of always procedure and assigns operator condition to define its
behavior and uses non-blocking operator to prevent delay of each statement.
II. Multiplexer_4_to_1.

module mux(
input wire [3:0] clk,
input [1:0] sw,
output reg clk_out
);
always@(clk,sw)
begin
case(sw)
0: clk_out = clk[0];
1: clk_out = clk[1];
2: clk_out = clk[2];
3: clk_out = clk[3];
endcase
end
endmodule

HDL description for 4_1 multiplexer, this circuit has four inputs and one output, the
special is it has a switch input, this input can choose the value of one input to export
to the output as the CASE statement is described above.

Figure 3 Waveform

The value of SW is changed each 100ns, if SW chose 00 that means the first element
of input will be exported, if SW chose 01 then the output gets the value of the second
element, the rest are the same.
Figure 4 RTL Schematic insight

Figure 5 Product
III. Counter
1. 4_bit counter up.

module counter4bit(
input clk,reset,
output reg [3:0] q
);
always @(posedge clk, posedge reset)
begin
if(reset) q<=0;
else
q <= q+1;
end
endmodule

HDL description for the 4-bit counter, the behavior above said that the circuit will
count if it has an impact of posedge clock pulse and the reset input must be active
low, continue use non_blocking operator to prevent the delay, the circuit count up
from 0 to 15 as it four-bit output.

Figure 6 Waveform

At the first 10ns, the reset input is active high to initialize the output, after that it will
count at every posedge clock pulse like fig6.
Figure 7 RTL schematic insight

Figure 8 Product
2. 8_bit counter down.

module counter8bit(
input clk,reset,
output reg [7:0] q
);
always @(posedge clk, posedge reset)
begin
if(reset) q<=0;
else
q <= q-1;
end
endmodule

The code for the 8_bit counter down is similar to the 4_bit counter up, but the output
q will have eight-bit and it will count down from 255 to 0.

Figure 9 Waveform

The waveform goes right behavior.

Figure 10 RTL schematic insight

Figure 11 Product

3. 8_bit counter up down and stop.

module counvip(
input clk,rst,SS,UD,
output reg [7:0] out
);
always @(posedge clk, negedge rst)
begin
if (rst)
out = 7'b0;
else if (UD == 1'b1)
case (SS)
1'b0 : out = out;
1'b1 : out = out + 1'b1;
endcase
else if (UD == 1'b0)
case (SS)
1'b0 : out = out;
1'b1 : out = out - 1'b1;
endcase
end
endmodule
This circuit is more special than the two circuits above, it’s HDL description
integrated more functions, that is stop function as SS input and UD input for
selecting to count up or count down, this point will help the user design the desired
counter circuit easier in reality.
Figure 12 Waveform

At first, 60ns is used to impact the RST input to initialize the output and begin to
count, at 60ns to 150ns when SS and UD are active low, the output is stopped
counting until the SS input is active high, the posedge CLK at 350ns, the output is
255 that means it counts down when UD is active low, at 550ns, UD is active high
then the output starts to count up until SS is active low again, the process is stopped.

Figure 13 RTL schematic insight

Figure 14 Product

4. 8_bit counter up down use a different clock from the Spartan3E kit.
module counterkid(
input clk,rst,SS,UD,sw,
output wire [7:0] out
);
wire [3:0] f;
wire clk_o;
frequency freqz (reset, clk, f);
mux mx ( f, sw, clk_o);
counvip coun ( clk_o, rst, SS, UD, out);
endmodule

This behavior shows how to test a counter circuit by kit Spartan3E, this kit uses a
50MHz clock pulse, thus, it has to connect through a divided frequency circuit has
a selection of low frequencies, the freqz circuit and the MX circuit will do that,
then a low-speed clock pulse is generated to serve the coun circuit begin to
perform its function.
Figure 15 RTL schematic insight

Fig15 shows the connection between the three circuits.

Figure 16 Product

James Ly
 REPORT ON SYSTEM AND INTEGRATED CIRCUIT DESIGN
DATED 07/10/2022

STUDENT’S NAME: LY GIA HUY

ID: 20161205

I. 74LS90
IC 74LS90 is a circuit that usually use to design a counting circuit or a frequency division circuit.
It can divide the frequency into three values 2, 5, and 10. It works the same as mod counters.

Figure 1 74ls90

It has a total of fourteen pins as the fig above, two clock pulse pins for the selection of which mod
want to count, four output pins, two pins for supply voltage and ground, and four pins reset active
high which R1, R2 is reset to 0 and R3, R4 is reset to 9, and finally is two pins not connected.
The idea of HDL description for this IC is to research its operation and its truth table is shown
below:
Figure 2 MASTER RESET

Fig2 shows the condition of the four elements reset will impact the output.

Figure 3 Count single mode

Fig3 shows how the IC would count for a single mode which means the mod 2 counter and mod 5
counter are synchronous countings.
Figure 4 Count in order

Fig4 shows the output count from 0 to 9, this is a mod 10 circuit which means the mod 2 counter
will operate as a clock pulse for the mod 5 counter, asynchronous counting.

module sub1(
input clk, output q
);
reg k = 0; wire k1;
always@(negedge clk)
begin
k <= k1;
end
assign k1 = k + 1; First instance’s behavior for the mod 2 counter.
assign q = k;
endmodule
module sub2( Second instance’s behavior for the mod 5
input wire clk, counter.
output wire [2:0] q
);
reg [2:0] k = 0; wire [2:0] k1;
always@(negedge clk)
begin
if ( k == 4 ) k <= 0;
else k <= k1;
end
assign k1 = k + 1;
assign q = k;
endmodule
 The top module
module ls7490(
input clkA,clkB , demonstrates the state of
input [1:0] mr,ms, the connection of two
output [3:0] q instances and the operator
); assigns a statement
wire [3:0] ko;
condition to set up the
sub1 mod2 (clkA, ko[0]); output work similar to the
sub2 mod5 (ko[0] , ko[3:1]); truth table.
assign q = (ms ==2'b11)? 4'b1001 : (( (mr == 2'b11 &&
ms[0]==1'b0 ) || (mr == 2'b11 && ms[1] ==1'b0) ) ? 4'b0000 :
{ko[3:1] , ko[0]} ) ;

endmodule

Figure 5 MOD 2 COUNTER

Figure 6 MOD 5 COUNTER

Figure 7 MOD SINGLE

Figure 8 MOD 10 COUNTER

The waveform goes correctly as the truth table above, the disadvantage of this circuit is not to
pause the counter when the reset input is activated, thus it has to go to the second counting period
for the right behavior.

Figure 9 RTL schematic insight

Figure 10 Product
 II. LED shift and add up circuit.
The HDL description below shows the behavior of the LED shift and add-up circuit, this circuit
requires two modes of LED, the first mode is shifted, the second mode adds sup light, then
combines two modes of this mode.
The idea for this circuit uses three variant reg type, and two variant integer type, firstly, the two
variant integer type is declared, one ( k ) is counted many time the LED will shift, and the
remaining ( i ) will count for the add up light, and here is the algorithm, the mode LED shift put
inside the mode add up, compare k and i to determine how many times shift, the first variants held
for the value of two remaining variants which is the sum of one is shifted and one is equal zero,
and add up the variant k, until k equal i, we decrease i by one and reset k also the one is shifted,
now the one variant is equal zero will hold the value for the first variant to hold the LED light up.
When i came to zero, it has to be reset to the number of bits the same as LED.

module sangdon(
input clk,reset,
output [7:0] q
);
integer i = 8, k=0 ;
reg [7:0] oneesama, onichan=8'h80 , oneechan=8'h00;

always@(posedge clk)
begin
if(reset) oneesama <= 8'h00;
else
if ( i > 0 )
begin
if ( k < i )
begin
oneesama <= onichan | oneechan;
onichan <= onichan >> 1;
k <= k+1;
end
else if ( k == i)
begin
i = i- 1;
k=0;
oneechan <= oneesama;
onichan <= 8'h80;
end
else i <= 8;
end
end
assign q = oneesama;
endmodule
The LED is shifted.

The LSB element is hold up the value.

 REPORT ON SYSTEM AND INTEGRATED CIRCUIT DESIGN
DATED 7/10/2022 & 14/10/2022
STUDENT’S NAME: LY GIA HUY
ID: 20161205

I. Finite-state machine
FSM is a mathematical model of computation. It is an abstract machine that can be in
exactly one of a finite number of states at any given time. The FSM can change from
one state to another in response to some inputs, the change from one state to another is
called a transition. An FSM is defined by a lot of its states, its initial state, and the
inputs that trigger each transition. The finite-state machine is of two types – Moore
machine uses only entry actions, and output depends only on the state, the mealy
machine also uses input actions output depends on input and state.
1. Write the behavior for FSM below.

Figure 1. Basics FSM

The idea for Verilog: the FSM has three different states S0, S1, and S2. Each state will
have the following value 2’b00, 2’b01, 2’b10. Then, an input and two outputs will be
set for the condition of each state of the following figure 1, the ( 1 / 0 ) meaning the
condition value (input/output) of each state, in the state S1, the output would be one
and state S2 and S3 are zeros. From state S1, if the input active is high, it will move to
the next state is still S1 and the output doesn’t change, if the input active is low, the
next state is S2 and the output will change to zero. For the Moore-type machine, the
output clearly depends on the present state, but for the mealy type machine, the output
also depends on the input and the present state, in this special case, how matter what
the input is, the output at state S1 is still one, thus, the mealy type would depend on
only the present state.
module fsm(
input wire clk , reset ,
input wire a,
output wire y1,
output reg y0
);
//symbolic state declaration
localparam [1:0] S0 = 2'b00, S1 = 2'b01 , S2=2'b10;
// signal declaration
reg [1 : 0] state_reg, state_next ;
// state register
always @ (posedge clk ,posedge reset)
if (reset)
state_reg<=S0;
else
state_reg<=state_next;
//next_state logic
always @(*)
case (state_reg)
S0: begin
if ( a == 1'b1) state_next=S1;
else state_next=S2;
//mealy machine
y0 = 0;
end

S1: begin
if ( a == 1'b1) state_next=S1;
else state_next=S2;
y0 = 1;
end

S2: begin
if ( a == 1'b1) state_next=S1;
else state_next=S2;
y0 = 0;
end

default: state_next=S0;
endcase
//moore machine
assign y1=(state_reg==S1)? 1'b1 : 1'b0;
endmodule
Figure 2 Test bench

From figure 2, the stimulation goes correctly in the behavior above, firstly, the reset input will be
active to initialize the value for the present state as S0 and the output is zeros for state S0, when
the input a is active low then the next state will be S2, at 100ns for the posedge CLK is activate
then the present state update to S2 and the output is zero for state S2. When input a is active high,
the next state goes to S1, at 300ns for the posedge CLK activates then the present state update to
S1 and the output is one for state S1. The rest are the same from the following figure 1.

Figure 3 The RTL schematic insight

Figure 4 Product

2. Write behavior for FSM below

Figure 5 Advance FSM

Idea: similar to figure 1, but this FSM has two inputs, four states, and different
outputs for each value of inputs, the beginning state is St0 and it also stands for the
reset state. St0, St1, St2, St3 are set the value as 2’b00, 2’b01, 2’b10, 2’b11. Q1
will define as Moore type and Q0 is a mealy type.
module oppa(
input wire clk , reset ,
input wire a, b,
output wire q0, q1 );
//symbolic state declaration
localparam [1:0] St0 = 2'b00, St1 = 2'b01 , St2=2'b10, St3= 2'b11;
// signal declaration
reg [1 : 0] state_reg, state_next ;
// state register
always @ (posedge clk ,posedge reset)
if (reset)
state_reg<=St0;
else
state_reg<=state_next;
//next_state logic
always @(*)
case (state_reg)
St0: begin
if ( a == 1'b0)
state_next=St2;
else
state_next=St1; end

St1: begin
if ( a == 1'b1)
state_next=St3;
else
state_next=St0; end

St2: begin
if ( a == 1'b1 )
begin
if(b)
state_next=St3;
else
state_next=St1;
end
else state_next = St2; end
St3: begin
if ( a == 1'b0 )
begin
if(b)
state_next=St2;
else
state_next=St0;
end
else state_next = St3; end

default: state_next=St0;
endcase
//moore machine
assign q1=(state_reg==St2 || state_reg==St3)? 1'b1 : 1'b0;
//mealy machine
assign q0=(state_reg==St2 || state_reg==St3)&a&b;

endmodule
Figure 6 Test bench

First, the reset input is activated to initialize the present state as St0, at the 150ns, the previous
state is St1, when a = 0, b = 1 the next state is St0 update for the present state, and the output Q1
= 0. At the 350ns, the previous state is St1, when a = 1, b = 1 then the next state is St3 updating
for the present state and the output Q1 = 1. At the 550ns, the previous state is St0, when a = 1,
b=0, the next state is St1 updating for the present state and the output Q1 =0. The stimulation goes
correctly.

Figure 7 The RTL schematic insight

Figure 8 Product

II. Combination circuit LED shift

Design an alarm led circuit using eight-bit LED as these require below: SW0 chooses
the speed of frequency swept at 4Hz or 10Hz from internal clock 2MHz; SW1 chooses
the mode of led: bit 0 lights up one by one then off all, bit 1 is flash off; SW3-SW2
define the remaining times for each mode would do, 2’b00: one time, 2’b01: two times,
2’10: three times and 2’b11: four times.
module LED(
input clk,reset, // xung 2Mhz
input sw0,sw1, //chon tan so va chon stop
input [1:0] sw23, //chon mode led
output [7:0] q // ngo ra
);
wire [7:0] bien, bientam;
wire [1:0] clk_o; // ngo ra chia tan
wire k, s_in;
wire [7:0] dem; // bien dich ngo vao

frequency freqz (clk, clk_o); // mach chia tan

mux2 mux (clk_o, sw0, k); // mach chon tan
sangdan led (k, reset, s_in, bien); // mach sang dan tu pst
choptat ko (k, reset, bientam); // mach dich bit tu ngoai vao trong
counterup nia (k, reset, sw23, dem); // khong che so lan

assign s_in = 1'b1;

assign q = ( (sw1 == 1'b0)&&(dem < (sw23*9)) )? bien : ( (sw1 == 1'b1)&&(dem < (sw23*2)) )? bientam :
8'b0 ;
endmodule

module frequency
#(parameter N= 21, M = 2000000)
( input wire clk,
output wire [1:0] q
);
reg [N-1:0] r_reg4H=0, r_reg10H=0;
wire [N-1:0] r_next4H,r_next10H;
always @(posedge clk)
begin
r_reg4H<=r_next4H;
r_reg10H<=r_next10H;
end
assign r_next4H = (r_reg4H ==M/4 )?0:r_reg4H + 1;
assign r_next10H = (r_reg10H==M/10 )?0:r_reg10H + 1;

// output logic
assign q[0]=(r_reg4H <M/8 )?0:1;
assign q[1]=(r_reg10H<M/20)?0:1;
endmodule
module mux2(
input [1:0] p,
input sel,
output q
);
reg biennho;

always@(*)
begin
case(sel)
0 : biennho = p[0];
1 : biennho = p[1];
endcase
end

assign q=biennho;
endmodule

module sangdan(
input clk,reset,s_in,
output [7:0] q_out
);
// signal declaration
reg [7:0] r_reg=0;
wire [7:0] r_next;
// body, register
always@(posedge clk)
begin
if(reset) r_reg<=8'b00000000;
else if (r_reg == 8'b11111111)
r_reg <= !r_reg;
else
r_reg <= r_next;
end
assign r_next = {s_in, r_reg[7:1]};
assign q_out = r_reg;
endmodule
module choptat(
input wire clk,reset,
output wire [7:0] q_out
);
// signal declaration
reg [7:0] r_reg;
wire [7:0] r_next;
// body, register
always@(posedge clk)
begin
if(reset) r_reg <=8'b0;
else
r_reg <= r_next;
end
assign r_next = !(r_reg);
assign q_out = r_reg;
endmodule

module counterup(
input clk, reset,
input [1:0] sw,
output [7:0] q
);
reg [7:0] r_reg=0;
reg [7:0] bien=0;
reg [2:0] tam=0, tt=1;
always@(sw)
begin
tam <= tam +1;
end
always@(posedge clk, sw)
begin
bien <= (sw*9);
if(reset) r_reg <= 2'b0;
else
if( tam > tt )
begin
r_reg <= 0;
tam <= 1;
end
else
if(r_reg < bien )
r_reg <= r_reg +1;
else
if(r_reg == bien )
r_reg <= r_reg;
end
assign q = r_reg;
endmodule