A3955 Datasheet PDF

A3955
Full-Bridge PWM Microstepping Motor Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: January 30, 2012
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, refer to the A4975.
NOTE: For detailed information on purchasing options, contact your

local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A3955
Full-Bridge PWM Microstepping Motor Driver
Features and Benefits Description

▪ ±1.5 A continuous output current The A3955 is designed to drive one winding of a bipolar
▪ 50 V output voltage rating stepper motor in a microstepping mode. The outputs are
▪ Internal PWM current control rated for continuous output currents to ±1.5 A and operating
▪ 3-bit nonlinear DAC voltages to 50 V. Internal pulse width modulated (PWM) current
▪ Fast, mixed fast/slow, and slow current-decay modes control combined with an internal three-bit nonlinear digital-
▪ Internal transient-suppression diodes to-analog converter allows the motor current to be controlled
▪ Internal thermal shutdown circuitry in full-, half-, quarter-, or eighth-step (microstepping) modes.
▪ Crossover-current and UVLO protection Nonlinear increments minimize the number of control lines
necessary for microstepping. Microstepping provides increased
step resolution, and reduces torque variations and resonance
problems at low speed.
Internal circuitry determines whether the PWM current-control
circuitry operates in a slow (recirculating) current-decay
Packages:
mode, fast (regenerative) current-decay mode, or in a mixed
current-decay mode in which the off-time is divided into a
period of fast current decay and with the remainder of the
fixed off-time spent in slow current decay. The combination of
user-selectable current-sensing resistor and reference voltage,
Package B, 16-pin DIP Package LB, 16-pin SOIC digitally selected output current ratio; and slow, fast, or mixed
with exposed tabs with internally fused pins current-decay modes provides users with a broad, variable
Not to scale range of motor control.
Continued on the next page…
Functional Block Diagram

SUPPLY
SUPPLY
LOGIC
OUTA
OUTB
LOAD
6 10 15 16
PHASE VCC
7
VBB
GROUND
4
5
UVLO
12 & TSD
13
BLANKING CURRENT-SENSE SENSE

MIXED-DECAY GATE COMPARATOR
PWM LATCH 11
COMPARATOR +
PFD 1 + R –
– Q
S
BLANKING ÷3 D/A DISABLE
RS
VCC + –
RC
V TH
3 2 8 9 14
D1
REF
D0
D2
CT
RT
Dwg. FP-042
29319.41G
A3955 Full-Bridge PWM Microstepping Motor Driver
Description (continued)
Internal circuit protection includes thermal shutdown with hysteresis, and a 16-lead plastic SOIC with internally fused pins (suffix ‘LB’).
transient-suppression diodes, and crossover-current protection. For both package styles, the thermally enhanced pins are at ground
Special power-up sequencing is not required. potential and need no electrical isolation. Both packages are lead
The A3955 is supplied in a choice of two power packages; a 16-pin (Pb) free, with leadframe plating 100% matte tin.
dual-in-line plastic package with copper heat-sink tabs (suffix ‘B’),
Selection Guide
Part Number Packing Package
A3955SB-T 16-pin DIP with exposed thermal tabs 25 per tube
A3955SLBTR-T 16-pin SOICW with internally fused pins 1000 per reel
Absolute Maximum Ratings

Characteristic Symbol Notes Rating Units
Load Supply Voltage VBB 50 V
Logic Supply Voltage VCC 7.0 V
Logic/Reference Input Voltage Range VIN –0.3 to VCC + 0.3 V
Sense Voltage VS 1.0 V
Output current rating may be limited by duty cycle, ambient
temperature, and heat sinking. Under any set of conditions, do
Output Current, Continuous IOUT ±1.5 A
not exceed the specified current rating or a junction tempera-
ture of 150°C.
Package Power Dissipation PD See graph W
Operating Ambient Temperature TA Range S –20 to 85 ºC
Fault conditions that produce excessive junction temperature
Maximum Junction Temperature TJ(max) will activate the device’s thermal shutdown circuitry. These 150 ºC
conditions can be tolerated but should be avoided.
Storage Temperature Tstg –55 to 150 ºC
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
B Package, single-layer PCB, 1 in.2 2-oz. exposed copper 43 ºC/W
Package Thermal Resistance, Junction
RθJA LB Package, 2-layer PCB, 0.3 in.2 2-oz. exposed copper each
to Ambient 67 ºC/W
side
Package Thermal Resistance, Junction
RθJT 6 ºC/W
to Tab
*Additional thermal information available on Allegro website.
ALLOWABLE PACKAGE POWER DISSIPATION (W)
R θJT = 6.0°C/W
SUFFIX 'B', R θJA = 43°C/W

2
SUFFIX 'LB', R θJA = 67°C/W
0
25 50 75 100 125 150
TEMPERATURE IN °C
Allegro MicroSystems, Inc. 2

115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V

(unless otherwise noted.)
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Power Outputs
Load Supply Voltage Range VBB Operating, IOUT = ±1.5 A, L = 3 mH VCC — 50 V
Output Leakage Current ICEX VOUT = VBB — <1.0 50 μA
VOUT = 0 V — <-1.0 -50 μA
Output Saturation Voltage VCE(SAT) VS = 1.0 V:

(Forward or Reverse Mode) Source Driver, IOUT = -0.85 A — 1.0 1.2 V
Source Driver, IOUT = -1.5 A — 1.3 1.5 V
Sink Driver, IOUT = 0.85 A — 0.5 0.6 V
Sink Driver, IOUT = 1.5 A — 1.3 1.5 V
Sense Current Offset ISO IS - IOUT, IOUT = 850 mA, 20 33 40 mA
VS = 0 V, VCC = 5 V
Clamp Diode Forward Voltage VF IF = 0.85 A — 1.2 1.4 V
(Sink or Source) IF = 1.5 A — 1.4 1.7 V
Motor Supply Current IBB(ON) — 2.0 4.0 mA
(No Load) IBB(OFF) D0 = D1 = D2 = 0.8 V — 1.0 50 μA
Continued next page…
Table 1 — PHASE Truth Table Table 3 — DAC Truth Table

PHASE OUTA OUTB DAC DATA Current
D2 D1 D0 Ratio, % VREF/VS
H H L
L L H H H H 100 3.00
H H L 92.4 3.25
Table 2 — PFD Truth Table H L H 83.1 3.61
H L L 70.7 4.24
VPFD Description
L H H 55.5 5.41
≥3.5 V Slow Current-Decay Mode
L H L 38.2 7.85
1.1 V to 3.1 V Mixed Current-Decay Mode
L L H 19.5 15.38
≤0.8 V Fast Current-Decay Mode
L L L All Outputs Disabled
where VS = ITRIP•RS. See Applications section.

ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VBB = 5 V to 50 V, VCC = 4.5 V to

5.5 V (unless otherwise noted. )
Limits
Control Circuitry
Logic Supply Voltage Range VCC Operating 4.5 5.0 5.5 V
Reference Voltage Range VREF Operating 0.5 — 2.5 V
UVLO Enable Threshold VCC = 0 →5 V 3.35 3.70 4.05 V
UVLO Hysteresis 0.30 0.45 0.60 V
Logic Supply Current ICC(ON) — 42 50 mA
ICC(OFF) D0 = D1 = D2 = 0.8 V — 12 16 mA
Logic Input Voltage VIN(1) 2.0 — — V
VIN(0) — — 0.8 V
Logic Input Current IIN(1) VIN = 2.0 V — <1.0 20 μA
IIN(0) VIN = 0.8 V — <-2.0 -200 μA
Mixed-Decay Comparator VPFD Slow Current-Decay Mode 3.5 — — V
Trip Points Mixed Current-Decay Mode 1.1 — 3.1 V
Fast Current-Decay Mode — — 0.8 V
Mixed-Decay Comparator VIO(PFD) — 0 ±20 mV
Input Offset Voltage
Mixed-Decay Comparator ∆VIO(PFD) 5.0 25 55 mV
Hysteresis
Reference Input Current IREF VREF = 0 V to 2.5 V — — ±5.0 μA
Reference Divider Ratio VREF/VS at trip, D0 = D1 = D2 = 2 V — 3.0 — —
Digital-to-Analog Converter — 1.0 V < VREF 2.5 V — — ±3.0 %
Accuracy*
0.5 V < VREF 1.0 V — — ±4.0 %
Current-Sense Comparator VIO(S) VREF = 0 V — — ±5.0 mV
Input Offset Voltage*
Step Reference SRCR D0 = D1 = D2 = 0.8 V — 0 — %

Current Ratio D0 = 2 V, D1 = D2 = 0.8 V — 19.5 — %
D0 = 0.8 V, D1 = 2 V, D2 = 0.8 V — 38.2 — %
D0 = D1 = 2 V, D2 = 0.8 V — 55.5 — %
D0 = D1 = 0.8 V, D2 = 2 V — 70.7 — %
D0 = 2 V, D1 = 0.8 V, D2 = 2 V — 83.1 — %
D0 = 0.8 V, D1 = D2 = 2 V — 92.4 — %
D0 = D1 = D2 = 2 V — 100 — %
Continued next page…

* The total error for the VREF/VS function is the sum of the D/A error and the current-sense comparator input offset voltage.

ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VBB = 5 V to 50 V, VCC = 4.5 V to

5.5 V (unless otherwise noted. )
Limits
Control Circuitry (cont’d)

Thermal Shutdown Temp. TJ — 165 — °C
Thermal Shutdown Hysteresis ∆TJ — 15 — °C
AC Timing
PWM RC Fixed Off-time tOFF RC CT = 470 pF, RT= 43 kΩ 18.2 20.2 22.3 μs
PWM Turn-Off Time tPWM(OFF) Current-Sense Comparator Trip — 1.0 1.5 μs
to Source OFF, IOUT = 100 mA
Current-Sense Comparator Trip — 1.4 2.5 μs
to Source OFF, IOUT = 1.5 A
PWM Turn-On Time tPWM(ON) IRC Charge ON to Source ON, — 0.4 0.7 μs
IOUT = 100 mA
IRC Charge ON to Source ON, — 0.55 0.85 μs
IOUT = 1.5 A
PWM Minimum On Time tON(min) VCC = 5.0 V, RT ≥ 43 kΩ, CT = 470 pF 1.0 1.6 2.2 μs
IOUT = 100 mA
Crossover Dead Time tCODT 1 kΩ Load to 25 V 0.3 1.5 3.0 μs

Note the A3955SB (DIP) and the A3955SLB

(SOIC) are electrically identical and share a
common terminal number assignment.
Terminal Functions
Terminal Name Description
1 PFD (Percent Fast Decay) The analog input used to set the current-decay mode.
2 REF (VREF) The voltage at this input (along with the value of RS and the states of DAC inputs
D0, D1, and D2) set the peak output current.
3 RC The parallel combination of external resistor RT and capacitor CT set the off time for the
PWM current regulator. CT also sets the blanking time.
4-5 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage
measurements.
6 LOGIC SUPPLY (VCC) Supply voltage for the logic circuitry. Typically = 5 V.
7 PHASE The PHASE input determines the direction of current in the load.
8 D2 (DATA2) One-of-three (MSB) control bits for the internal digital-to-analog converter.
9 D1 (DATA1) One-of-three control bits for the internal digital-to-analog converter.
10 OUTA One-of-two output load connections.
11 SENSE Connection to the sink-transistor emitters. Sense resistor RS is connected between this
point and ground.
12-13 GROUND Return for the logic supply (VCC) and load supply (VBB); the reference for all voltage
measurements.
14 D0 (DATA0) One-of-three (LSB) control bits for the internal digital-to-analog converter.
15 OUTB One-of-two output load connections.
16 LOAD SUPPLY (VBB) Supply voltage for the load.

Functional Description which turns off the source drivers (slow-decay mode) or the sink
and source drivers (fast- or mixed-decay mode).
Two A3955 full-bridge PWM microstepping motor drivers are
needed to drive the windings of a bipolar stepper motor. Internal With the DATA input lines tied to VCC, the maximum value of
pulse width modulated (PWM) control circuitry regulates each current limiting is set by the selection of RS and VREF with a
motor winding current. The peak motor current is set by the transconductance function approximated by:
value of an external current-sense resistor (RS), a reference ITRIP ≈ VREF / 3RS.
voltage (VREF), and the digital-to-analog converter (DAC) data
inputs (D0, D1, and D2). The actual peak load current (IPEAK) will be slightly higher than
ITRIP due to internal logic and switching delays. The driver(s)
To improve motor performance, especially when using remain off for a time period determined by a user-selected
sinusoidal current profiles necessary for microstepping, the external resistor-capacitor combination (RTCT). At the end of
A3955 has three distinct current-decay modes: slow decay, fast the fixed off-time, the driver(s) are re-enabled, allowing the load
decay, and mixed decay. current to increase to ITRIP again, maintaining an average load
PHASE Input. The PHASE input controls the direction of current.
current flow in the load (table 1). An internally generated dead The DAC data input lines are used to provide up to eight levels
time of approximately 1 μs prevents crossover currents that of output current. The internal 3-bit digital-to-analog converter
could occur when switching the PHASE input. reduces the reference input to the current-sense comparator
DAC Data Inputs (D0, D1, D2). A non-linear DAC is used in precise steps (the step reference current ratio or SRCR) to
to digitally control the output current. The output of the DAC is provide half-step, quarter-step, or “microstepping” load-current
used to set the trip point of the current-sense comparator. Table 3 levels.
shows DAC output voltages for each input condition. When D0, ITRIP ≈ SRCR x VREF/3RS
D1, and D2 are all logic low, all of the power output transistors
are turned off. Slow Current-Decay Mode. When VPFD ≥ 3.5 V, the
device is in slow current-decay mode (the source drivers are
Internal PWM Current Control. Each motor driver disabled when the load current reaches ITRIP). During the fixed
contains an internal fixed off-time PWM current-control circuit off-time, the load inductance causes the current to recirculate
that limits the load current to a desired value (ITRIP). Initially, through the motor winding, sink driver, ground clamp diode,
a diagonal pair of source and sink transistors are enabled and and sense resistor (see figure 1). Slow-decay mode produces
current flows through the motor winding and RS (figure 1). When low ripple current for a given fixed off-time (see figure 2).
the voltage across the sense resistor equals the DAC output Low ripple current is desirable because the average current
voltage the current-sense comparator resets the PWM latch, in the motor winding is more nearly equal to the desired
V
BB
I PEAK
SLOW (VPFD ≥ 3.5 V)
MIXED (1.1 V ≤ V PFD ≤ 3.1 V)

DRIVE CURRENT
RECIRCULATION FAST (V PFD ≤ 0.8 V)

(SLOW-DECAY MODE) PFD
RECIRCULATION
(FAST-DECAY MODE)
t OFF
Dwg. WP-031-1
RS
Dwg. EP-006-15
Figure 1 — Load-Current Paths Figure 2 — Current-Decay Waveforms

reference value, resulting in increased motor performance in

microstepping applications.
For a given level of ripple current, slow decay affords the lowest
PWM frequency, which reduces heating in the motor and driver
IC due to a corresponding decrease in hysteretic core losses and
switching losses respectively. Slow decay also has the advantage
that the PWM load current regulation can follow a more rapidly
increasing reference before the PWM frequency drops into the
audible range. For these reasons slow-decay mode is typically
used as long as good current regulation can be maintained.
Under some circumstances slow-decay mode PWM can fail to
maintain good current regulation:
A — Slow-Decay
1) The load current will fail to regulate in slow-decay mode
due to a sufficiently negative back-EMF voltage in conjunction
with the low voltage drop across the load during slow decay
recirculation. The negative back-EMF voltage can cause the load
current to actually increase during the slow decay off time. A
negative back-EMF voltage condition commonly occurs when
driving stepping motors because the phase lead of the rotor
typically causes the back-EMF voltage to be negative towards
the end of each step (see figure 3A).
2) When the desired load current is decreased rapidly, the slow
rate of load current decay can prevent the current from following
the desired reference value.
3) When the desired load current is set to a very low value, the
current-control loop can fail to regulate due to its minimum duty B — Fast-Decay
cycle, which is a function of the user-selected value of tOFF and
the minimum on-time pulse width ton(min) that occurs each time
the PWM latch is reset.
Fast Current-Decay Mode. When VPFD 0.8 V, the device
is in fast current-decay mode (both the sink and source drivers
are disabled when the load current reaches ITRIP). During the
fixed off-time, the load inductance causes the current to flow
from ground to the load supply via the motor winding, ground-
clamp and flyback diodes (see figure 1). Because the full motor
supply voltage is across the load during fast-decay recirculation,
the rate of load current decay is rapid, producing a high ripple
current for a given fixed off-time (see figure 2). This rapid rate of
decay allows good current regulation to be maintained at the cost
of decreased average current accuracy or increased driver and
C — Mixed-Decay
motor losses.
Figure 3 — Sinusoidal Drive Currents

Mixed Current-Decay Mode. If VPFD is between 1.1 V With increasing values of tOFF, switching losses will decrease,
and 3.1 V, the device will be in a mixed current-decay mode. low-level load-current regulation will improve, EMI will be
Mixed-decay mode allows the user to achieve good current reduced, the PWM frequency will decrease, and ripple current
regulation with a minimum amount of ripple current and will increase. A value of tOFF can be chosen for optimization
motor/driver losses by selecting the minimum percentage of fast of these parameters. For applications where audible noise is a
decay required for their application (see also the Stepper Motor concern, typical values of tOFF are chosen to be in the range of
Applications section). 15 to 35 μs.
As in fast current-decay mode, mixed-decay starts with the sink RC Blanking. In addition to determining the fixed off-time of
and source drivers disabled after the load current reaches ITRIP. the PWM control circuit, the CT component sets the comparator
When the voltage at the RC terminal decays to a value below blanking time. This function blanks the output of the current-
VPFD, the sink drivers are re-enabled, placing the device in slow sense comparator when the outputs are switched by the internal
current-decay mode for the remainder of the fixed off-time current-control circuitry (or by the PHASE input, or when the
(figure 2). The percentage of fast decay (PFD) is user determined device is enabled with the DAC data inputs). The comparator
by VPFD or two external resistors. output is blanked to prevent false over-current detections due to
PFD = 100 ln (0.6[R1+R2]/R2) reverse recovery currents of the clamp diodes, and/or switching
transients related to distributed capacitance in the load.
where:
VCC During internal PWM operation, at the end of the tOFF time, the
comparator’s output is blanked and CT begins to be charged
R1 from approximately 0.22VCC by an internal current source of
approximately 1 mA. The comparator output remains blanked
until the voltage on CT reaches approximately 0.6VCC. The
PFD
blanking time, tBLANK, can be calculated as:
R2 tBLANK = RTCT ln (RT/[RT – 3 kΩ]).

When a transition of the PHASE input occurs, CT is discharged
to near ground during the crossover delay time (the crossover
D EP 062
delay time is present to prevent simultaneous conduction of
Fixed Off-Time. The internal PWM current-control circuitry the source and sink drivers). After the crossover delay, CT is
uses a one shot to control the time the driver(s) remain(s) off. charged by an internal current source of approximately 1 mA.
The one-shot off-time, tOFF, is determined by the selection of The comparator output remains blanked until the voltage on CT
an external resistor (RT) and capacitor (CT) connected from the reaches approximately 0.6VCC.
RC timing terminal to ground. The off-time, over a range of
values of CT = 470 pF to 1500 pF and RT = 12 kΩ to 100 kΩ, is Similarly, when the device is disabled, via the DAC data inputs,
approximated by: CT is discharged to near ground. When the device is re-enabled,
CT is charged by an internal current source of approximately 1
tOFF ≈ RTCT. mA. The comparator output remains blanked until the voltage on
When the load current is increasing, but has not yet reached the CT reaches approximately 0.6VCC. The blanking time, tBLANK,
sense-current comparator threshold (ITRIP), the voltage on the can be calculated as:
RC terminal is approximately 0.6VCC. When ITRIP is reached,
tBLANK = RTCT ln ([RT - 1.1 kΩ]/RT - 3 kΩ).
the PWM latch is reset by the current-sense comparator and
the voltage on the RC terminal will decay until it reaches The minimum recommended value for CT is 470 pF ± 5 %.
approximately 0.22VCC. The PWM latch is then set, thereby This value ensures that the blanking time is sufficient to avoid
re-enabling the driver(s) and allowing load current to increase false trips of the comparator under normal operating conditions.
again. The PWM cycle repeats, maintaining the peak load For optimal regulation of the load current, this value for CT is
current at the desired value. recommended and the value of RT can be sized to determine tOFF.

Thermal Considerations. Thermal-protection circuitry drive applications (see figures 4 and 5). When the load current
turns off all output transistors when the junction temperature is increasing, the slow current-decay mode is used to limit the
reaches approximately +165°C. This is intended only to protect switching losses in the driver and iron losses in the motor. This
the device from failures due to excessive junction temperatures also improves the maximum rate at which the load current can
and should not imply that output short circuits are permitted. The increase (as compared to fast decay) due to the slow rate of
output transistors are re-enabled when the junction temperature decay during tOFF. When the load current is decreasing, the mixed
cools to approximately +150°C. current-decay mode is used to regulate the load current to the
Stepper Motor Applications. The A3955 is used to desired level. This prevents tailing of the current profile caused
optimize performance in microstepping/sinusoidal stepper-motor by the back-EMF voltage of the stepper motor (see figure 3A).
VBB
BRIDGE A BRIDGE B
V PFD 16
D 1B D2B
1 9 8
47 μF
+
V REF 2 15 10 7 PHASE B
D 0A
3 14 11 6 +5 V
470 pF
0.5 Ω
30 kΩ
4 13 12 5
470 pF
LOGIC LOGIC
30 kΩ
0.5 Ω
5 12 13 4
+5 V 6 11
11 D0B 14 3
PHASE A 7 10 15 2 V REF
47 μF
+
D2A 8 9 D 1A VBB 16 1 V PFD
Dwg. EP-047-3
Figure 4 — Typical Application
MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY
Dwg. WK-004-3
Figure 5 — Microstepping/Sinusoidal Drive Current

Table 4 — Step Sequencing
Bridge A Bridge B
Full Half Quarter Eighth
Step Step Step Step PHASEA D2A D1A D0A ILOADA PHASEB D2B D1B D0B ILOADB
1 1 1 1 H H L L 70.7% H H L L 70.7%
2 H L H H 55.5% H H L H 83.1%
2 3 H L H L 38.2% H H H L 92.4%
4 H L L H 19.5% H H H H 100%
2 3 5 X L L L 0% H H H H 100%
6 L L L H -19.5% H H H H 100%
4 7 L L H L -38.2% H H H L 92.4%
8 L L H H -55.5% H H L H 83.1%
2 3 5 9 L H L L -70.7% H H L L 70.7%
10 L H L H -83.1% H L H H 55.5%
6 11 L H H L -92.4% H L H L 38.2%
12 L H H H -100% H L L H 19.5%
4 7 13 L H H H -100% X L L L 0%
14 L H H H -100% L L L H -19.5%
8 15 L H H L -92.4% L L H L -38.2%
16 L H L H -83.1% L L H H -55.5%
3 5 9 17 L H L L -70.7% L H L L -70.7%
18 L L H H -55.5% L H L H -83.1%
10 19 L L H L -38.2% L H H L -92.4%
20 L L L H -19.5% L H H H -100%
6 11 21 X L L L 0% L H H H -100%
22 H L L H 19.5% L H H H -100%
12 23 H L H L 38.2% L H H L -92.4%
24 H L H H 55.5% L H L H -83.1%
4 7 13 25 H H L L 70.7% L H L L -70.7%
26 H H L H 83.1% L L H H -55.5%
14 27 H H H L 92.4% L L H L -38.2%
28 H H H H 100% L L L H -19.5%
8 15 29 H H H H 100% X L L L 0%
30 H H H H 100% H L L H 19.5%
16 31 H H H L 92.4% H L H L 38.2%
32 H H L H 83.1% H L H H 55.5%

A MAXIMUM FULL-STEP
100
TORQUE (141%)
92.4
10
P
83.1
E
0%
1/8 ST
TEP
C
O
N
ST
S
EP
1/4
AN
70.7
ST
T
TO
3/8
CURRENT IN PER CENT
R
Q
EP
U
ST
E
2
55.5
1/ EP
ST
5/8
38.2
P
STE
3/4
19.5 EP
7/8 ST
FULL STEP
B B
19.5 38.2 55.5 70.7 83.1 92.4 100

A CURRENT IN PER CENT
Dwg. GK-020-1
Figure 5 —
Current and Displacement Vectors

B package 16-pin DIP

19.05±0.25
16
+0.10
0.38 –0.05
+0.76 +0.38
6.35 –0.25 10.92 –0.25 7.62
A
1 2
For Reference Only

5.33 MAX
(reference JEDEC MS-001 BB)
Dimensions in millimeters
+0.51 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
3.30 –0.38
Exact case and lead configuration at supplier discretion within limits shown
1.27 MIN 2.54 A Terminal #1 mark area
+0.25
1.52 –0.38
0.46 ±0.12
LB package 16-pin SOICW

10.30±0.20 1.27
0.65
4° ±4
16
+0.07
0.27 –0.06
7.50±0.10 10.30±0.33 9.50
A
+0.44
0.84 –0.43
2.25
1 2
B PCB Layout Reference View
0.25
For Reference Only

16X C SEATING PLANE
SEATING Pins 4 and 5, and 12 and 13 internally fused
0.10 C PLANE GAUGE PLANE Dimensions in millimeters
(reference JEDEC MS-013 AA)
0.41 ±0.10 1.27 Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
2.65 MAX Exact case and lead configuration at supplier discretion within limits shown
0.20 ±0.10
A Terminal #1 mark area
B Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Copyright ©1997-2010, Allegro MicroSystems, Inc.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:

www.allegromicro.com


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A3955

Full-Bridge PWM Microstepping Motor Driver

Date of status change: January 30, 2012

NOTE: For detailed information on purchasing options, contact your

Full-Bridge PWM Microstepping Motor Driver

Features and Benefits Description

Functional Block Diagram

BLANKING CURRENT-SENSE SENSE

Absolute Maximum Ratings

SUFFIX 'B', R θJA = 43°C/W

SUFFIX 'LB', R θJA = 67°C/W

Allegro MicroSystems, Inc. 2

ELECTRICAL CHARACTERISTICS at TA = 25°C, VBB = 5 V to 50 V, VCC = 4.5 V to 5.5 V

Output Saturation Voltage VCE(SAT) VS = 1.0 V:

Continued next page…

Table 1 — PHASE Truth Table Table 3 — DAC Truth Table

Allegro MicroSystems, Inc. 3

ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VBB = 5 V to 50 V, VCC = 4.5 V to

Step Reference SRCR D0 = D1 = D2 = 0.8 V — 0 — %

Continued next page…

Allegro MicroSystems, Inc. 4

ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VBB = 5 V to 50 V, VCC = 4.5 V to

Control Circuitry (cont’d)

Allegro MicroSystems, Inc. 5

Note the A3955SB (DIP) and the A3955SLB

Allegro MicroSystems, Inc. 6

MIXED (1.1 V ≤ V PFD ≤ 3.1 V)

RECIRCULATION FAST (V PFD ≤ 0.8 V)

Figure 1 — Load-Current Paths Figure 2 — Current-Decay Waveforms

Allegro MicroSystems, Inc. 7

reference value, resulting in increased motor performance in

Figure 3 — Sinusoidal Drive Currents

Allegro MicroSystems, Inc. 8

R2 tBLANK = RTCT ln (RT/[RT – 3 kΩ]).

Allegro MicroSystems, Inc. 9

D2A 8 9 D 1A VBB 16 1 V PFD

Figure 4 — Typical Application

MIXED DECAY SLOW DECAY MIXED DECAY SLOW DECAY

Figure 5 — Microstepping/Sinusoidal Drive Current

Allegro MicroSystems, Inc. 10

Table 4 — Step Sequencing

Allegro MicroSystems, Inc. 11

19.5 38.2 55.5 70.7 83.1 92.4 100

Allegro MicroSystems, Inc. 12

B package 16-pin DIP

For Reference Only

LB package 16-pin SOICW

7.50±0.10 10.30±0.33 9.50

For Reference Only

Copyright ©1997-2010, Allegro MicroSystems, Inc.

For the latest version of this document, visit our website:

Allegro MicroSystems, Inc. 13

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