Uc184xa PDF
Uc184xa PDF
Uc184xa PDF
M PACKAGE:
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 95°C/W COMP 1 14 VREF
N.C. 2 13 N.C.
DM PACKAGE:
VFB 3 12 VCC
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 165°C/W N.C. 4 11 VC
D PACKAGE: ISENSE 5 10 OUTPUT
N.C. 6 9 GND
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 120°C/W RT/CT 7 8 PWR GND
Y PACKAGE: D PACKAGE
THERMAL RESISTANCE-JUNCTION TO AMBIENT, θ JA 130°C/W (Top View)
RoHS / Pb-free 100% Matte Tin Lead Finish
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θ JA numbers are guidelines for the thermal performance of the device/pc-board system.
All of the above assume no ambient airflow
Copyright © 1995
2 Rev. 1.2a 10/25
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P R O D U C T I O N D A T A S H E E T
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for UC384xA with 0°C ≤ TA ≤ 70°C, UC284xA with -40°C ≤ TA ≤ 85°C,
UC184xA with -55°C ≤ TA ≤ 125°C; VCC=15V; RT=10K; C T=3.3nF. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal
to the ambient temperature.)
UC184xA/284xA UC384xA
Parameter Symbol Test Conditions Units
Min. Typ. Max. Min. Typ. Max.
Reference Section
Output Voltage VREF TJ = 25°C, IL = 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V
Line Regulation 12 ≤ VIN ≤ 25V 6 20 6 20 mV
Load Regulation 1 ≤ IO ≤ 20mA 6 25 6 25 mV
Temperature Stability (Note 2 & 7) 0.2 0.4 0.2 0.4 mV/°C
Total Output Variation Over Line, Load, and Temperature 4.9 5.1 4.82 5.18 V
Output Noise Voltage (Note 2) VN 10Hz ≤ f ≤ 10kHz, TJ = 25°C 50 50 µV
Long Term Stability (Note 2) TA = 125°C, t = 1000hrs 5 25 5 25 mV
Output Short Circuit Current ISC -30 -100 -180 -30 -100 -180 mA
Oscillator Section
Initial Accuracy (Note 6) TJ = 25°C 47 52 57 47 52 57 kHz
Voltage Stability 12 ≤ VCC ≤ 25V 0.2 1 0.2 1 %
Temperature Stability (Note 2) TMIN ≤ TA ≤ TMAX 5 5 %
Amplitude (Note 2) 1.7 1.7 V
Discharge Current TJ = 25°C, VPIN 4 = 2V 7.8 8.3 8.8 7.8 8.3 8.8 mA
VPIN 4 = 2V, TMIN ≤ TA ≤ TMAX 7.5 8.8 7.6 8.8 mA
Error Amp Section
Input Voltage VPIN 1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V
Input Bias Current IB -0.3 -1 -0.3 -2 µA
Open Loop Gain AVOL 2 ≤ V O ≤ 4V 65 90 65 90 dB
Unity Gain Bandwidth (Note 2) UGBW Tj = 25°C 0.7 1 0.7 1 MHz
Power Supply Rejection Ratio (Note 3) PSRR 12 ≤ VCC ≤ 25V 60 70 60 70 dB
Output Sink Current IOL VPIN 2 = 2.7V, VPIN 1 = 1.1V 2 6 2 6 mA
Output Source Current I OH VPIN 2 = 2.3V, VPIN 1 = 5V -0.5 -0.8 -0.5 -0.8 mA
Output Voltage High Level VOH VPIN 2 = 2.3V, RL = 15K to ground 5 6 5 6 V
Output Voltage Low Level VOL VPIN 2 = 2.7V, RL = 15K to VREF 0.7 1.1 0.7 1.1 V
Current Sense Section
Gain (Note 3 & 4) AVOL 2.85 3 3.15 2.85 3 3.15 V/V
Maximum Input Signal (Note 3) VPIN 1 = 5V 0.9 1 1.1 0.9 1 1.1 V
Power Supply Rejection Ratio (Note 3) PSRR 12 ≤ VCC ≤ 25V 70 70 dB
Input Bias Current IB -2 -10 -2 -10 µA
Delay to Output (Note 2) Tpd VPIN 3 = 0 to 2V 150 300 150 300 ns
Output Section
Output Low Level ISINK = 20mA 0.1 0.4 0.1 0.4 V
VOL
ISINK = 200mA 1.5 2.2 1.5 2.2 V
Output High Level ISOURCE = 20mA 13 13.5 13 13.5 V
VOH
ISOURCE = 200mA 12 13.5 12 13.5 V
Rise Time (Note 2) TR TJ = 25°C, CL = 1nF 50 150 50 150 ns
Fall Time (Note 2) TF TJ = 25°C, CL = 1nF 50 150 50 150 ns
UVLO Saturation VSAT VCC = 5V, ISINK = 10mA 0.7 1.2 0.7 1.2 V
(Electrical Characteristics continue next page.)
Copyright © 1995
Rev. 1.2a 10/25 3
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P R O D U C T I O N D A T A S H E E T
UC184xA/284xA UC384xA
Parameter Symbol Test Conditions Units
Min. Typ. Max. Min. Typ. Max.
Under-Voltage Lockout Section
Start Threshold x842A/4A 15 16 17 14.5 16 17.5 V
x843A/5A 7.8 8.4 9.0 7.8 8.4 9.0 V
Min. Operation Voltage After Turn-On x842A/4A 9 10 11 8.5 10 11.5 V
x843A/5A 7.0 7.6 8.2 7.0 7.6 8.2 V
PWM Section
Maximum Duty Cycle x842A/3A 94 96 100 94 96 100 %
x844A/5A 47 48 50 47 48 50 %
Minimum Duty Cycle 0 0 %
Total Standby Section
Start-Up Current 0.3 0.5 0.3 0.5 mA
Operating Supply Current I CC 11 17 11 17 mA
Zener Voltage VZ ICC = 25mA 30 35 30 35 V
Notes: 2. These parameters, although guaranteed, are not 100% tested in 7. "Temperature stability, sometimes referred to as average temperature
production. coefficient, is described by the equation:
3. Parameter measured at trip point of latch with VVFB = 0. VREF (max.) - VREF (min.)
∆ V COMP Temp Stability =
T J (max.) - TJ (min.)
4. Gain defined as: AVOL = ; 0 ≤ V ISENSE ≤ 0.8V.
∆ VISENSE
V REF (max.) & V REF (min.) are the maximum & minimum reference
5. Adjust VCC above the start threshold before setting at 15V. voltage measured over the appropriate temperature range. Note that
6. Output frequency equals oscillator frequency for the UC1842A the extremes in voltage do not necessarily occur at the extremes in
and UC1843A. Output frequency is one half oscillator frequency temperature."
for the UC1844A and UC1845A.
BLOCK DIAGRAM
VCC *
34V
UVLO VREF
S/R 5V 5.0V
** Hysteresis Ref
GROUND 50mA
6V (1842A/4A)
UVLO
0.8V (1843A/5A)
16V (1842A/4A)
8.4V (1843A/5A) Internal
Bias
2.5V
*
VREF VC
Good Logic
RT/CT Oscillator
*** T
OUTPUT
Error Amp S
2R
VFB R PWM
R 1V Latch **
Current Sense POWER GROUND
COMP
Comparator
CURRENT SENSE
Copyright © 1995
4 Rev. 1.2a 10/25
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P R O D U C T I O N D A T A S H E E T
CHARACTERISTIC CURVES
VREF 8
CT = 1nF
Oscillator Frequency - (Hz)
1M RT
CT = 2.2nF RT/CT 4
100k CT
GROUND 5
CT = 4.7nF
10k
1.72
For RT > 5k, f »
RT CT
RT - (ohms)
100.0
80.0
Maximum Duty Cycle - (%)
60.0
40.0
20.0
0
300 1.0k 3.0k 10.0k 30.0k 100k
RT - (ohms)
Copyright © 1995
Rev. 1.2a 10/25 5
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P R O D U C T I O N D A T A S H E E T
T Y P I C A L A P P L I C AT I O N C I R C U I T S
7
7
R1 Q1
Q1
UCx84xA UCx84xA 6
6
5
IPK
CHANGE RS
3 1.0V
IPK(MAX) =
C RS RS 5
The RC low pass filter will eliminate the leading edge current spike A resistor (R1) in series with the MOSFET gate will reduce overshoot
caused by parasitics of Power MOSFET. & ringing caused by the MOSFET input capacitance and any
inductance in series with the gate drive. (Note: It is very important to
have a low inductance ground path to insure correct operation of the
I.C. This can be done by making the ground paths as short and as
wide as possible.)
RA 8 4
7
UCx84xA
6 555 3 4
RB
TIMER
2
5 1
0.01 5
To other
1.44
UCx84xA devices
f=
(R A + 2RB)C
RB Precision duty cycle limiting as well as synchronizing several parts is
f=
RA + 2R B possible with the above circuitry.
Copyright © 1995
6 Rev. 1.2a 10/25
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P R O D U C T I O N D A T A S H E E T
T Y P I C A L A P P L I C AT I O N C I R C U I T S (continued)
UCx84xA 7(12)
VO
5V
8(14)
UVLO
S 5V
R REF
RT
INTERNAL
BIAS
2.5V
2N222A
VREF
GOOD LOGIC
7(11)
RSLOPE
4(7)
OSCILLATOR Q1
From VO CT
6(10)
C.S.
2R COMP
Ri
2(3)
1V
ERROR R 5(8)
Rd CF RF AMP PWM
LATCH R
1(1) 3(5)
C RS
5(9)
Due to inherent instability of current mode converters running above 50% duty cycle, slope compensation should be added to either
the current sense pin or the error amplifier. Figure 6 shows a typical slope compensation technique.
VREF
RT
A VCC
UCx84xA
2N2222
4.7K
1 COMP VREF 8
100K
1K 2 VFB VCC 7
0.1µF 0.1µF
ERROR AMP 1K
ADJUST 5K
4.7K ISENSE 3 ISENSE OUTPUT 6 OUTPUT
ADJUST
4 RTCT GROUND 5
GROUND
CT
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be
connected to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an
adjustable ramp to pin 3.
Copyright © 1995
Rev. 1.2a 10/25 7
PRODUCT DATABOOK 1996/1997
UC184xA/284xA/384xA
CURRENT MODE PWM CONTROLLER
P R O D U C T I O N D A T A S H E E T
T Y P I C A L A P P L I C AT I O N C I R C U I T S (continued)
TI MBR735
4.7kW 1W
16V
1N4935
2 VFB VCC
2.5kW
150kW 27kW
1 COMP
OUT 6
IRF830
3.6kW 100pF
8 VREF 1kW
CUR
10kW 3
SEN
470pF 0.85kW
4 RT/CT GND
0.01µF .0022µF 5
ISOLATION
BOUNDARY
SPECIFICATIONS
Input line voltage: 90VAC to 130VAC * This circuit uses a low-cost feedback scheme in which the DC
Input frequency: 50 or 60Hz voltage developed from the primary-side control winding is
Switching frequency: 40KHz ±10% sensed by the UC3844A error amplifier. Load regulation is
Output power: 25W maximum therefore dependent on the coupling between secondary and
Output voltage: 5V +5% control windings, and on transformer leakage inductance.
Output current: 2 to 5A
Line regulation: 0.01%/V
Load regulation: 8%/A*
Efficiency @ 25 Watts,
VIN = 90VAC: 70%
VIN = 130VAC: 65%
Output short-circuit current: 2.5Amp average
Copyright © 1995
8 Rev. 1.2a 10/25