Advanced VLSI Design CMOS Basics CMPE 640

MOS: Metal Oxide Semiconductor

Transistors are built on a Silicon (semiconductor) substrate.

Pure silicon has no free carriers and conducts poorly.

Dopants are added to increase conductivity: extra electrons (n-type) or extra holes (p-type)

MOS structure created by superimposing several layers of conducting, insulating and tran-
sistor-forming materials.

Metal gate has been replaced by polysilicon or poly in modern technologies.

There are two types of MOS transistors:

nMOS : Negatively doped silicon, rich in electrons.

pMOS : Positively doped silicon, rich in holes.

CMOS: Both type of transistors are used to construct any gate.

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Advanced VLSI Design CMOS Basics CMPE 640

nMOS and pMOS

Four terminal devices: Source, Gate, Drain, body (substrate, bulk).

Source Gate Drain

Polysilicon
Thin
W Oxide SiO2
Source Gate Drain
L
nMOS n+ n+

n+ n+ p bulk Si
p substrate

Source Gate Drain

Polysilicon
SiO2
pMOS

p+ p+

n bulk Si

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Advanced VLSI Design CMOS Basics CMPE 640

CMOS Inverter Cross-Section

Cadence Layer's for AMI 0.6mm technology

p-substrate contact (cc) m1-m2 contact (via) p-diffusion contact (cc)

(source)
metal2 metal1
n-diffusion contact (cc) n-substrate contact (cc)
(source) (Out)
glass(insulator)
VDD
GND
layer #3
layer #2
layer #1
p+ n+ n+ p+ p+ n+
(pactive) (drains)
n-well (nwell)
(nactive)

p substrate (black background)

n-transistor polysilicon gate (poly ) p-transistor

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Advanced VLSI Design CMOS Basics CMPE 640

CMOS Cadence Layout

Cadence Layout for the inverter on previous slide

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Advanced VLSI Design CMOS Basics CMPE 640

MOS Transistor Switches

We can treat MOS transistors as simple on-off switches with a source (S), gate (G) (con-
trols the state of the switch) and drain (D).

1 represents high voltage, VDD (5V, 3.3V, 1.8V, 1.2V, <=1.0V today, .....)
0 represent low voltage - GND or VSS. (0V for digital circuits)

g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

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Advanced VLSI Design CMOS Basics CMPE 640

Signal Strengths

Signals such as 1 and 0 have strengths, measures ability to sink or source current
VDD and GND Rails are the strongest 1 and 0

Under the switch abstraction, G has complete control and S and D have no effect.
In reality, the gate can turn the switch on only if a potential difference of at least Vt
exists between the G and S.
We will look at Vt in detail later on in the course.

Thus signal strengths are related to Vt and therefore p and n transistors produce signals with
different strengths

Strong 1: VDD, Strong 0: GND, Weak 1 :(~VDD -Vt) and Weak 0 :(~GND + Vt).

G 1 nMOS 1 G 0 pMOS 0
S D S D
0 1 0 1
*** Strong 0*** Weak 1 Weak 0 *** Strong 1***

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Advanced VLSI Design CMOS Basics CMPE 640

CMOS Inverter

Vdd A O
P1
A Out
A O
N1 0 1
1 0
CMOS Inverter
THE CONFIGURATION BELOW FOR A BUFFER IS NOT A GOOD IDEA. WHY?

A Vdd

P1 N1 BAD IDEA
Out

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Advanced VLSI Design CMOS Basics CMPE 640

NAND and NOR CMOS Gates

Vdd
A B C
A
A P1 P2 B B
C
0 0 1
Out 0 1 1
N2
1 0 1

N1 1 1 0

Vdd
A A B C
P1 A
C
B 0 0 1
P2 B
Out 0 1 0
1 0 0
N1 N2
1 1 0

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Advanced VLSI Design CMOS Basics CMPE 640

Pass Transistor

The off-state of a transistor creates a high impedance condition Z at the drain.

No current flows from source to drain. So transistors can be used as switches.

g g=0 Input g = 1 Output

s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g g=0 Input Output

g=0
s d 0 degraded 0
s d
g=1
g=0
s d strong 1

However, as we previously discussed this will produce degraded outputs, if only one
transistor is used as a switch.

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Advanced VLSI Design CMOS Basics CMPE 640

Transmission Gates
A One pMOS and one nMOS in parallel.
Note that neither transistor is connected to VDD or GND.
P1
In Out A and A control the transmission of a signal on In to Out.
N1
A Transmission gates act as tristate buffers.

Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb

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Advanced VLSI Design CMOS Basics CMPE 640

Transmission Gate Application: Select Mux

Transmission Gate 2-to-1 MUX

Select
A
In Out
Select Out

Select B

VDD
Truth Table for 2-to-1 MUX
Select Out Select
0 B
1 A

Out = A.S + B.S

How many transistors are required to implement this using CMOS gates?

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Advanced VLSI Design CMOS Basics CMPE 640

D Latch

Positive CLK CLK

level-sensitive
latch
D

Latch
D Q
Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

If CLK is unavailable one extra inverter

CLK
needed to generate it using CLK

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Advanced VLSI Design CMOS Basics CMPE 640

D Flip-Flop
Positive CLK
edge-triggered
CLK
flip-flop
a.k.a D

Flop
master-slave D Q
flip-flop Q

CLK CLK
CLK QM
D Q
CLK CLK CLK Master CLK CLK Slave
Latch

Latch

QM
D Q
CLK CLK
Master Slave

If CLK is unavailable one extra inverter needed to generate it using CLK

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Advanced VLSI Design CMOS Basics CMPE 640

D Flip-Flop Operation

QM Q
D

QM follows D, Q is latched
CLK = 0

QM
D Q

QM transferred to Q, QM latched
CLK = 1

CLK
Positive
edge-triggered
D
flip-flop

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Advanced VLSI Design CMOS Basics CMPE 640

More CMOS Gates

Vdd

B
P1

Vdd

A P2 Out
N2

N1

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Advanced VLSI Design CMOS Basics CMPE 640

And More CMOS Gates

Out

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Advanced VLSI Design CMOS Basics CMPE 640

And More CMOS Gates

Vdd

P2 P1 P3

P4
OAI
A N1
B N2
C
D N3 N4

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