Digital VLSI Design

Lecture 4:
Standard Cell Libraries
Semester A, 2016-17
Lecturer: Dr. Adam Teman

27 November 2016

Disclaimer: This course was prepared, in its entirety, by Adam Teman. Many materials were copied from sources freely available on the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or overlooked. If you feel that a picture, graph, or code example has been copied from you and either needs to be cited or removed,
please feel free to email adam.teman@biu.ac.il and I will address this as soon as possible.
 Motivation
• A standard cell library is a collection of well defined and appropriately
characterized logic gates that can be used to implement a digital design.
• Similar to LEGO, standard cells must meet predefined specifications to
be flawlessly manipulated by synthesis, place, and route algorithms.
• Therefore, a standard cell library is
delivered with a collection of files
that provide all the information needed
by the various EDA tools.

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 Example
• Inverter standard
cell layout
• Pay attention to:
• Cell height
• Cell width
• Voltage rails
• Well definition
• Pin Placement
• Metal layers
• PR Boundary

http://www.csee.umbc.edu/~tinoosh/cmpe641/
Ideally, Standard Cells should be routed entirely in M1 !
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 1 2 5
3 4
Motivation Library Other
LEF LIB
Contents Contents

Standard Cell Library Contents

 What cells are in a standard cell library?
• Combinational logic cells (NAND, NOR, INV, etc.):
• Variety of drive strengths for all cells.
• Larger variety of buffers and inverters.
• “Clock cells” with balanced rise and fall delays.
• Complex cells (AOI, OAI, etc.)
• Cells with Fan-In <= 4 AND-OR
INVERT
• Delay cells
(AOI)
• Level Shifters
• ECO Cells
• Sequential Cells:
• Many types of flip flops: pos/negedge, set/reset, Q/QB, enable
• Latches
• Integrated Clock Gating cells
• Scan enabled cells for ATPG.
• Other Cells:
• Fillers, Tap cells, Antennas, DeCaps, EndCaps, Tie Cells
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 Multiple Drive Strengths and VTs
• Multiple Drive Strength
• Each cell will have various sized output stages.
• Larger output stage  better at driving fanouts/loads.
• Smaller drive strength  less area, leakage, input cap.
• Often called X2, X3, or D2, D3, etc.

• Multiple Threshold (MT-CMOS)

• A single additional mask can provide more or less doping
in a transistor channel, shifting the threshold voltage.
• Most libraries provide equivalent cells with three VTs:
SVT, HVT, LVT to tradeoff speed vs. leakage.
• All threshold varieties have same footprint and therefore
can be swapped without any placement/routing iterations.

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 Clock Cells
• General standard cells are optimized for speed.
• That doesn’t mean they’re balanced…  tp,LH  tp,HL 
min tpd  min    tp,LH  tp,HL
• This isn’t good for clock nets…  2 
• Unbalanced rising/falling delays will result in unwanted skew.
• Special “clock cells” are designed with balanced rising/falling delays to
minimize skew.
• These cells are usually less optimal for data and so should not be used.
• In general, only buffers/inverters should be used on clock nets
• But sometimes, we need gating logic.
• Special cells, such as integrated clock gates,
provide logic for the clock networks.

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 Sequentials
• Flip Flops and Latches, including
• Positive/Negative Edge Triggered
• Synchronous/Asynchronous Reset/Set
• Q/QB Outputs
• Enable
• Scan
• etc., etc.

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 Level Shifters
• Level shifter cells are placed between voltage domains to pass
signals from one voltage to another.
VDDH

• HL shifter INH OUTH

• Requires only one voltage
VDDH
• Single height cell VSS

OUTH

• LH shifter
• Needs 2 voltages VSS

• Often double height INL

VDDL

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 Filler and Tap Cells
• Filler cells Must be inserted in empty areas in rows
• Ensure well and diffusion mask continuity
• Ensure density rules on bottom layers
• Provide dummy poly for scaled technologies
• Sometimes, special cells are needed at the
boundaries of rows. These are known as “End Caps”
• Other fillers may include MOSCAPs between VDD
and GND for voltage stability. These are called “DeCAP cells”

• Well Taps needed to ensure local body voltage

• Eliminate latch-up
• No need to tap every single cell

• Back or forward biasing for performance/leakage optimization

• N-well voltage different from VDD
• Substrate or P-well (triple well process) voltage different from VSS
• Bias voltage routed as signal pin or special power net
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 Engineering Change Order (ECO) Cells
• An Engineering Change Order (ECO) is a very late
change in the design.
• ECOs usually are done after place and route.
• However, re-spins of a chip are often done without
recreating all-masks. This is known as a “Metal-Fix”.
• ECOs usually require small changes in logic.
• How can we do this after placement?
• Or worse – after tapeout???
• Solution – Spare (Bonus) Cells!
• Cells without functionality
• Cells are added during design (fill)
• In case of problems (after processing) new metal
and via mask  cells get their wanted functionality
• Cell combinations can create more complex functions
• Ex. And,nand,nor,xor,FF,mux,inv,..
• Special standard cells are used to differentiate from real cells.

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 My favorite word… ABSTRACTION!
• So, what is a cell?
• I guess that the detailed layout is sufficient to know (guess) anything and
everything about a standard cell.
• Or it would be easier, if we got the whole Open Access database of the cell…
• But do we really need to know everything?
• For example, does logic simulation need to know if your inverter is CMOS or
Pseudo-NMOS?
• And does a logic synthesizer need to know what type of transistors you used?
• No!
• To make life (and calculations) simpler, we will abstract away this info.
• Each tool will get only the data it really needs.

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 What files are in a standard cell library?
• Behavioral Views: Behavioral (.v)
• Verilog (or Vital) description used for simulation, logic equivalence.
• Physical Views: Abstract (.lef)
• Layout of the cells (GDSII format) for DRC, LVS, Custom Layout.
• Abstract of the cells (LEF format) for P&R, RC extraction. Layout (.gds)
• Transistor Level:
• Spice/Spectre netlist for LVS, transistor-level simulation. Spice (.spi, .cdl)
• Often provided both with parasitics (post-layout) and without.
• Timing/Power:
• Liberty files with characterization of timing and power for STA. Timing (.lib)

• Power Grid Views:

• Needed for IR Drop analysis.
• Others:
• Symbols for displaying the cells in various tools. Open Access (.oa)
• OA Libraries for easy integration with Virtuoso.

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 1 2 5
3 4
Motivation Library Other
LEF LIB
Contents Contents

Library Exchange Format (LEF)

 Library Exchange Format (LEF)
• Abstract description of the layout for P&R
• Readable ASCII Format.
• Contains detailed PIN information for
connecting.
• Does not include front-end of the line (poly,
diffusion, etc.) data.
• Contains blockages for DRC.

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 Library Exchange Format (LEF)

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 Technology LEF
• Technology LEF Files contain (simplified) information about
the technology for use by the placer and router:
• Layers and layer types.
• Sites (x and y grids of the library) – i.e., double height cells!
• Via definitions
LAYER MET1
• Design Rules TYPE ROUTING ;
PITCH 3.5 ;
• Parasitic and Antenna data. WIDTH 1.2 ;
SPACING 1.4 ;
DIRECTION HORIZONTAL ;
RESISTANCE RPERSQ .7E-01 ;
CAPACITANCE CPERSQDIST .46E-04 ;
END MET1

LAYER VIA
TYPE CUT ;
END VIA

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 VDD

Technology LEF W1

• Cell height is measured in Tracks W4

• A Track is one M1 pitch W3

• E.g., An 8-Track Cell has room for 8

W2
H

horizontal M1 wires.
• The more tracks, the wider the
transistors, the faster the cells. W1

• 7-8 low-track libraries for area

efficiency VSS

• 11-12 tall-track libraries for Parameter Symbol

Cell height (# tracks) H
performance, but have high leakage
Power rail width W1
• 9-10 standard-track libraries for a Vertical grid W2
reasonable area-performance tradeoff Horizontal grid W3
N-Well height W4
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 Technology LEF
Cell
Origin
• Cells must fit into a predefined grid
• The minimum Height X Width is called a
SITE.
PR
• Must be a multiple of the minimum X-grid Boundary
unit and row height.
• Cells can be double-height, for example. Horizontal
Grid
• Pins should coincide with routing tracks
• This enables easy connection of higher
Vertical
metals to the cell. Grid

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 1 2 5
3 4
Motivation Library Other
LEF LIB
Contents Contents

Liberty Timing Models (.lib)

 Liberty (.lib): Introduction
• How do we know the delay through a gate in a logic path?
• Running SPICE is way too complex.
• Instead, create a timing model that will simplify the calculation.
• Goal:
• For every timing arc, calculate: tpd
• Propagation Delay (tpd)
• Output transition (trise, tfall)
• Based on:
• Input net transition. tf
• Output Load Capacitance

Note that every .lib will provide timing/power/noise information for a single
corner, i.e., process, voltage, temperature, RCX, etc.
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 Liberty (.lib): General
library (nameoflibrary) {

• Timing data of standard cells is ... /* Library level simple and complex attributes */

provided in the Liberty format.

/* Cell definitions */
cell (cell_name) {
... /* cell level simple attributes */
• Library:
/* pin groups within the cell */
• General information common to pin(pin_name) {
all cells in the library. ... /* pin level simple attributes */

• For example, operating conditions, /* timing group within the pin level */
timing(){
wire load models, look-up tables ... /* timing level simple attributes */ }
• Cell: ... /* additional timing groups */

• Specific information about each } /* end of pin */

... /* more pin descriptions */
standard cell. } /* end of cell */
• For example, function, area. ... /* more cells */

• Pin: } /* end of library */

• Timing, power, capacitance,

leakage, functionality, etc.
characteristics of
each pin in each cell.
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 Liberty (.lib): Timing Models
• Non-Linear Delay Model (NLDM)
• Driver model:
• Ramp voltage source
• Fixed drive resistance lu_table_template(delay_template_5x5) {
• Receiver model: variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
• Min/max rise/fall input caps index_1 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
index_2 ("1000.0, 1001.0, 1002.0, 1003.0, 1004.0");
• Very fast }

• Doesn’t model cap variation during transition.

• Loses accuracy beyond 130nm cell (INVX1) {
pin(Y) {

tpd =f  tinput , Cload 

timing() {
tpd cell_rise(delay_template_5x5) {
values ( \
"0.147955, 0.218038, 0.359898, 0.922746, 1.76604", \
tf "0.224384, 0.292903, 0.430394, 0.991288, 1.83116", \
"0.365378, 0.448722, 0.584275, 1.13597, 1.97017", \
"0.462096, 0.551586, 0.70164, 1.24437, 2.08131", \
"0.756459, 0.874246, 1.05713, 1.62898, 2.44989"); }
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 Liberty (.lib): Timing Models
• Non-Linear Delay Model (NLDM)
• Delay calculation interpolation

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 Liberty (.lib): Timing Models
• Current Source Models (CCS, ECSM)
• Model a cell's nonlinear output
behavior as a current source
Courtesy: Cadence
• Driver model:
• Nonlinear current source
• Receiver model:
• Changing capacitance
• Requires many more values
• Requires a bit more calculation
• Essential under 130nm
• Within 2% of SPICE.

Courtesy: Synopsys
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 Liberty (.lib): Timing Models
• NLDM vs CCS/ECSM

Courtesy:
26 Synopsys
 Liberty (.lib): Wire Load Models
• How do you estimate the parasitics (RC) of a net
before placement and routing?
• Wire Load Models estimate the parasitics based on the fanout of a net.
library (myLib) {
wire_load(“WLM1”)
resistance: 0.0006 ; // R per unit length
capacitance: 0.0001 ; // C per unit length
area : 0.1 ; // Area per unit length
slope : 1.5 ; // Used for linear extrapolation
fanout_length(1, 0.002) ; // for fo=1, Lwire=0.002
fanout_length(2, 0.006) ; // for fo=2, Lwire=0.006
fanout_length(3, 0.009) ; // for fo=3, Lwire=0.009
fanout_length(4, 0.015) ; // for fo=4, Lwire=0.015
fanout_length(5, 0.020) ; // for fo=5, Lwire=0.020
fanout_length(6, 0.028) ; // for fo=6, Lwire=0.028
}
} /* end of library */

http://www.vlsi-expert.com/ Instead, try topographical synthesis!

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 1 2 5
3 4
Motivation Library Other
LEF LIB
Contents Contents

Other Contents of SC Library

 Other contents of SC Library
• Many other files and formats may be provided as part of a standard cell
library:
• GDS
• Verilog
• ATPG
• Power Grid Models
• OA Databases
• Spice Models
• etc.
• We will go over a real life example in the discussion.

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 Documentation and Datasheets
• So, are we just supposed to look through and see what the vendor
decided to provide us with?
• Yes!
• However they probably supplied some PDFs describing the library.
• And usually there are data sheets with numbers for each corner.

30 www.vlsi.ce.titech.ac.jp/kunieda/lecture
 And what about other IPs?
• All IPs will be provided as a library, including most of the views a
standard cell library will have.
• These are required for integration of the hard macros in the standard
design flow (simulation, synthesis, P&R, verification, etc.)
• Memories (SRAMs) are a special case, as they usually come with a
memory compiler that generates the particular memory cut the
designer requires.

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 Main References
• IDESA
• Synopsys
• Cadence
• Mississippi State
• Arizona State

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